Une forte exigence de robustesse s’est imposée dans tous les domaines d’application des composants de puissance. Dans ce cadre très contraint, seule une analyse fine des phénomènes liés directement ou indirectement aux défaillances peut garantir une maîtrise de la fiabilité des fonctions assurées par les nouveaux composants de puissance. Cependant, ces phénomènes impliquent des couplages entre des effets électriques, thermiques et mécaniques, rendant leur étude très complexe. Le recours à la modélisation multi-physique bien adaptée s’avère alors déterminant. Dans ce mémoire de thèse, nous proposons une méthodologie de modélisation électrique prenant en compte les effets de la température sur les phénomènes localisés qui initient une défaillance souvent fatale. En prévision de la simulation électrothermique couplée impliquant des transistors MOS de puissance, un modèle électrique thermosensible de ce composant et de sa diode structurelle a été développé. Corrélativement un ensemble de bancs expérimentaux a été mis en œuvre pour l’extraction des paramètres et pour la validation du modèle. Une attention particulière a été accordée à l’étude des phénomènes parasites qui pourraient survenir de manière très localisée suite à une répartition inhomogène de la température et à l’apparition de points chauds. Ainsi les fonctionnements limites en avalanche, avec le déclenchement du transistor bipolaire parasite et de son retournement ont été modélisés. Des bancs spécifiques pour la validation du modèle pour les régimes extrêmes ont été utilisés en prenant des précautions liées à la haute température. Enfin, Le modèle électrique thermosensible complet développé a été utilisé par la société Epsilon ingénierie pour faire des simulations électrothermiques du MOS de puissance en mode d’avalanche en adaptant le logiciel Epsilon-R3D / Strong demand for robustness has emerged in all areas of application of power components.Only a detailed analysis of phenomena related directly or indirectly to failures can ensure thereliability of the functions of the new power components. However, these phenomena involvethe coupling between electrical effects, thermal and mechanical, making their study verycomplex. The use of multi-physics modeling is well suited when determining. In this thesis,we propose a methodology for electrical modeling taking into account the effects of temperatureon the localized phenomena that initiate failure is often fatal. In preparation for thecoupled electro-thermal simulation involving MOS power transistors, an electric thermosensitivemodel of the MOS and its body diode has been developed. Correspondingly a set ofexperimental studies was implemented to extract the parameters and model validation. Particularattention was paid to the study of interference phenomena that could occur in a localizedresponse to an inhomogeneous distribution of temperature and hot spots. Thus the workingslimits avalanche, with the outbreak of parasitic bipolar transistor (snapback) and its reversalwere modeled. Benches specific validations of the model for harsh switching conditions wereused by taking precautions related to high temperature. Finally, the complete thermal electricmodel developed was used by the company “EPSILON Ingénierie” for electro-thermal simulationof power MOS mode Avalanche Software adapting Epsilon-R3D.

Le nitrure de gallium (GaN) est un matériau semi-conducteur de la famille III-V à large bande interdite directe, ayant des propriétés électriques et thermiques intéressantes. Grâce à sa large bande interdite, son fort champ de claquage et sa forte vitesse de saturation, il est très convoité pour la réalisation de dispositifs électroniques de puissance et de hautes fréquences pouvant fonctionner à haute température. De plus, grâce au caractère direct de sa bande interdite et son pouvoir d’émission à faible longueur d’onde, il est aussi avantageux pour la réalisation de dispositifs optoélectroniques de hautes performances en émission ou en détection tels que les DELs, les lasers ou les photo-détecteurs. Les difficultés de son élaboration, les problèmes d’inefficacités du dopage p et les densités élevées de défauts cristallins dans les couches épitaxiées ont constitué pendant longtemps des handicaps majeurs au développement des technologies GaN. Il a fallu attendre le début des années 1990 pour voir apparaître des couches épitaxiales de meilleures qualités et surtout pour obtenir un dopage p plus efficace [I. Akasaki, 2002]. Cet événement a été l’une des étapes clés qui a révolutionnée cette technologie et a permis d’amorcer son intégration dans le milieu industriel. Malgré l’avancé rapide qu’a connu le GaN et son potentiel pour la réalisation de sources optoélectroniques de haute efficacité, certains aspects de ce matériau restent encore mal maîtrisés, tels que la réalisation de contacts ohmiques avec une faible résistivité, ou encore le contrôle des interfaces métal/GaN et isolant/GaN. Les hétérostructures isolant/GaN sont généralement caractérisées par la présence d’une forte densité d’états de surface (D[indice inférieur it]). Cette forte D[indice inférieur it], aussi rapportée sur GaAs et sur d’autres matériaux III-V, détériore considérablement les performances des dispositifs réalisés et peut induire l’ancrage (‘pinning’) du niveau de Fermi. Elle constitue l’un des freins majeurs au développement d’une technologie MIS-GaN fiable et performante. Le but principal de ce projet de recherche est l’élaboration et l’optimisation d’un procédé de passivation du GaN afin de neutraliser ou minimiser l’effet de ses pièges. Les conditions de préparation de la surface du GaN avant le dépôt de la couche isolante (prétraitement chimique, gravure, prétraitement plasma etc.), les paramètres de dépôt de la couche diélectrique par PECVD (pression, température, flux de gaz, etc.) et le traitement post dépôt (tel que le recuit thermique) sont des étapes clés à investiguer pour la mise au point d’un procédé de passivation de surface efficace et pour la réalisation d’une interface isolant/GaN de bonne qualité (faible densité d’états de surface, faible densité de charges fixes, bonne modulation du potentiel de surface, etc.). Ceci permettra de lever l’un des verrous majeurs au développement de la technologie MIS-GaN et d’améliorer les performances des dispositifs micro- et optoélectroniques à base de ce matériau. Le but ultime de ce projet est la réalisation de transistors MISFETs ou MIS-HEMTs de hautes performances sur GaN.

Les mémoires non-volatiles à grille flottante sont utilisées pour le stockage d'information sous la forme d'une charge électrique contenue dans la grille flottante d'un transistor. Le comportement de ces dispositifs mémoire est fortement lié aux propriétés de leur oxyde tunnel, qui permet à la fois le passage de cette charge lors d'opérations de programmation ainsi que sa rétention en l'absence d'alimentation électrique. Au cours de ce travail, des mesures de courant tunnel ont été réalisées sur des capacités semiconducteur-oxyde-semiconducteur de grande surface représentatives de la zone d'injection des cellules mémoire. L'application de pulses courts sur la grille de ces structures de test, au cours desquels le courant peut être mesuré en temps réel, a permis de mettre en évidence les principales propriétés transitoires et stationnaires pouvant affecter le fonctionnement des dispositifs mémoire. L'effet de la dégradation des oxydes tunnel, qui impacte le comportement des cellules mémoire lors des opérations de programmation et de la rétention, a été observé et interprété dans le cas d'un stress à tension constante. Les résultats obtenus sur les capacités de grande surface ont pu être utilisés dans le cadre d'une modélisation de cellules EEPROM. / Floating gate non-volatile memory devices are used to store data under the form of an electric charge contained in the floating gate of a transistor. The behavior of these memory devices is strongly linked to the properties of their tunnel oxide, which allows the transit of this charge during write/erase operations as well as its retention while the transistor is not polarized. During this work, tunneling current measurements have been performed on large area semiconductor-oxide-semiconductor capacitors that are representative of the injection zone of memory cells. The application of short pulses to the gates of these test structures, during which the current can be measured as a function of time, allowed the observation of the main transient and steady-state properties that can affect the functioning of memory devices, The effect of tunnel oxide degradation, which impacts the behavior of memory cells during write/erase operations as well as data retention, has been observed and interpreted in the case of a constant voltage stress. The results obtained on large area capacitors have been used to model EEPROM cells.

O projeto de amplificadores de baixo ruído (LNA) aparenta ser um trabalho simples pelos poucos componentes ativos e passivos que o compõe, porém a alta correlação entre os seus parâmetros de projeto dificulta muito esse trabalho. Esta dissertação apresenta uma proposta para contornar essa dificuldade: o uso de algoritmos metaheurísticos, em particular algoritmos genéticos e simulated annealing. Algoritmos metaheurísticos são técnicas avançadas que emulam princípios físicos ou naturais para resolver problemas com alto grau de complexidade. Esses algoritmos estão emergindo nos últimos anos porque têm mostrado eficiência e eficácia. São feitos neste trabalho os projetos de três LNAs, dois (LNA1 e LNA2) para sistemas com arquitetura homódine (LNA com carga capacitiva) e um (LNA3) para sistemas com arquitetura heteródine (LNA com carga resistiva) utilizando-se algoritmos genéticos e simulated annealing (recozimento simulado). Apresenta-se inicialmente a análise detalhada da configuração escolhida para os projetos (fonte comum cascode com degeneração indutiva FCCDI). A frequência de operação dos LNAs é 1,8 GHz e a fonte de alimentação de 2,0 V. Para o LNA1 e o LNA2 se atingiu uma figura de ruído de 2,8 dB e 3,2 dB, consumo de potência de 6,8 mW e 2,7 mW e ganho de tensão de 22 dB e 24 dB, respectivamente. Para LNA3 se atingiu uma figura de ruído de 3,5 dB, consumo de potência de 7,8 mW e ganho de tensão de 15,5 dB. Os resultados obtidos e comparações feitas com LNAs da literatura demonstram viabilidade e eficácia da aplicação de algoritmos metaheurísticos no projeto de LNA. Neste trabalho utilizaram-se as ferramentas ELDO (simulador de circuitos elétricos), versão 2009.1 patch1 64 bits, ASITIC (para projetar e simular os indutores), versão 03.19.00.0.0.0 e MATLAB (o toolbox fornece os algoritmos metaheurísticos), versão 7.9.0.529 R2009b. Além disso, os projetos foram desenvolvidos na tecnologia CMOS 0,35 m da AMS (Austria Micro Systems). / The design of low noise amplifiers (LNA) seems to be a simple work because the small number of active and passive device that they are composes, nevertheless the high trade off of LNA parameters complicates very much the work. This research presents a proposal to contour act the obstacle: to use metaheuristic algorithms, in special genetic algorithms and simulated annealing. The metaheuristic algorithms are advanced techniques that emulate physics or natural principles to solve problems with high grade of complexity. They have been emerging in the last years because they have shown effectiveness and efficiency. In this dissertation were designed three LNAs using genetic algorithms and simulated annealing: two (LNA1 and LNA2) to homódine architecture (LNA with capacitive load) and one (LNA3) to heteródine architecture (LNA with resistive load). First it is show the detailed analysis of configuration chosen to the designs (common source cascode with inductive degeneration). The operation frequency is 1.8 GHz and power supply is 2.0 V for all LNAs. LNA1 and LNA2 reached a noise figure of 2.8 dB and 3.2 dB, a dissipation power of 6.8 mW and 2.7 mW, and a voltage gain of 22 dB and 24 dB respectively. LNA3 reached 3.5 dB of noise figure, 7.8 mW of dissipation power, and 15.5 dB of voltage gain. The results obtained and the comparisons with LNAs from the literature demonstrate that the metaheuristic algorithms show efficiency and effectiveness in the design of LNA. This study was developed with the help of the tools ELDO (electric circuit simulator) version 2009.1 patch1 64 bits, ASITIC (to design and simulate the inductors) version 03.19.00.0.0.0, and MATLAB (the toolbox provides the metaheuristic algorithms) version 7.9.0.529 R2009b. Furthermore, the designs were developed on CMOS 0.35 AMS (Austria Micro Systems) technology.

Neste trabalho foram fabricados diodos túnel MOS Al/SiOxNy/Si(p) e TiN/SiOxNy/Si(p) com áreas de 300µm x 300?m e de 700?m x 700µm. Para o crescimento do oxinitreto de silício (SiOxNy), como dielétrico de porta, foi utilizado um forno térmico junto com um aparato de quartzo para processamento de apenas uma lâmina por vez. Foi empregada uma temperatura de processamento de 850°C e fluxos de gases ultrapuros ajustados na proporção em volume de 5N2 : 1O2 (2 l/min. de N2 e 0,4 l/min. de O2). Foi constatado que a nitretação térmica rápida do silício introduz armadilhas no dielétrico de porta de duas naturezas: a) armadilhas do tipo K na interface dielétrico-silício devido à existência de ligações Si?N que podem armazenar elétron, lacuna ou ficar em um estado neutro e b) armadilhas geradas devido à quebra das cadeias Si-O-Si durante a oxinitretação. As armadilhas criadas durante a nitretação térmica rápida, tanto na interface como no corpo, influíram no mecanismo de tunelamento através do dielétrico de porta que foi predominantemente do tipo tunelamento assistido por armadilhas (TAT). A partir da característica J-V típica de diodos túnel MOS com porta de Al, verificou-se para VG =-1V que os níveis de densidade de corrente atingem 64mA/cm2, valor que é superior aos valores obtidos para óxidos de porta com espessura na faixa de 1-1,5nm na literatura apesar do nosso dielétrico apresentar espessura média de 2,1nm. Tal fato foi uma evidência clara de que um outro mecanismo diferente de tunelamento direto ocorreu no oxinitreto de silício crescido. Nos diodos túnel MOS, com porta de Al, observou-se a presença de dois picos característicos na curva C-V, o primeiro deles em tensão de porta mais negativa com uma fenomenologia que permitiu extrair a tensão de faixa plana (VG = VFB). O segundo pico na característica C-V do diodo MOS com porta de Al ocorreu em uma tensão menos negativa VG=VK= -0,78V o que foi atribuído à uma capacitância devido às armadilhas de interface Si?N localizadas dentro da banda proibida junto à interface silício-dielétrico e cerca de 0,16eV abaixo do nível de energia intrínseco do semicondutor. Para tensões de porta positivas, foi também constatada uma clara dependência da densidade de corrente com a intensidade da luz (0,05W/cm2 e 0,1W/cm2) devido à taxa de geração dentro do semicondutor. Da modelagem do tunelamento de corrente na região de depleção, verificou-se que a largura de depleção resultou sistematicamente maior do que a largura de depleção de equilíbrio, fato que permitiu concluir que o diodo túnel MOS entra em um estado de depleção profunda quase estacionária induzida pela corrente de tunelamento que atravessa o dielétrico de porta. / In this work Al/ SiOxNy/Si(p) and TiN/SiOxNy/Si(p) MOS tunnel diodes were fabricated with areas of 300µm x 300µm x 700µm and 700µm. For the growth of silicon oxynitrides (SiOxNy) as gate dielectrics, it was used a heating furnace with a quartz apparatus for single wafer processing. It was employed a processing temperature of 850°C and ultrapure gas flows adjusted in a volume proportion of 5N2:1O2 (2 l/min of N2 and 0.4l/min of O2). It has been found that the rapid thermal nitridation of silicon introduces traps in the gate dielectrics of two natures: a) K-type traps at the dielectric-silicon interface due to Si?N bonds that can store electrons or holes or can stay in a neutral state and b) traps generated from broken Si-O-Si chains during the oxynitridation. The traps created at the interface and in the oxynitride bulk, both influenced the tunneling mechanism through the gate dielectrics, which was predominantly a trap assisted tunneling (TAT). For VG = -1V, the current density of the Al-gate MOS tunnel diodes reached 64mA/cm2, a value which is higher than the reported values obtained for gate oxides with thickness in the range of 1-1.5nm in spite of our oxynitride thickness is 2.1nm. This fact is a clear evidence that another mechanism, different from direct tunneling, occurred in the silicon oxynitrides. For Al-gate MOS tunnel diodes, it was observed the presence of two characteristic peaks in the C-V curve: the first for more negative gate voltage with a phenomenology that allows one to extract the flat band voltage (VG = VFB). The second peak was located at a gate voltage VG = VK = -0.78V corresponding to a depletion regime and its maximum of capacitance was attributed to Si?N interface traps located in the bandgap at the silicon-dielectric interface, about 0.16eV below the intrinsic energy of the semiconductor. It was also observed a clear dependence of the current density against the light intensity (0.05/cm2 to 0.10W/cm2) due to the carriers generation inside the semiconductor. From the modeling of the current mechanism through the depletion region, it was found that the depletion width was systematically higher than the depletion width at the thermal equilibrium regime, a fact showing that the MOS tunnel diode achieves an almost stationary deep depletion, which is feeded by the tunneling current through the gate dielectrics.

Neste trabalho foram fabricados diodos túnel MOS Al/SiOxNy/Si(p) e TiN/SiOxNy/Si(p) com áreas de 300µm x 300?m e de 700?m x 700µm. Para o crescimento do oxinitreto de silício (SiOxNy), como dielétrico de porta, foi utilizado um forno térmico junto com um aparato de quartzo para processamento de apenas uma lâmina por vez. Foi empregada uma temperatura de processamento de 850°C e fluxos de gases ultrapuros ajustados na proporção em volume de 5N2 : 1O2 (2 l/min. de N2 e 0,4 l/min. de O2). Foi constatado que a nitretação térmica rápida do silício introduz armadilhas no dielétrico de porta de duas naturezas: a) armadilhas do tipo K na interface dielétrico-silício devido à existência de ligações Si?N que podem armazenar elétron, lacuna ou ficar em um estado neutro e b) armadilhas geradas devido à quebra das cadeias Si-O-Si durante a oxinitretação. As armadilhas criadas durante a nitretação térmica rápida, tanto na interface como no corpo, influíram no mecanismo de tunelamento através do dielétrico de porta que foi predominantemente do tipo tunelamento assistido por armadilhas (TAT). A partir da característica J-V típica de diodos túnel MOS com porta de Al, verificou-se para VG =-1V que os níveis de densidade de corrente atingem 64mA/cm2, valor que é superior aos valores obtidos para óxidos de porta com espessura na faixa de 1-1,5nm na literatura apesar do nosso dielétrico apresentar espessura média de 2,1nm. Tal fato foi uma evidência clara de que um outro mecanismo diferente de tunelamento direto ocorreu no oxinitreto de silício crescido. Nos diodos túnel MOS, com porta de Al, observou-se a presença de dois picos característicos na curva C-V, o primeiro deles em tensão de porta mais negativa com uma fenomenologia que permitiu extrair a tensão de faixa plana (VG = VFB). O segundo pico na característica C-V do diodo MOS com porta de Al ocorreu em uma tensão menos negativa VG=VK= -0,78V o que foi atribuído à uma capacitância devido às armadilhas de interface Si?N localizadas dentro da banda proibida junto à interface silício-dielétrico e cerca de 0,16eV abaixo do nível de energia intrínseco do semicondutor. Para tensões de porta positivas, foi também constatada uma clara dependência da densidade de corrente com a intensidade da luz (0,05W/cm2 e 0,1W/cm2) devido à taxa de geração dentro do semicondutor. Da modelagem do tunelamento de corrente na região de depleção, verificou-se que a largura de depleção resultou sistematicamente maior do que a largura de depleção de equilíbrio, fato que permitiu concluir que o diodo túnel MOS entra em um estado de depleção profunda quase estacionária induzida pela corrente de tunelamento que atravessa o dielétrico de porta. / In this work Al/ SiOxNy/Si(p) and TiN/SiOxNy/Si(p) MOS tunnel diodes were fabricated with areas of 300µm x 300µm x 700µm and 700µm. For the growth of silicon oxynitrides (SiOxNy) as gate dielectrics, it was used a heating furnace with a quartz apparatus for single wafer processing. It was employed a processing temperature of 850°C and ultrapure gas flows adjusted in a volume proportion of 5N2:1O2 (2 l/min of N2 and 0.4l/min of O2). It has been found that the rapid thermal nitridation of silicon introduces traps in the gate dielectrics of two natures: a) K-type traps at the dielectric-silicon interface due to Si?N bonds that can store electrons or holes or can stay in a neutral state and b) traps generated from broken Si-O-Si chains during the oxynitridation. The traps created at the interface and in the oxynitride bulk, both influenced the tunneling mechanism through the gate dielectrics, which was predominantly a trap assisted tunneling (TAT). For VG = -1V, the current density of the Al-gate MOS tunnel diodes reached 64mA/cm2, a value which is higher than the reported values obtained for gate oxides with thickness in the range of 1-1.5nm in spite of our oxynitride thickness is 2.1nm. This fact is a clear evidence that another mechanism, different from direct tunneling, occurred in the silicon oxynitrides. For Al-gate MOS tunnel diodes, it was observed the presence of two characteristic peaks in the C-V curve: the first for more negative gate voltage with a phenomenology that allows one to extract the flat band voltage (VG = VFB). The second peak was located at a gate voltage VG = VK = -0.78V corresponding to a depletion regime and its maximum of capacitance was attributed to Si?N interface traps located in the bandgap at the silicon-dielectric interface, about 0.16eV below the intrinsic energy of the semiconductor. It was also observed a clear dependence of the current density against the light intensity (0.05/cm2 to 0.10W/cm2) due to the carriers generation inside the semiconductor. From the modeling of the current mechanism through the depletion region, it was found that the depletion width was systematically higher than the depletion width at the thermal equilibrium regime, a fact showing that the MOS tunnel diode achieves an almost stationary deep depletion, which is feeded by the tunneling current through the gate dielectrics.

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In dieser Arbeit werden Speichertransistoren mit Oxid-Nitrid-Oxid-Speicherschicht und lokaler Ladungsspeicherung untersucht, die zur nichtflüchtigen Speicherung von Informationen genutzt werden. Charakteristisch für diese Transistoren ist, dass an beiden Enden des Transistorkanals innerhalb der Isolationsschicht Informationen in Form von Ladungspaketen unabhängig und getrennt voneinander gespeichert werden. Für das Auslesen, Programmieren und Löschen der Speichertransistoren werden die physikalischen Hintergründe diskutiert und grundlegende Algorithmen zur Implementierung dieser Operationen auf einer typischen Speicherfeldarchitektur aufgezeigt. Für Standard-MOS-Transistoren wird ein Kurzkanal-Schwellspannungsmodell abgeleitet und analytisch gelöst. Anhand dieser Modellgleichung werden die bekannten Kurzkanaleffekte betrachtet. Weiterhin wird ein Modell zur Berechnung des Drainstroms von Kurzkanaltransistoren im Subthreshold-Arbeitsbereich abgeleitet und gezeigt, dass sich die Drain-Source-Leckströme bei Kurzkanaltransistoren vergrößern. Die Erweiterung des Schwellspannungsmodells für Standard-MOS-Transistoren auf den Fall der lokalen Ladungsspeicherung innerhalb der Isolationsschicht erlaubt die Ableitung eines Schwellspannungsmodells für Oxid-Nitrid-Oxid-Transistoren mit lokaler Ladungsspeicherung. Dieses Modell gestattet die qualitative und quantitative Diskussion der Erhöhung der Schwellspannung durch die lokale Injektion von Ladungsträgern beim Programmiervorgang. Weiterhin ist es mit diesem Modell möglich, die Trennung der an beiden Kanalenden des Transistors gespeicherten Informationen beim Auslesevorgang qualitativ zu erklären und diese Bittrennung in Abhängigkeit von der Drainspannung zu berechnen. Für Langkanalspeichertransistoren wird eine analytische Näherungslösung des Schwellspannungsmodells angegeben, während das Kurzkanalverhalten durch die numerische Lösung der Modellgleichung bestimmt werden kann. Für Langkanalspeichertransistoren wird ein Subthreshold-Modell zur Berechnung des Drainstroms abgeleitet. Dieses Modell zeigt, dass sich die Leckströme von programmierten Speichertransistoren im Vergleich zu Standard-MOS-Transistoren gleicher Schwellspannung vergrößern. Die Ursache dieses Effekts, die Verringerung der Subthreshold-Steigung von Transistoren im programmierten Zustand, wird analysiert. Für einige praktische Beispiele wird die Anwendung der hergeleiteten Modellgleichungen beim Entwurf von Flash-Speichern demonstriert. / In this work, memory transistors with an oxide-nitride-oxide trapping-layer and local charge storage, which are used for non-volatile information storage, are examined. Characteristic for these transistors is an independent and separated storage of information by charge packages, located at both sides of the transistor channel, in the insulation layer. The physical backgrounds for reading, programming and erasing the memory transistors are discussed, and basic algorithms are shown for implementing these operations on a typical memory array architecture. For standard MOS-transistors a short channel threshold model is derived and solved analytically. By using these model equations, the known short channel effects are considered. Further, a model for calculating the drain current of short channel transistors in the subthreshold operation region is derived. This model is used to show the increase of drain-source leakage currents in short channel transistors. By extending the standard MOS-transistor threshold voltage model for local charge storage in the insulation layers, the derivation of a threshold voltage model for oxide-nitride-oxide transistors with local charge storage is enabled. This model permits the quantitative and qualitative discussion of the increase in threshold voltage caused by local injection of charges during programming. Furthermore, with this model, the separation of the information, which are stored at both sides of the transistor channel, in the read-out operation is explained qualitatively, and the bit separation is calculated dependent on the drain voltage. For long channel memory transistors an analytical approximation of the threshold voltage model is given, whereas the short channel behaviour can be determined by solving the model equation numerically. For long channel memory transistors, a subthreshold model for calculating the drain current is derived. This model shows the increase in leakage current of programmed memory transistors in comparision to standard MOS-transistors. The root cause of this effect, the reduced subthreshold swing of transistors in the programmed state, is analysed. The application of the derived model equations for the development of flash memories is demonstrated with some practical examples.

Aggressive scaling required to augment device performance has caused conventional electrode materials to approach their physical scaling limits. Alternative metal gate/high dielectric constant (MG/High-[kappa]) stacks have been implemented successfully in commercial devices and hold promise for further scaling based performance advances. Existing MG/High-[kappa] technology does not achieve a single metal n-MOS to p-MOS effective work function (EWF) tuning range suitable for bulk silicon (Si) device applications. Dual metal gates (DMGs) utilizing a separate metal for n-MOS and p-MOS electrodes increases the cost and complexity of fabrication. The research presented herein introduces a method by which the cost and complexity of MG/High-[kappa] device fabrication may be reduced. Innovative fin field effect transistors (FinFETs) incorporating 3 dimensional ultra thin body silicon on oxide (3-D UTB-SOI) technology display superior electrical characteristics compared to bulk Si devices at the nanometer (nm) dimension and require only a +/-200meV n-MOS to p-MOS EWF tuning range around the Si mid-gap. Single metals capable of achieving this +/-200meV EWF tuning range have been evaluated herein and the tuning mechanisms investigated and engineered to develop a single MG/High-[kappa] FinFET the fabrication complexity of which is reduced by 40%. More specifically, the research shows that the metal thickness of titanium nitride/hafnium silicon oxide (TiN/HfSiOx) gate stack may be engineered to achieve an n-MOS (thinner TiN) to p-MOS (thicker TiN) appropriate FinFET EWF tuning range. FinFETs may be fabricated by depositing a single p-MOS appropriate TiN thickness which may be selectively etched back to achieve thinner, n-MOS appropriate films. Similar electrical behavior is exhibited by etched back and as deposited TiN electrode FinFETs. The single metal etch back fabrication method removes many of the additional steps required for DMG fabrication and preserves the integrity of the MG/High-[kappa] interface between n-MOS and p-MOS devices. These advantages result in reduced fabrication complexity and improved reliability and reproducibility. / text

Les sols de montagne représentent d'importants réservoirs de carbone (C) potentiellement vulnérables aux changements climatiques et changements d'usage qui les affectent de manière amplifiée. Or la grande variabilité de ces milieux, leur faible accessibilité ainsi que le manque d'outils de mesure appropriés limitent nos connaissances qui restent aujourd'hui très fragmentaires en ce qui concerne les stocks, la chimie et la réactivité du carbone organique des sols (COS). Ces informations sont pourtant nécessaires pour appréhender l'évolution de ces sols et de leur C dans ce contexte de changements globaux. Les objectifs de ce travail de thèse étaient (i) d'accéder à une meilleure compréhension de la nature, de la stabilité et de la vulnérabilité du COS dans une mosaïque d'écosystèmes des Préalpes calcaires (massif du Vercors), (ii) de rechercher des outils de caractérisation rapides et fiables adaptés à l'étude et au suivi du COS à l'échelle du paysage, et enfin (iii) de proposer des indices pour l'évaluation et le suivi de la qualité des sols en milieu de montagne. Dans un premier temps, nous avons testé l'application de la pyrolyse Rock-Eval pour l'étude du COS à grande échelle sur un ensemble d'unités écosystémiques. Nous avons ensuite comparé la pyrolyse Rock-Eval à deux techniques classiques d'étude de la matière organique du sol (MOS) : le fractionnement granulodensimétrique de la MOS et la spectroscopie moyen infrarouge. Ces approches analytiques couplées nous ont permis de quantifier les stocks de C à l'échelle de la zone d'étude et d'expliquer la stabilité et la vulnérabilité du COS sous des angles variés. Les facteurs responsables des patrons observés dans les différentes unités écosystémiques sont discutés. Ce travail a également confirmé la pertinence de l'outil Rock-Eval pour répondre aux objectifs fixés. Parallèlement, des approches biologiques nous ont permis d'évaluer l'importance de la composante microbienne dans ces sols. Enfin, des indices évaluant le statut organique des sols (stockage de COS, fertilité des sols, vulnérabilité du COS) sont proposés pour constituer des outils de gestion et d'aide à la décision.