科学研究費補助金 研究種目:基盤研究(C) 課題番号:10650238 研究代表者:安田 仁彦 研究期間:1998-1999年度

Radio Frequency (RF) energy transfer is getting increasingly importance in new generations of wireless sensor networks and this trend is tremendously supported by the modern trends to Internet of things (IoT). This promising technology enables proactive energy replenishment for wireless devices. With RF energy, transmission long distances between the energy source and the receiver can be overbridged. The main challenge thereby is the power conversion efficiency from a low level RF input power to a Direct Current (DC) voltage which is able to supply the mobile system. For this purpose, a novel approach for RF DC conversion is proposed. It consists of a modified voltage multiplier RF DC converter circuit by incorporating an inductor at the input of the circuit, which generates an induced voltage able to boost the output circuit and improve the conversion efficiency. Analytical analysis of the novel approach has been carried out to determine the optimal value of the inductor to maximize the output power. The experimental investigations show that the proposed solution is able to improve significantly both the output voltage and the power conversion efficiency, compared to the state of the art, and this especially at low input power ranges, which are often the case. At -10 dBm input power, the modified voltage multiplier RF DC converter circuit can reach 1.71 V output voltage and 49.21 % power conversion efficiency for, respectively, 500 kΩ and 10 kΩ resistive loads. In order to validate the new proposal for the RF transfer system experimentally, microstrip meander line antennas and microstrip patch antenna arrays are designed for different ISM bands, where relevant requirements for RF energy transfer are respected. For each antenna a modified voltage multiplier RF DC converter circuit has been applied and the system is tuned to the corresponding resonant frequency to avoid mismatching. In this investigation several scenarios have been addressed, such as RF transmission energy, RF energy harvesting in Global System for Mobile (GSM) bands and Wireless Local Area Networks (WLAN) band are developed. Field test results show high performances of experimental results in comparison to the state of the art.:1 Introduction 2 Theoretical Background 3 State of the Art of RF Energy Transfer 4 Novel Approach for a RF DC Converter Circuit 5 Antennas Design 6 Experimental Verification at Specific Scenarios 7 Conclusion / Die RF-Energieübertragung (RF) gewinnt in neuen Generationen von drahtlosen Sensornetzen zunehmend an Bedeutung. Dieser Trend wird durch das Internet der Dinge (IoT) weiter unterstützt. Diese vielversprechende Technologie ermöglicht eine proaktive Energieversorgung für drahtlose Geräte. Mit RF-Energie können große Entfernungen zwischen der Energiequelle und dem Empfänger überbrückt werden. Die größte Herausforderung dabei ist der Wirkungsgrad, mit dem von einer niedrigen HF-Eingangsleistung in eine Gleichspannung (DC), mit welcher das mobile System versorgt wird, gewandelt wird. Zu diesem Zweck wird ein neuer Ansatz für einen RF-DC-Wandler vorgeschlagen. Er besteht aus einer modifizierten Spannungsvervielfacher-RF-DC-Wandlerschaltung, die eine Spule am Eingang der Schaltung integriert. Diese erzeugt eine induzierte Spannung, die in der Lage ist die Ausgangsschaltung zu verstärken und den Umwandlungswirkungsgrad zu verbessern. Analytische Untersuchungen zu diesem neuartigen Ansatz wurden durchgeführt, um den optimalen Wert der Spule zu bestimmen und die Ausgangsleistung zu maximieren. Die experimentellen Untersuchungen zeigen, dass die vorgeschlagene Lösung in der Lage ist, sowohl die Ausgangsspannung als auch den Wirkungsgrad der Leistungsumwandlung im Vergleich zum Stand der Technik deutlich zu verbessern. Dies gilt besonders für niedrige Eingangsleistungsbereiche, welche häufig vorkommen. Bei -10 dBm Eingangsleistung kann die modifizierte Spannungsvervielfacher-RF-DC-Wandlerschaltung 1.71 V Ausgangsspannung und 49.21 % Leistungswandlungswirkungsgrad für jeweils 500 kΩ und 10 kΩ ohmsche Last erreichen. Um das neue RF-Übertragungssystem experimentell zu validieren, werden Mikrostreifenmäanderlinienantennen und Mikrostreifen-Patch-Antennenarrays für verschiedene ISM-Bänder ausgelegt, wobei die relevanten Anforderungen an die RF-Energieübertragung eingehalten werden. Für jede Antenne wurde eine modifizierte Spannungsvervielfacher-HF-DC-Wandlerschaltung verwendet und das System auf die entsprechende Resonanzfrequenz abgestimmt, um Fehlanpassungen zu vermeiden. Dabei wurden mehrere Szenarien untersucht, wie z.B. RF-Energieübertragung, RF-Energiegewinnung aus GSM-Bändern und WLAN-Netzwerken. Die Feldtests zeigen eine hohe Leistungsfähigkeit der experimentellen Ergebnisse im Vergleich zum Stand der Technik.:1 Introduction 2 Theoretical Background 3 State of the Art of RF Energy Transfer 4 Novel Approach for a RF DC Converter Circuit 5 Antennas Design 6 Experimental Verification at Specific Scenarios 7 Conclusion

This thesis primarily deals with the concept of designing an antenna based device to harvest energy from Radio Frequency (RF) and using the harvested energy to sense the available Long Term Evolution (LTE) network in order for the Internet of Things (IoT) devices to connect to the network for the purpose of transmitting and receiving data. Secondarily the importance of this project is targeting how to conserve battery power in an IoT device and extend it’s lifetime. Research in the field of energy harvesting has been going on for a long time. Most of the researches concentrate on harvesting significant amount of energy to power up an entire device and so no one has ever thought of using the harvested RF energy to sense the availability of LTE network. This method of using antenna to sense network requires only a small amount of harvested energy. Due to this reason the proposed design works for a very low input received signal strength indicator (RSSI) as well, unlike higer RSSI required for other applications. The proposed design has three major sub-parts such as the (i) Antenna for the purpose of receiving the available ambient radio frequency. (ii) Matching circuit for the purpose of maximum power transfer between the antenna and the rectifier circuit. Finally (iii) rectifier which is used to convert the AC voltage into DC voltage. The device then measures the obtained voltage through the Analog to Digital Converter (ADC) pin in the Micro-Controlling Unit (MCU) available with the attached IoT device. The MCU then maps the harvested voltage into the corresponding analog voltage.Depending on the set threshold voltage the MCU can then advice whether or not to connect to the LTE network. The design implements matching circuit for the two LTE bands that are primarily in use in the European region i.e., band 3, 8 that work in 915, 1800 MHz frequency region respectively. In this way we can identify in which band the device is harvesting energy. The matching circuit also acts as a bandpass filter. For the design and production of the entire harvester device one needs adequate knowledge in the field of RF and Antennas and a high level knowledge in the field of electronics in order to run Simulations and to design Printed Circuit Boards (PCBs). Advanced Design Software (ADS) has been used to run all the simulations and Altium software for the design of PCBs. The final prototype is presented along with the casing and tested on the field in practical scenario. Antenna test chambers were used to test the performance of the antennas being used for the design. The prototype harvests RF energy and indicates whether or not to connect to the LTE network with the help of light emitting diode (LED). The uniqueness of the device is that it can detect signals as low as -110 dBm, this has been set as the threshold for the purpose of sensing LTE networks. / Denna avhandling behandlar primärt konceptet att använda antenner för att hämta energi från RF och att använda den insamlade energin för att känna av det tillgängliga LTE-nätverket för att IoT-enheterna ska kunna ansluta till nätverket för syftet med att överföra och ta emot data. Sekundärt Målet med av detta projekt är att spara batteri i en IoT-enhet och förlänga dess livslängd. Forskning inom området energiskörd har pågått under lång tid nu. De flesta av undersökningarna koncentrerar sig på att skörda betydande mängder energi för att driva en hel enhet och så ingen har någonsin tänkt på att använda den avkända RF-energin för att känna av tillgängligheten för LTE-nätverket. Denna metod för att använda antenn för att känna av nätverk kräver endast en liten mängd skördad energi. På grund av denna anledning fungerar den föreslagna designen även för en mycket låg ingång RSSI, till skillnad från högre RSSI som krävs för andra applikationer. Den föreslagna designen har tre huvuddelar, såsom (i) antennen för att ta emot den tillgängliga omgivande radiofrekvensen. (ii) Matchningskrets för maximal effektöverföring mellan antennen och likriktarkretsen. Slutligen (iii) likriktaren som används för att omvandla AC-spänningen till DC-spänning. Enheten mäter sedan den erhållna spänningen genom ADC-stiftet i MCU som finns tillgänglig med den anslutna IoT-enheten. MCU mappar sedan den genererade spänningen till motsvarande analoga spänning. Beroende på den inställda tröskelspänningen kan MCU sedan ge råd om att ansluta till LTE-nätverket eller inte. Konstruktionen implementerar matchningskrets för de två LTE-banden som primärt används i den europeiska regionen vilka är band 3, 7 som arbetar i 915 respektive 1800 MHz frekvensområdet. På så sätt kan vi identifiera i vilket band enheten hämtar energi i. Matchningskretsen fungerar också som ett bandpassfilter. För design och produktion av hela insamlingsenheten behöver man adekvat kunskap inom området RF och antenner och en hög nivå kunskap inom elektronikområdet för att kunna köra simuleringar och designa PCBs.ADS har använts för att köra alla simuleringar och Altium-mjukvara för design av PCBs. Den slutliga prototypen presenteras tillsammans med höljet och testas på fältet i praktiskt scenario. Antenntestkammare användes för att testa prestandan hos antennerna som användes för konstruktionen. Prototypen skördar RF-energi och indikerar om man ska ansluta till LTE-nätverket eller inte med hjälp av blinkande LED.Det unika med enheten är att den kan upptäcka signaler så låga som - 110 dBm, detta har satts som tröskel för avkänning LTE nätverk.

The multiple constant multiplication (MCM) operation is a fundamental operation in digital signal processing (DSP) and digital image processing (DIP). Examples of the MCM are in finite impulse response (FIR) and infinite impulse response (IIR) filters, matrix multiplication, and transforms. The aim of this work is minimizing the complexity of the MCM operation using common subexpression elimination (CSE) technique and redundant number representations. The CSE technique searches and eliminates common digit patterns (subexpressions) among MCM coefficients. More common subexpressions can be found by representing the MCM coefficients using redundant number representations. A CSE algorithm is proposed that works on a type of redundant numbers called the zero-dominant set (ZDS). The ZDS is an extension over the representations of minimum number of non-zero digits called minimum Hamming weight (MHW). Using the ZDS improves CSE algorithms' performance as compared with using the MHW representations. The disadvantage of using the ZDS is it increases the possibility of overlapping patterns (digit collisions). In this case, one or more digits are shared between a number of patterns. Eliminating a pattern results in losing other patterns because of eliminating the common digits. A pattern preservation algorithm (PPA) is developed to resolve the overlapping patterns in the representations. A tree and graph encoders are proposed to generate a larger space of number representations. The algorithms generate redundant representations of a value for a given digit set, radix, and wordlength. The tree encoder is modified to search for common subexpressions simultaneously with generating of the representation tree. A complexity measure is proposed to compare between the subexpressions at each node. The algorithm terminates generating the rest of the representation tree when it finds subexpressions with maximum sharing. This reduces the search space while minimizes the hardware complexity. A combinatoric model of the MCM problem is proposed in this work. The model is obtained by enumerating all the possible solutions of the MCM that resemble a graph called the demand graph. Arc routing on this graph gives the solutions of the MCM problem. A similar arc routing is found in the capacitated arc routing such as the winter salting problem. Ant colony optimization (ACO) meta-heuristics is proposed to traverse the demand graph. The ACO is simulated on a PC using Python programming language. This is to verify the model correctness and the work of the ACO. A parallel simulation of the ACO is carried out on a multi-core super computer using C++ boost graph library.

Development Finance Institutions (DFIs) have played a crucial role in moving socially responsibility considerations up on the private equity industry’s agenda. DFIs add a development impact criterion to traditional financial performance goals in the investment industry and play a catalytic role by mobilizing other investors. The gap in research regarding DFIs implications and significance in the investment community from a SRI perspective is evident. The development impact objective introduced by the DFIs is examined to understand its effects on fund managers’ decision-making and if it exists a trade-off between this objective and financial performance. An understanding of how DFIs control fund managers to act in accordance to their objective as well as how they determine compensation schemes to incentivize them to pursue high return on investments, is discussed in relation to the agency theory. Furthermore, stakeholder/shareholder consideration is examined in relation to the subject. The aim of this study is to examine how the behavior of fund managers is affected by the involvement of a DFI investor and try to add to the understanding of their significance as institutional investors in developing markets. Previous studies have been more focused on determining the financial performance of socially responsible investments by using very similar quantitative data collection methods. This thesis undertakes an in-depth approach with the purpose to understand the fund manager’s drives as well as how a DFI involvement affects the behavior and decision-making process.   This thesis undertook a qualitative research strategy and semi-structured interviews were used as the tool to understand the fund managers’ personals beliefs and perceptions of how the relationship with DFIs affect them. The selection criteria for the fund managers was that they needed to work in a fund in which a DFIs has invested. We also included DFI investors in order to understand their point of view. The interview was recorded, transcribed and later divided into themes in accordance with the thematic approach, following six steps. Our findings show that Development Finance Institutions plays an important role in emerging markets and affect fund manager behavior to a certain extent. They did not perceive a trade-off between financial performance goals and development impact objectives. We conclude that DFIs increase fund manager focus on ESG/SEE elements in the investment process. DFIs requirements and reporting obligations is used as a tool to ensure that the fund manager act in accordance to DFI objective. The fund managers were neither willing to sacrifice commercial return in favor of development impact. Lastly, the interest among the DFIs and commercial investors is fairly similar, hence reducing the conflict of interest between investors.

De plus en plus de constructeurs proposent des accélérateurs de calculs à base de circuits reconfigurables FPGA, cette technologie présentant bien plus de souplesse que le microprocesseur. Valoriser cette flexibilité dans le domaine de l'accélération de calcul flottant en utilisant les langages de description de circuits classiques (VHDL ou Verilog) reste toutefois très difficile, voire impossible parfois. Cette thèse a contribué au développement du logiciel FloPoCo, qui offre aux utilisateurs familiers avec VHDL un cadre C++ de description d'opérateurs arithmétiques génériques adapté au calcul reconfigurable. Ce cadre distingue explicitement la fonctionnalité combinatoire d'un opérateur, et la problématique de son pipeline pour une précision, une fréquence et un FPGA cible donnés. Afin de pouvoir utiliser FloPoCo pour concevoir des opérateurs haute performance en virgule flottante, il a fallu d'abord concevoir des blocs de bases optimisés. Nous avons d'abord développé des additionneurs pipelinés autour des lignes de propagation de retenue rapides, puis, à l'aide de techniques de pavages, nous avons conçu de gros multiplieurs, possiblement tronqués, utilisant des petits multiplieurs. L'évaluation de fonctions élémentaires en flottant implique souvent l'évaluation en virgule fixe d'une fonction. Nous présentons un opérateur générique de FloPoCo qui prend en entrée l'expression de la fonction à évaluer, avec ses précisions d'entrée et de sortie, et construit un évaluateur polynomial optimisé de cette fonction. Ce bloc de base a permis de développer des opérateurs en virgule flottante pour la racine carrée et l'exponentielle qui améliorent considérablement l'état de l'art. Nous avons aussi travaillé sur des techniques de compilation avancée pour adapter l'exécution d'un code C aux pipelines flexibles de nos opérateurs. FloPoCo a pu ainsi être utilisé pour implanter sur FPGA des applications complètes. / Due to their potential performance and unmatched flexibility, FPGA-based accelerators are part of more and more high-performance computing systems. However, exploiting this flexibility for accelerating floating-point computations by manually using classical circuit description languages (VHDL or Verilog) is very difficult, and sometimes impossible. This thesis has contributed to the development of the FloPoCo software, a C++ framework for describing flexible FPGA-specific arithmetic operators. This framework explicitly separates the description of the combinatorial functionality of an arithmetic operator, and its pipelining for a given precision, operating frequency and target FPGA.In order to be able to use FloPoCo for designing high performance floating-point operators, we first had to design the optimized basic blocks. We first developed pipelined addition architectures exploiting the fast-carry lines present in modern FPGAs. Next, we focused on multiplication architectures. Using tiling techniques, we proposed novel architectures for large multipliers, but also truncated multipliers, based on the multipliers found in modern FPGA DSP blocks. We also present a generic FloPoCo operator which inputs the expression of a function, its input and output precisions, and builds an optimized polynomial evaluator for the fixed-point evaluation of this function. Using this building block we have designed floating-point operators for the square-root and exponential functions which significantly outperform existing operators. Finally, we also made use of advanced compilation techniques for adapting the execution of a C program to the flexible pipelines of our operators.