Cobalt Ferrite has important, size-dependent magnetic properties. Consequently, an overview of particle size is important. Co-precipitation in air was the fabrication method used because it is comparatively simple and safe. The effects of three different reaction times including 1, 2, 3 hour(s) on particle size were compared. Also, the effectiveness of three different capping agents (Oleic Acid, Polyvinylpyrollidone (PVP), and Trisodium Citrate) in reducing aggregation and correspondingly particle size were examined. Using Welch’s analysis of variance (ANOVA) and the relevant post hoc tests, there was no significant difference (p=0.05) between reaction times of 1 hour and 2 hours, but there was a significant difference between reaction times of 2 hours and 3 hours. Potentially, because of increased coarsening for the 3 hour reaction time. PVP and Oleic Acid were shown to be effective in reducing aggregation; however, Citrate was not effective. Possibly, the synthesis procedure was inadequate.

Memristor is a novel passive electronic device and a promising candidate for new generation non-volatile memory and analog computing. Analog computing based on memristors has been explored in this study. Due to the lack of commercial electrical testing instruments for those emerging devices and crossbar arrays, we have designed and built testing circuits to implement analog and parallel computing operations. With the setup developed in this study, we have successfully demonstrated image processing functions utilizing large memristor crossbar arrays. We further designed and experimentally demonstrated the first memristor based field programmable analog array (FPAA), which was successfully configured for audio equalizer and frequency classifier demonstration as exemplary applications of such memristive FPAA (memFPAA).

Over the past few years, the size of semiconductor devices has been shrinking whereas the density of transistors has exponentially increased. Thus, thermal management has become a serious concern as device performance and reliability is greatly affected by heat. An understanding of thermal transport properties at device level along with predictive modelling can lead us to design of new systems and materials tailored according to the thermal conductivity. In our work we first review different models used to calculate thermal conductivity and examine their accuracy using the experimentally measured thermal conductivity for Si. Our results suggest that empirically calculated rates used in thermal conductivity calculations do not capture the scaling behavior for three phonon scattering mechanism properly. This directly affects the estimation of the thermal conductivity and therefore we need to capture them more accurately. Also, we observe that at low temperature the Callaway and the improved Callaway model show good agreement where boundary scattering is dominant, whereas at high temperature iterative and RTA models show good agreement where three-phonon scattering is dominant. Therefore, their lies a need for a model which can characterize K properly at low and high temperature. Second, we then calculate the three phonon scattering rates using first-principles and combine them into the Callaway model. Through our work we successfully build a hybrid model which can be used to describe thermal conductivity of Si for a temperature range of 10K to 425K which captures the thermal conductivity accurately. We also show that in case of Si the improved Callaway model and Callaway model both perform equally well.

With the scaling of technology nodes, modern CMOS integrated circuits face severe fundamental challenges that stem from device scaling limitations, interconnection bottlenecks and increasing manufacturing complexities. These challenges drive researchers to look for revolutionary technologies beyond the end of CMOS roadmap. Towards this end, a new nanoscale 3-D computing fabric for future integrated circuits, Skybridge, has been proposed [1]. In this new fabric, core aspects from device to circuit style, connectivity, thermal management and manufacturing pathway are co-architected in a 3-D fabric-centric manner. However, the Skybridge fabric uses only n-type transistors in a dynamic circuit style for logic and memory implementations. Therefore, it requires complicated clocking schemes to overcome signal monotonicity associated with cascading dynamic logic gates. For Skybridge’s large-scale circuits, the dynamic circuit style requires cascaded stages to be micro-pipelined, which results in large number of buffers used for storing minterms causing significant overhead in terms of area and power. Moreover, implementation of logic is limited to NAND or AND-of-NAND based logic expressions, which does not always result in compact circuits. In this work, we propose an extension of original Skybridge fabric, called NP-Dynamic-Skybridge, to solve these challenges by using both n-and p-type transistors in an innovative circuit style. Here, every stage in a given circuit is implemented by either n-type or p-type dynamic logic. Cascading n- and p-type dynamic logic effectively avoids signal monotonicity problem, and allows combinational-like circuit implementation. This helps to simplify the clocking scheme for cascaded logics requiring only one set of global precharge and evaluate clock signals. And also it expands the degree of expressing logic enabling expressions such as NOR, OR-of-NORs, in addition to those previously mentioned. Furthermore, the number of pipeline stages is significantly reduced for a given logic function, and buffer requirements are less compared with Skybridge 3D fabric thus improving on area and power metrics. Initial evaluation for NP-Dynamic-Skybridge’s 4-bit carry look-ahead adder shows up to 2x density benefits over Skybridge 3-D fabric and at least 17% power/throughput benefit.

Hardware implementations of artificial neural networks (ANNs) have become feasible due to the advent of persistent 2-terminal devices such as memristor, phase change memory, MTJs, etc. Hybrid memristor crossbar/CMOS systems have been studied extensively and demonstrated experimentally. In these circuits, memristors located at each cross point in a crossbar are, however, stacked on top of CMOS circuits using back end of line processing (BOEL), limiting scaling. Each neuron’s functionality is spread across layers of CMOS and memristor crossbar and thus cannot support the required connectivity to implement large-scale multi-layered ANNs. This work proposes a new fine-grained 3D integrated circuit technology for ANNs that is one of the first IC technologies for this purpose. Synaptic weights implemented with devices are incorporated in a uniform vertical nanowire template co-locating the memory and computation requirements of ANNs within each neuron. Novel 3D routing features are used for interconnections in all three dimensions between the devices enabling high connectivity without the need for special pins or metal vias. To demonstrate the proof of concept of this fabric, classification of binary images using a perceptron-based feed forward neural network is shown. Bottom-up evaluations for the proposed fabric considering 3D implementation of fabric components reveal up to 19x density, 1.2x power benefits when compared to 16nm hybrid memristor/CMOS technology.

Quantum-Dot Cellular Automata (QCA) is currently being investigated as an alternative to CMOS technology. There has been extensive study on a wide range of circuits from simple logical circuits such as adders to complex circuits such as 4-bit processors. At the same time, little if any work has been done in considering the possibility of reconfiguration to reduce power in QCA devices. This work presents one of the first such efforts when considering reconfigurable QCA architectures which are expected to be both robust and power efficient. We present a new reconfiguration scheme which is highly robust and is expected to dissipate less power with respect to conventional designs. An adder design based on the reconfiguration scheme will be presented in this thesis, with a detailed power analysis and comparison with existing designs. In order to overcome the problems of routing which comes with reconfigurability, a new wire crossing mechanism is also presented as part of this thesis.

Here we present the design, assembly and successful ion trapping of a room-temperature ion trap system with a custom designed and fabricated surface electrode ion trap, which allows for rapid prototyping of novel trap designs such that new chips can be installed and reach UHV in under 2 days. The system has demonstrated success at trapping and maintaining both single ions and cold crystals of ions. We achieve this by fabricating our own custom surface Paul traps in the UMass Amherst cleanroom facilities, which are then argon ion milled, diced, mounted and wire bonded to an interposer which is placed in an ultra-high vacuum chamber and baked in a conventional oven for 46 hours. We demonstrate the system’s ability to confine strontium ions and present preliminary data towards calibrating the ion trap parameters for reduced heating rates. Future work will see the system being used to study the effects of various trap geometries, process fabrication steps and surface treatments on anomalous heating rates, and for portable quantum sensing applications, as an optical atomic clock.

Gallium nitride (GaN) light emitting diodes (LED) embody a large field of research that aims to replace inefficient, conventional light sources with LEDs that have lower power, higher luminosity, and longer lifetime. This thesis presents an international collaboration effort between the State Key Laboratory for Mesoscopic Physics in Peking University (PKU) of Beijing, China and the Electrical Engineering Department of California Polytechnic State University, San Luis Obispo. Over the course of 2 years, Cal Poly’s side has simulated GaN LEDs within the pure blue wavelength spectrum (460nm), focusing specifically on the effects of reflection gratings, transmission gratings, top and bottom gratings, error gratings, 3-fold symmetric photonic crystal, and 2-fold symmetric nano-imprinted gratings. PKU used our simulation results to fabricate GaN high brightness LEDs from the results of our simulation models. We employed the use of the finite difference time domain (FDTD) method, a computational electromagnetic solution to Maxwell’s equations, to measure light extraction efficiency improvements of the various grating structures. Since the FDTD method was based on the differential form of Maxwell’s equations, it arbitrarily simulated complex grating structures of varying shapes and sizes, as well as the reflection, diffraction, and dispersion of propagating light throughout the device. We presented the optimized case, as well as the optimization trend for each of the single grating structures within a range of simulation parameters on the micron scale and find that single grating structures, on average, doubled the light extraction efficiency of GaN LEDs. Photonic crystal grating research in the micron scale suggested that transmission gratings benefit most when grating cells tightly pack together, while reflection gratings benefit when grating cells space further apart. The total number of grating cells fabricated on a reflection grating layer still affects light extraction efficiency. For the top and bottom grating structures, we performed a partial optimization of the grating sets formed from the optimized single grating cases and found that the direct pairing of optimized single grating structures decreases overall light extraction efficiency. However, through a partial optimization procedure, top and bottom grating designs could improve light extraction efficiency by 118% for that particular case, outperforming either of the single top or bottom grating cases alone. Our research then explored the effects of periodic, positional perturbation in grating designs and found that at a 10-15% randomization factor, light extraction efficiency could improve up to 230% from the original top and bottom grating case. Next, in an experiment with PKU, we mounted a 2-fold symmetric photonic crystal onto a PDMS hemi-cylinder by nano-imprinting to measure the transmission of light at angles from near tangential to normal. Overall transmission of light compared with the non-grating design increases overall light extraction efficiency when integrated over the range of angles. Finally, our research focused on the 3-fold symmetric photonic crystal grating structure and employed the use of 3-D FDTD methods and incoherent light sources to better study the effects of higher-ordered symmetry in grating design. Grating cells were discovered as the source of escaping light from the GaN LED model. The model revealed that light extraction efficiency and the far-field diffraction pattern could be estimated by the position of grating cells in the grating design.

<p>Over the past few years various successful miniaturization attempts of External Cavity Semiconductor Lasers (ECSL) were published. They built upon the rich literature of ECSL configurations that were extensively analyzed and improved upon since the 1960s. This was merged with the microfabrication techniques of 3D structures based on MEMS technology. The main drive for miniaturizing such tunable lasers in the recent past was the huge potential for such devices in all optical networks specifically as signal sources that enable Wavelength Division Multiplexing (WDM).<br />This thesis compares the different configurations chosen to build tunable lasers using MOEMS technology. Our criteria of comparison include wavelength tuning range, side mode suppression, tuning speed and device dimensions. Designs based on the simple ECSL with a movable external mirror suffered from the tradeoff between tuning range and Side Mode Suppression SMS. To overcome this limitation most designs adopted grating based tuning using the Littrow or Littman/Metcalf configurations. These configurations allow for much better tuning results but don’t lend themselves easily to miniaturization. The grating based devices were bulky and quite complicated to realize.<br />We propose the adoption of the Zhu/Cassidy double external cavity configuration. It retains the simplicity of the single external mirror configuration along with the tuning range and the SMS of including multiple tuning elements. In its original form this configuration suffered from mode hopping within the tuning range. Thorough simulation, design and experimental evidence is presented in this work to show that by extending the configuration to allow full control over both optical tuning elements this drawback can be eliminated.<br />Our proposed design would reduce the form factor to < 300μm x 200μm x 200μm. The voltage required to tune through all the modes is < 40V and the resonant frequency of the mirror is in the 10s of MHz order of magnitude. When coupled with a multimode laser of a sufficiently broad lasing profile this setup should enable a tuning range > 72nm with a SMS >20dB.</p> / Master of Applied Science (MASc)

<p>GaAs/GaP heterostructure nanowires (NWs) were grown on GaAs(111)B and Si(111) substrates by gold (Au) assisted vapor-liquid-solid (VLS) growth in a molecular beam epitaxy (MBE) system. NW morphology and crystal structure were characterized by scanning electron microscopy (SEM) and transmission electron microscopy (TEM). Early results indicated substantial differences in the length and crystal structure of the GaAs/GaP heterostructures. Efforts to remove these inhomogeneities required an improved Au VLS seed deposition method as well as a better understanding of VLS growth across GaAs/GaP hetero-interfaces.</p> <p>Experiments with GaAs/GaP heterostructures yielded the observation of changes in crystal phase in GaP, including the first reported occurrence of the 4H polytype. These observations revealed the presence of transient growth behavior during the formation of the GaAs to GaP hetero-interface that was unique to the VLS technique. Further characterization required the need to move from VLS seeds formed by annealing thin Au films to Au particles formed precisely by electron beam lithography (EBL). NW growth using EBL patterned Au seeds was discovered to be inhibited by the formation of a thin silicon oxide layer, formed at low temperatures by Au-enhanced silicon oxidation. Elimination of this layer immediately prior to growth resulted in successful patterned VLS growth.</p> <p>A systematic study of the transient GaP growth behavior was then conducted using patterned arrays to grow GaAs/GaP heterostructure NWs with frequent, periodic oscillations in the group V composition. These oscillations were measured by high angle annular dark field (HAADF) to determine the instantaneous growth rate of many NWs. A phenomenological model was fit to the data and transient growth rate behavior following a GaAs to GaP hetero-interface was understood on the basis of transient droplet compositions, which arise due to the large difference in As or P alloy concentrations required to reach the critical supersaturation.</p> / Doctor of Philosophy (PhD)