A generalised model of biological topographic map development is presented which combines both weight plasticity and the formation and elimination of synapses (synaptic rewiring) as well as both activity-dependent and -independent processes. The question of whether an activity-dependent process can refine a mapping created by an activity-independent process is investigated using a statistical approach to analysingmapping quality. The model is then implemented in custom mixed-signal VLSI. Novel aspects of this implementation include: (1) a distributed and locally reprogrammable address-event receiver, with which large axonal fan-out does not reduce channel capacity; (2) an analogue current-mode circuit for Euclidean distance calculation which is suitable for operation across multiple chips; (3) slow probabilistic synaptic rewiring driven by (pseudo-)random noise; (4) the application of a very-low-current design technique to improving the stability of weights stored on capacitors; (5) exploiting transistor non-ideality to implement partially weightdependent spike-timing-dependent plasticity; (6) the use of the non-linear capacitance of MOSCAP devices to compensate for other non-linearities. The performance of the chip is characterised and it is shown that the fabricated chips are capable of implementing the model, resulting in biologically relevant behaviours such as activity-dependent reduction of the spatial variance of receptive fields. Complementing a fast synaptic weight change mechanism with a slow synapse rewiring mechanism is suggested as a method of increasing the stability of learned patterns.

<div>Deep Neural Networks (DNNs) have emerged as the state-of-the-art technique in a wide range of machine learning tasks for analytics and computer vision in the next generation of embedded (mobile, IoT, wearable) devices. Despite their success, they suffer from high energy requirements both in inference and training. In recent years, the inherent error resiliency of DNNs has been exploited by introducing approximations at either the algorithmic or the hardware levels (individually) to obtain energy savings while incurring tolerable accuracy degradation. We perform a comprehensive analysis to determine the effectiveness of cross-layer approximations for the energy-efficient realization of large-scale DNNs. Our experiments on recognition benchmarks show that cross-layer approximation provides substantial improvements in energy efficiency for different accuracy/quality requirements. Furthermore, we propose a synergistic framework for combining the approximation techniques. </div><div>To reduce the training complexity of Deep Convolutional Neural Networks (DCNN), we replace certain weight kernels of convolutional layers with Gabor filters. The convolutional layers use the Gabor filters as fixed weight kernels, which extracts intrinsic features, with regular trainable weight kernels. This combination creates a balanced system that gives better training performance in terms of energy and time, compared to the standalone Deep CNN (without any Gabor kernels), in exchange for tolerable accuracy degradation. We also explore an efficient training methodology and incrementally growing a DCNN to allow new classes to be learned while sharing part of the base network. Our approach is an end-to-end learning framework, where we focus on reducing the incremental training complexity while achieving accuracy close to the upper-bound without using any of the old training samples. We have also explored spiking neural networks for energy-efficiency. Training of deep spiking neural networks from direct spike inputs is difficult since its temporal dynamics are not well suited for standard supervision based training algorithms used to train DNNs. We propose a spike-based backpropagation training methodology for state-of-the-art deep Spiking Neural Network (SNN) architectures. This methodology enables real-time training in deep SNNs while achieving comparable inference accuracies on standard image recognition tasks.</div>

L’étude du fonctionnement de notre système nerveux et des mécanismes sensoriels a mené à la création de capteurs événementiels. Ces capteurs ont un fonctionnement qui retranscrit les atouts de nos yeux et oreilles par exemple. Cette thèse se base sur la recherche de méthodes bio-inspirés et peu coûteuses en énergie permettant de traiter les données envoyées par ces nouveaux types de capteurs. Contrairement aux capteurs conventionnels, nos rétines et cochlées ne réagissent qu’à l’activité perçue dans l’environnement sensoriel. Les implémentations de type « rétine » ou « cochlée » artificielle, que nous appellerons capteurs dynamiques, fournissent des trains d’évènements comparables à des impulsions neuronales. La quantité d’information transmise est alors étroitement liée à l’activité présentée, ce qui a aussi pour effet de diminuer la redondance des informations de sortie. De plus, n’étant plus contraint à suivre une cadence d’échantillonnage, les événements créés fournissent une résolution temporelle supérieure. Ce mode bio-inspiré de retrait d’information de l’environnement a entraîné la création d’algorithmes permettant de suivre le déplacement d’entité au niveau visuel ou encore reconnaître la personne parlant ou sa localisation au niveau sonore, ainsi que des implémentations d’environnements de calcul neuromorphiques. Les travaux que nous présentons s’appuient sur ces nouvelles idées pour créer de nouvelles solutions de traitement. Plus précisément, les applications et le matériel développés s’appuient sur un codage temporel de l’information dans la suite d'événements fournis par le capteur. / Studying how our nervous system and sensory mechanisms work lead to the creation of event-driven sensors. These sensors follow the same principles as our eyes or ears for example. This Ph.D. focuses on the search for bio-inspired low power methods enabling processing data from this new kind of sensor. Contrary to legacy sensors, our retina and cochlea only react to the perceived activity in the sensory environment. The artificial “retina” and “cochlea” implementations we call dynamic sensors provide streams of events comparable to neural spikes. The quantity of data transmitted is closely linked to the presented activity, which decreases the redundancy in the output data. Moreover, not being forced to follow a frame-rate, the created events provide increased timing resolution. This bio-inspired support to convey data lead to the development of algorithms enabling visual tracking or speaker recognition or localization at the auditory level, and neuromorphic computing environment implementation. The work we present rely on these new ideas to create new processing solutions. More precisely, the applications and hardware developed rely on temporal coding of the data in the spike stream provided by the sensors.

Redes Neurais têm sido um tema de pesquisas por pelo menos sessenta anos. Desde a eficácia no processamento de informações à incrível capacidade de tolerar falhas, são incontáveis os mecanismos no cérebro que nos fascinam. Assim, não é nenhuma surpresa que, na medida que tecnologias facilitadoras tornam-se disponíveis, cientistas e engenheiros têm aumentado os esforços para o compreender e simular. Em uma abordagem semelhante à do Projeto Genoma Humano, a busca por tecnologias inovadoras na área deu origem a projetos internacionais que custam bilhões de dólares, o que alguns denominam o despertar global de pesquisa da neurociência. Avanços em hardware fizeram a simulação de milhões ou até bilhões de neurônios possível. No entanto, as abordagens existentes ainda não são capazes de fornecer a densidade de conexões necessária ao enorme número de neurônios e sinapses. Neste sentido, este trabalho propõe DHyANA (Arquitetura Digital Neuromórfica Hierárquica), uma nova arquitetura em hardware para redes neurais pulsadas, a qual utiliza comunicação em rede-em-chip hierárquica. A arquitetura é otimizada para implementações de Máquinas de Estado Líquido. A arquitetura DHyANA foi exaustivamente testada em plataformas de simulação, bem como implementada em uma FPGA Stratix IV da Altera. Além disso, foi realizada a síntese lógica em tecnologia 65nm, a fim de melhor avaliar e comparar o sistema resultante com projetos similares, alcançando uma área de 0,23mm2 e potência de 147mW para uma implementação de 256 neurônios. / Neural Networks has been a subject of research for at least sixty years. From the effectiveness in processing information to the amazing ability of tolerating faults, there are countless processing mechanisms in the brain that fascinates us. Thereupon, it comes with no surprise that as enabling technologies have become available, scientists and engineers have raised the efforts to understand, simulate and mimic parts of it. In a similar approach to that of the Human Genome Project, the quest for innovative technologies within the field has given birth to billion dollar projects and global efforts, what some call a global blossom of neuroscience research. Advances in hardware have made the simulation of millions or even billions of neurons possible. However, existing approaches cannot yet provide the even more dense interconnect for the massive number of neurons and synapses required. In this regard, this work proposes DHyANA (Digital HierArchical Neuromorphic Architecture), a new hardware architecture for a spiking neural network using hierarchical network-on-chip communication. The architecture is optimized for Liquid State Machine (LSM) implementations. DHyANA was exhaustively tested in simulation platforms, as well as implemented in an Altera Stratix IV FPGA. Furthermore, a logic synthesis analysis using 65-nm CMOS technology was performed in order to evaluate and better compare the resulting system with similar designs, achieving an area of 0.23mm2 and a power dissipation of 147mW for a 256 neurons implementation.

Emerging computing architectures such as, neuromorphic computing and third party intellectual property (3PIP) cores, have attracted significant attention in the recent past. Neuromorphic Computing introduces an unorthodox non-von neumann architecture that mimics the abstract behavior of neuron activity of the human brain. They can execute more complex applications, such as image processing, object recognition, more efficiently in terms of performance and energy than the traditional microprocessors. However, focus on the hardware security aspects of the neuromorphic computing at its nascent stage. 3PIP core, on the other hand, have covertly inserted malicious functional behavior that can inflict range of harms at the system/application levels. This dissertation examines the impact of various threat models that emerges from neuromorphic architectures and 3PIP cores. Near-Threshold Computing (NTC) serves as an energy-efficient paradigm by aggressively operating all computing resources with a supply voltage closer to its threshold voltage at the cost of performance. Therefore, STC system is scaled to many-core NTC system to reclaim the lost performance. However, the interconnect performance in many-core NTC system pose significant bottleneck that hinders the performance of many-core NTC system. This dissertation analyzes the interconnect performance, and further, propose a novel technique to boost the interconnect performance of many-core NTC system.

This thesis presents a body of work in the field of reconfigurable and neuromorphic circuits and systems. Three main projects were undertaken. The first was using a Field-Programmable Analog Array (FPAA) to model the cable behavior of dendrites using analog circuits. The second was to design, lay out, and test part of a new FPAA, the RASP 2.9v. The final project was to use floating-gate programming to remove offsets in a neuromorphic FPAA, the RASP Neuron 1D.

Analog circuit technology is of vital importance in today's world of electronic design. Increasing prevalence of mobile electronics necessitates the search for solutions which offer high performance given tight constraints on power and chip area. Field programmable arrays utilizing floating-gate technology are one possible solution to analog design. It offers the advantages of analog processing with the additional advantage of reconfigurability, giving the designer the ability to test new analog designs without costly and time-consuming fabrication and test cycles. In this work, a new interface for FPAA's is demonstrated called Sim2spice, with which users can design signal processing systems in Matlab Simulink and compile them to SPICE circuit netlists. These netlists can be further compiled with a tool called GRASPER to a switch list for programming on an FPAA chip. Example library elements are shown, along with some compiled systems such as filters and vector-matrix multipliers. One particularly compelling application of reconfigurable analog design is the field of neuromorphic circuits, which aims to reproduce the basic functional characteristics of biological neurons and synapses in analog integrated circuit technology. Simulink libraries have been built to allow designers to build neuromorphic systems on several FPAAs that have been developed expressly for the purpose of building neurons and connecting them in networks with synapses. Several possible dynamically learning synapses have also been explored.

This work details CMOS, bio-inspired, bio-compatible circuits which were used as synapses between an artificial neuron and a living neuron and between two living neurons. An intracellular signal from a living neuron was amplified, an integrate-and-fire neuron was used as a simple processing element to detect the spikes, and an artificial synapse was used to send outputs to another living neuron. The key structure is an electronic synapse which is based around a floating-gate pFET. The charge on the floating-gate is analogous to the synaptic weight and can be modified. This modification can be viewed as similar to long-term potentiation and long-term depression. The modification can either be programmed (supervised learning) or can adapt to the inputs (unsupervised learning). Since the technology to change the floating-gate weight has greatly improved, these weights can be set quickly and accurately. Intrinsic floating-gate learning rules were explored and the ability to change the synaptic weight was shown.

Intelligent systems with even the bare minimum of sophistication require extensive computational power and complex processing units. At the same time, small insects like flies are adept at visual navigation, target pursuit, motionless hovering flight, and obstacle avoidance. Thus, biology provides engineers with an unconventional approach to solve complicated engineering design problems. Computational models of the neuronal architecture of the insect brain can provide algorithms for the development of software and hardware to accomplish sophisticated visual navigation tasks. In this research, we investigate biologically-inspired collision avoidance models primarily based on visual motion. We first present a comparative analysis of two leading collision avoidance models hypothesized in the insect brain. The models are simulated and mathematically analyzed for collision and non-collision scenarios. Based on this analysis it is proposed that along with the motion information, an estimate of distance from the obstacle is also required to reliably avoid collisions. We present models with tracking capability as solutions to this problem and show that tracking indirectly computes a measure of distance. We present a camera-based implementation of the collision avoidance models with tracking. The camera-based system was tested for collision and non-collision scenarios to verify our simulation claims that tracking improves collision avoidance. Next, we present a direct approach to estimate the distance from an obstacle by utilizing non-directional speed. We describe two simplified non-directional speed estimation models: the non-directional multiplication (ND-M) sensor, and the non-directional summation (ND-S) sensor. We also analyze the mathematical basis of their speed sensitivity. An analog VLSI chip was designed and fabricated to implement these models in silicon. The chip was fabricated in a 0.18 um process and its characterization results are reported here. As future work, the tracking algorithm and the collision avoidance models may be implemented as a sensor chip and used for autonomous navigation by intelligent systems.

Neurocomputers offer a massively parallel computing paradigm by mimicking the human brain. Their efficient use in statistical information processing has been proposed to overcome critical bottlenecks with traditional computing schemes for applications such as image and speech processing, and associative memory. In neural networks information is generally represented by phase (e.g., oscillatory neural networks) or amplitude (e.g., cellular neural networks). Phase-based neurocomputing is constructed as a network of coupled oscillatory neurons that are connected via programmable phase elements. Representing each neuron circuit with one oscillatory device and implementing programmable phases among neighboring neurons, however, are not clearly feasible from circuits perspective if not impossible. In contrast to nascent oscillatory neurocomputing circuits, mature amplitude-based neural networks offer more efficient circuit solutions using simpler resistive networks where information is carried via voltage- and current-mode signals. Yet, such circuits have not been efficiently realized by CMOS alone due to the needs for an efficient summing mechanism for weighted neural signals and a digitally-controlled weighting element for representing couplings among artificial neurons. Large power consumption and high circuit complexity of such CMOS-based implementations have precluded adoption of amplitude-based neurocomputing circuits as well, and have led researchers to explore the use of emerging technologies for such circuits. Although they provide intriguing properties, previously proposed neurocomputing components based on emerging technologies have not offered a complete and practical solution to efficiently construct an entire system. In this thesis we explore the generalized problem of co-optimization of technology and architecture for such systems, and develop a recipe for device requirements and target capabilities. We describe four plausible technologies, each of which could potentially enable the implementation of an efficient and fully-functional neurocomputing system. We first investigate fully-digital neural network architectures that have been tried before using CMOS technology in which many large-size logic gates such as D flip-flops and look-up tables are required. Using a newly-proposed all-magnetic non-volatile logic family, mLogic, we demonstrate the efficacy of digitizing the oscillators and phase relationships for an oscillatory neural network by exploiting the inherent storage as well as enabling an all-digital cellular neural network hardware with simplified programmability. We perform system-level comparisons of mLogic and 32nm CMOS for both networks consisting of 60 neurons. Although digital implementations based on mLogic offer improvements over CMOS in terms of power and area, analog neurocomputing architectures seem to be more compatible with the greatest portion of emerging technologies and devices. For this purpose in this dissertation we explore several emerging technologies with unique device configurations and features such as mCell devices, ovenized aluminum nitride resonators, and tunable multi-gate graphene devices to efficiently enable two key components required for such analog networks – that is, summing function and weighting with compact D/A (digital-to-analog) conversion capability. We demonstrate novel ways to implement these functions and elaborate on our building blocks for artificial neurons and synapses using each technology. We verify the functionality of each proposed implementation using various image processing applications based on compact circuit simulation models for such post-CMOS devices. Finally, we design a proof-of-concept neurocomputing circuitry containing 20 neurons using 65nm CMOS technology that is based on the primitives that we define for our analog neurocomputing scheme. This allows us to fully recognize the inefficiencies of an all-CMOS implementation for such specific applications. We share our experimental results that are in agreement with circuit simulations for the same image processing applications based on proposed architectures using emerging technologies. Power and area comparisons demonstrate significant improvements for analog neurocomputing circuits when implemented using beyond- CMOS technologies, thereby promising huge opportunities for future energy-efficient computing.