ANSYS Packaging Thermal/Mechanical Calculator (APTMC) is an interface program developed for use with ANSYS and specially designed to handle thermal and thermally induced stress modeling/simulation of Level 1 and Level 2 VLSI packaging structures and assemblies. APTMC is written in PASCAL and operates in an interactive I/O format mode. This user-friendly tool leads an analyst/designer through the process of creating appropriate thermal and thermally induced stress models and other operations necessary to run ANSYS. It includes such steps as the following: (1) construction of ANSYS commands through the string process; (2) creation of a dynamic data structure which expands and contracts during program execution based on the data storage requirements of the program sets to control model generation; (3) access of material data and model parameters from the developed INTERNAL DATABANK which contains: (a) material data list; (b) heat transfer modes; and (c) library of structures; (4) forming ANSYS PREP7 and POSTn command files. (Abstract shortened with permission of author.)

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A granola-type, omega-3-rich breakfast cereal prototype was developed using ground flaxseed as the principal source of linolenic acid (1.8% w/w). Other ingredients included rolled oats, yellow sugar, honey, sliced almonds, and canola oil. The focus of the research investigation was to apply and study the addition of an antioxidant (AO) and the use of Modified Atmosphere Packaging (MAP) on shelf-life extension of the enriched cereal. Granola samples, both with and without AO (300ppm of 70% mixed tocopherols), were packaged in air, and under the two atmospheres achieved by nitrogen flushing (MA 1) and an oxygen scavenger (MA2). Samples were stored at either 21 or 35°C. / Shelf-life was terminated when products reached a thiobarbituric acid (TBA) value of 4.0 mg malonaldehyde/kg corresponding to a sensory score of 5 (on a hedonic scale of 10). (Abstract shortened by UMI.)

Oxygen scavengers are used in active packages to protect the food against deteriorative oxidation processes. The aim of this work was to investigate the possibilities to produce oxygen-scavenging packaging materials based on oxygen-reducing enzymes. The enzymes were incorporated into a dispersion coating formulation applied onto a food-packaging board using conventional laboratory coating techniques. Various enzymes were used: a glucose oxidase, an oxalate oxidase and three laccases originating from different organisms. All of the enzymes were successfully incorporated into a coating layer and could be reactivated after drying. For at least two of the enzymes, re-activation was possible not only by using liquid water but also by using water vapour. Re-activation of the glucose oxidase and a laccase required relative humidities of greater than 75% and greater than 92%, respectively. Catalytic reduction of oxygen gas by glucose oxidase was promoted by creating an open structure through addition of clay to the coating at a level above the critical pigment volume concentration. Migration of the enzyme and the substrate was reduced by adding an extrusion-coated liner of polypropylene on top of the coating. For the laccase-catalysed reduction of oxygen it was possible to use lignin derivatives as substrates for the enzymatic reaction. The laccase-catalysed reaction created a polymeric network by cross-linking of lignin-based entities, which resulted in increased stiffness and increased water-resistance of biopolymer films. The laccases were also investigated with regard to their potential to function as oxygen scavengers at low temperatures. At 7°C all three laccases retained more than 20% of the activity they had at room temperature (25°C), which suggests that the system is also useful for packaging of refrigerated food.

Microelectronic systems such as cell phones, computers, consumer electronics, and implantable medical devices consist of subsystems which in turn consist of other subsystems and components. When such systems are designed, fabricated, assembled, and tested, they need to meet reliability, cost, performance, and other targets for being competitive. The design of reliable electronic packaging systems in a systematic and timely manner requires a consistent and unified method for allocating, predicting, and assessing reliability and for recommending design changes at the component and system level with consideration of both random and wearout failures. Accordingly, this dissertation presents a new unified knowledge modeling method for System Design for Reliability (SDfR) called the Reliability Object Model (ROM) method. The ROM method consistently addresses both reliability allocation and assessment for systems composed of series and parallel subsystems. The effectiveness of the ROM method has been demonstrated for allocating, predicting, and assessing reliability, and the results show that ROM is more effective compared to existing methods, providing richer semantics, unified techniques, and improved SDfR quality. Furthermore, this dissertation develops representative reliability metrics for random and wearout failures, and incorporates such metrics into ROM together with representative algorithms for allocation, assessment, and design change recommendations. Finally, this research implemented the ROM method in a computing framework and demonstrated its applicability using several relevant microelectronic system test cases and prototype SDfR tools.

Consumer demands are driving the current trend in the microelectronics industry to make electronic products that are miniature, fast, compact, high-density, reliable and low-cost. The use of surface mount devices (SMDs) has helped to decrease the size of electronic packages through the use of solder bump interconnections between the devices and the substrates/printed wiring boards (PWBs). Solder bumps act as not only mechanical, but also electrical interconnections between the device and the substrate/PWB. Common manufacturing defects ¨C such as open, cracked, missing, and misaligned solder bumps ¨C are difficult to detect because solder bumps are hidden between the device and the substrate/PWB after assembly. The reliability of packaged electronic devices in storage and usage is a major concern in the microelectronics industry. Therefore, quality inspection of solder bumps has become a critical process in the microelectronics industry to help ensure product quality and reliability. In this thesis, a methodology for quality evaluation and reliability study of solder bumps in electronic packages has been developed using the non-destructive and non-contact laser ultrasound-interferometric technique, finite element and statistical methods in this research work. This methodology includes the following aspects: 1) inspection pattern ¨C specific inspection patterns are created according to inspection purpose and package formats, 2) laser pulse energy density calibration ¨C specific laser pulse power and excitation laser spot size are selected in terms of package formats, 3) processing and analysis methods, including integrated analytical, finite element and experimental modal analyses approach, advanced signal processing methods and statistical analysis method, 4) approach combining modal analysis and advanced signal processing to improve measurement sensitivity of laser ultrasound-interferometric inspection technique, and 5) calibration curve using energy based simulation method and laser ultrasound inspection technique to predict thermomechanical reliability of solder bumps in electronic packages. Because of the successful completion of the research objectives, the system has been used to evaluate a broad range of solder bump defects in a variety of packaged electronic devices. The development of this system will help tremendously to improve the quality and reliability of electronic packages.

The fundamental motivation for this dissertation is to address the widening interconnect gap between integrated circuit (IC) demands and package substrates specifically for high frequency digital-RF systems applications. Moore's law for CMOS ICs predicts that transistor density on ICs will double approximately every 18 months. The current state-of-the-art in IC package substrates is at 20µm lines/spaces and 50-60µm microvia diameter using epoxy dielectrics with loss tangent above 0.01. The research targets are to overcome the barriers of current technologies and demonstrate a set of advanced materials and process technologies capable of 5-10µm lines and spaces, and 10-30µm diameter microvias in a multilayer 3-D wiring substrate using 10-25µm thin film dielectrics with loss tangent in the <0.005. The research elements are organized as follows with a clear focus on understanding and characterization of fundamental materials structure-processing-property relationships and interfaces to achieve the next generation targets. (a) Low CTE Core Substrate, (b) Low Loss Dielectrics with 25µm and smaller microvias, (c) Sub-10µm Width Cu Conductors, and (d) Integration of the various dielectric and conductor processes.