This thesis presents circuit-level techniques for soft error mitigation, low-power design with performance trade-off, and variation-tolerant low-power design. The proposed techniques are divided into two broad categories. First, error compensation techniques, which are used for soft error mitigation and also for low-power operation of linear and non-linear filters. Second, a framework for variation tolerant low-power operation of wireless devices is presented. This framework analyzes the effects of circuit "tuning knobs" such as voltage, frequency, wordlength precision, etc. on system performance, and power efficiency. Process variations are considered as well, and the best operating tuning knob levels are determined, which results in maximum system wide power savings while keeping the system performance within acceptable limits. Different methods are presented for variation-tolerant and power-efficient wireless communication. Techniques are also proposed for application driven low-power operation of the OFDM baseband receiver.

The continuous scaling of interconnect wires in deep submicron (DSM)circuits result in increased interconnect delay, power and crosstalk noise. In this dissertation, we address the problem of multi-metric optimization at post layout level in the design of deep submicron designs and develop a game theoretic framework for its solution. Traditional approaches in the literature can only perform single metric optimization and cannot handle multiple metrics. However, in interconnect optimization, the simultaneous optimization of multiple parameters such as delay, crosstalk noise and power is necessary and critical. Thus, the work described in this dissertation research addressing multi-metric optimization is an important contribution.Specifically, we address the problems of simultaneous optimization of interconnect delay and crosstalk noise during (i) wire sizing (ii) gate sizing (iii) integrated gate and wire sizing, and (iv) gate sizing considering process variations. Game the ory provides a natural framework for handling conflicting situations and allows optimization of multiple parameters. This property is exploited in modeling the simultaneous optimization of various design parameters such as interconnect delay, crosstalk noise and power, which are conflicting in nature. The problem of multi-metric optimization is formulated as a normal form game model and solved using Nash equilibrium theory. In wire sizing formulations, the net segments within a channel are modeled as the players and the range of possible wire sizes forms the set of strategies. The payoff function is modeled as (i) the geometric mean of interconnect delay andcrosstalk noise and (ii) the weighted-sum of interconnect delay, power and crosstalk noise, in order to study the impact of different costfunctions with two and three metrics respectively. In gate sizing formulations, the range of possible gate sizes is modeled as the set of strategies and the payoff function is modeled as the geome tric mean of interconnect delay and crosstalk noise. The gates are modeled as the players while performing gate sizing, whereas, the interconnect delay and crosstalk noise are modeled as players for integrated wire and gate sizing framework as well as for statistical gate sizing under the impact of process variations.The various algorithms proposed in this dissertation (i) perform multi-metric optimization (ii) achieve significantly better optimization and run times than other methods such as simulated annealing, genetic search, and Lagrangian relaxation (iii) have linear time and space complexities, and hence can be applied to very large SOC designs, and (iv) do not require rerouting or incur any area overhead. Thecomputational complexity analysis of the proposed algorithms as well as their software implementations are described, and experimental results are provided that establish the efficacy of the proposed algorithms.

Divers domaines d'application des systèmes électroniques, comme par exemple les implants médicaux ou les puces cryptographiques pour les appareils portables, exigent à la fois une très faible puissance consommé et un niveau de fiabilité très élevé. De plus, comme la miniaturisation des technologies CMOS s'approche de ses limites ultimes, ces exigences deviennent nécessaires pour l'ensemble de l'industrie de microélectronique. En effet, en approchant ces limites les problèmes de la dissipation de puissance, du rendement de fabrication et de la fiabilité des composants empirent, rendant la poursuite de miniaturisation nanométriques de plus en plus difficile. Ainsi, avant que ces problèmes bloquent le progrès technologique, des nouvelles solutions au niveau du processus de fabrication et du design sont exigées pour maintenir la puissance dissipée, le rendement de fabrication et la fiabilité à des niveaux acceptables. Le projet de thèse vise le développement des architectures tolérantes aux fautes capables de répondre à ces défis pour les technologies de fabrication CMOS présentes et à venir. Ces architectures devraient permettre d'améliorer le rendement de fabrication et la fiabilité et de réduire en même temps la puissance dissipée des composants électroniques. Elles conduiraient en une innovation majeure, puisque les architectures tolérant aux fautes traditionnelles permettraient d'améliorer le rendement de fabrication et la fiabilité des composants électroniques aux dépens d'une pénalité significative en puissance consommée. / Various applications of electronic systems, such as medical implant devices, or cryptographic chips for potable devices require both lower power dissipation and higher level of reliability. Moreover, as silicon-based CMOS technologies are fast approaching their ultimate limits, these requirements become necessary for the entire microelectronics industry. Indeed, by approaching these limits, power dissipation, fabrication yield, and reliability worsen steadily making further nanometric scaling increasingly difficult. Thus, before reaching these limits, these problems could become show-stoppers unless new techniques are introduced to maintain acceptable levels of power dissipation, fabrication yield and reliability. This thesis aims to develop a fault tolerant architecture for logic designs that conciliates the above contradictory challenges and provides a global solution to the yield, reliability and power dissipation issues in current and future nanometric technologies. The proposed fault tolerant architecture is expected to improve the fabrication yield and reliability while reducing the power dissipation of electronic components. It leads a breakthrough, since traditional fault-tolerant architectures introduce significant area and power penalties.

Orientadores: Guido Costa Souza de Araújo, Mario Lúcio Côrtes / Dissertação (mestrado) - Universidade Estadual de Campinas, Instituto de Computação / Made available in DSpace on 2018-08-21T20:47:12Z (GMT). No. of bitstreams: 1 Santana_MarceloFontes_M.pdf: 4262688 bytes, checksum: 3e2635e36cd3272eb4bd09c07b05bf63 (MD5) Previous issue date: 2012 / Resumo: O resumo, poderá ser visualizado no texto completo da tese digital / Abstract The abstract is available with the full electronic document / Mestrado / Ciência da Computação / Mestre em Ciência da Computação

Gate-all-around (GAA) nanosheet field effect transistors (NSFETs) seem to be one of the most promising replacement options for FinFETs towards scaling down below to the sub-7nm technology nodes. They offer better electrostatics and control of short channel effects (SCEs) due to their superior control over the channel and their large effective channel width. Moreover, one can vertically stack multiple nanosheets to improve the drive strength of the device at a much-relaxed geometry than an aggressively scaled FinFET. However, stacking nanosheets would result in complex device structure, leading to significant process variability. Process variations could arise from irregular sheet thicknesses, random doping fluctuations, strain-induced variability, temperature effects, etc. which would affect the performance of the device. This has put a great emphasis on the need to come up with a properly calibrated process and simulation tools to analyze the performance of the NSFETs by identifying the sources of process variations with utmost precision. For this purpose, a TCAD-based simulation assessment has been done to model the design and performance of GAA NSFETs. The study explores the impacts of the variation in various physical parameters including the number of nanosheets, the sheet thickness, the work-function (WF) of metal gate stack layers, operational temperatures and channel doping on the electrical performance of the NSFETs. Moreover, a detailed fabrication process simulation flow for the design of a 3-sheet GAA NSFET has been presented. The simulation results predict that the process variations primarily have an impact on the device threshold voltage (Vth) which in turn influences the on-off currents, and the sub-threshold swing of the device. A comparative analysis has been done to understand the deviation of these electrical characteristics from their ideal values as a result of these variations. / Gate-all-around (GAA) nanoblads-fälteffekttransistorer (NSFETs) verkar vara ett av de mest lovande ersättningsalternativen för FinFET transistorer för att möjliggöra skalning ner till sub 7nm teknologinoderna. Denna typ av transistorer har bättre elektrostatik och kontroll av kortkanalseffekter (SCE) tack vare sin goda kontroll över kanalen och sin stora effektiva kanalvidd. Man kan dessutom stapla nanoblad vertikalt för att förbättra komponentens strömdrivningsförmåga med en mer relaxerad geometri än för en aggressivt skalad FinFET. Att stapla nanoblad gör komponentens struktur mer komplex vilket leder till betydande processvariabilitet. Processvariationer kan uppstå från oregelbundna tjocklekar för bladen, slumpmässiga dopningsfluktuationer, töjningsinducerad variabilitet, temperatureffekter m.m. Alla dessa variationer kan påverka komponentens prestanda. Det är därför viktigt att etablera korrekt kalibrerade process- och simuleringsverktyg för att analysera prestandan hos nanoblads-transistorerna. För detta ändamål har en TCAD-baserad simuleringsstudie gjorts för att modellera designen och prestandan för GAA nanoblads-transistorer. Studien undersöker effekterna av variationen i olika fysiska parametrar, inklusive antalet nanoblad och bladtjockleken, utträdesarbetet för metallgaten, temperaturen och kanaldopningen på den elektriska prestandan hos nanobladstransistorerna. Dessutom har ett detaljerat processimuleringsflöde för utformningen av 3-blads transistorer presenterats. Simuleringsresultaten visar att processvariationerna i första hand har en inverkan på transistorns tröskelspänning som i sin tur påverkar av- och på- strömmarna och subtröskelegenskaperna. En jämförande analys har gjorts för att förstå avvikelsen mellan dessa elektriska egenskaper från deras idealvärden som ett resultat av dessa variationer.

Cette thèse porte sur la conception et le test des premiers circuits CMOS auto-adaptatifs nanométriques dédiés aux applications automobiles, avioniques et aérospatiales, dans des environnements à forte contrainte car soumis à des compromis entre vitesse (performance), consommation (Low Power) et vieillissement (Wearout). Des solutions innovantes ont été développées avec des boucles de régulation dynamiques pour optimiser la consommation des différents éléments (niveau de conception) et des blocs (système), tout en assurant leur bon fonctionnement. La validation des solutions a été réalisée étape par étape dans la chaîne de conception, en se concentrant d'abord sur le développement d'un premier démonstrateur en technologie CMOS (M40) 40 nm pour les applications automobiles de STMicroelectronics. Différentes manières d'anticiper les erreurs ont été comparées en conservant la détection de retard IS2M dans les chemins critiques. Une modélisation théorique des boucles de contrôle a abouti à un outil de simulation basé sur des chaînes de Markov discrètes dans le temps (DTMC). Cette modélisation a été confrontée avec succès à des mesures de silicium démontrant que les solutions sélectionnées offraient une réduction de la puissance consommée par 2 avec des performances et une fiabilité égales. Dans la dernière partie, les solutions proposees sont testees sur un demonstrateur CMOS FDSOI 28nm, afin de valider la pertinence de l'adaptation dynamique (D-ABB) dans les tensions d'alimentation et de face. / This thesis deals with the design and testing of the first self-adaptive nanoscale CMOS circuits dedicated to automotive, avionics and aerospace applications, under high stress environment because they are subject to the trade-off between speed (performance), consumption (Low Power) and aging (Wearout). Innovative solutions have been developed with dynamic control loops to optimize the consumption of the various elements (design level) and blocks (system), while ensuring their smooth operation. Validation of solutions has been achieved step by step in the design chain, focusing first on the development of a first demonstrator in 40nm CMOS (M40) technology for automotive applications from STMicroelectronics. Various ways of anticipating errors were compared by retaining the IS2M (adjustable time window) delay detection in critical paths as the most efficient for optimization solutions. A theoretical modeling of the control loops has resulted in a simulation tool based on time discrete Markov chains (DTMC). This modeling was successfully confronted with silicon measurements demonstrating that the solutions selected offered a reduction in the power consumed by 2 with equal performance and reliability. In the last part, the high-level hierarchical modeling was applied on several systems / products of 28nm FDSOI CMOS nodes (28FD), in order to validate the relevance of the dynamic adaptation (D-ABB) in supply and face voltages. (VDD, VB). This allowed to prove the validity of the complete methodology by arriving at the precise statistical prediction of the reliability integrating the whole performance-consumption value chain using the advanced simulations.

The objective of this research is to demonstrate the impact of interconnect process variations, line-edge roughness and size effects on interconnect effective resistivity and ultimately chip performance. The investigation is accomplished through five tasks. In Task I, a new closed-form effective resistivity model, which is a function of line-edge roughness (LER), surface specularity and grain boundary reflectivity, is derived. In Task II, a critical path model is enhanced by including interconnect parasitics using the model in Task I. This enhancement also involves an extensive survey of foundry process data to shed light on the device resistance estimation used in the critical path model in Task II. Task III develops a Monte Carlo (MC) simulation framework called the Fast Interconnect Statistical Simulator (FISS). Using the latest International Technology Roadmap for Semiconductors (ITRS) projections, the FISS projects the impact of interconnect process variations and size effects onto high performance microprocessor units (HP-MPUs). Task IV fabricates metallic interconnect test structures with sub-100nm line-widths. The fifth task statistically calibrates the model from Task I using resistivity data measured from the test structures in Task IV.

The advent of deep submicron technology coupled with ever increasing demands from the customer for more functionality on a compact silicon real estate has led to a proliferation of highly complex integrated RF system-on-chip (SoC) and system-on-insulator (SoI) solutions. The use of scaled CMOS technologies for high frequency wireless applications is posing daunting technological challenges both in design and manufacturing test. To ensure market success, manufacturers need to ensure the quality of these advanced RF devices by subjecting them to a conventional set of production test routines that are both time consuming and expensive. Typically the devices are tested for parametric specifications such as gain, linearity metrics, quadrature mismatches, phase noise, noise figure (NF) and end-to-end system level specifications such as EVM (error vector magnitude), BER (bit-error-rate) etc. Due to the reduced visibility imposed by high levels of integration, testing for parametric specifications are becoming more and more complex. To offset the yield loss resulting from process variability effects and reliability issues in RF circuits, the use of self-healing/self-tuning mechanisms will be imperative. Such self-healing is typically implemented as a test/self-test and self-tune procedure and is applied post-manufacture. To enable this, simple test routines that can accurately diagnose complex performance parameters of the RF circuits need to be developed first. After diagnosing the performance of a complex RF system appropriate compensation techniques need to be developed to increase or restore the system performance. Moreover, the test, diagnosis and compensation approach should be low-cost with minimal hardware and software overhead to ensure that the final product is economically viable for the manufacturer. The main components of the thesis are as follows: 1) Low-cost specification testing of advanced radio frequency front-ends: Methodologies are developed to address the issue of test cost and test time associated with conventional production testing of advanced RF front-ends. The developed methodologies are amenable for performing self healing of RF SoCs. Test generation algorithms are developed to perform alternate test stimulus generation that includes the artifacts of test signal path such as response capture accuracy, load-board DfT etc. A novel cross loop-back methodology is developed to perform low cost system level specification testing of multi-band RF transceivers. A novel low-cost EVM testing approach is developed for production testing of wireless 802.11 OFDM front-ends. A signal transformation based model extraction technique is developed to compute multiple RF system level specifications of wireless front-ends from a single data capture. The developed techniques are low-cost and facilitate a reduction in the overall contribution of test cost towards the manufacturing cost of advanced wireless products. 2)Analog tuning methodologies for compensating wireless RF front ends: Methodologies for performing low-cost self tuning of multiple impairments of wireless RF devices are developed. This research considers for the first time, multiple analog tuning parameters of a complete RF transceiver system (transmitter and receiver) for tuning purposes. The developed techniques are demonstrated on hardware components and behavioral models to improve the overall yield of integrated RF SoCs.

L'exportation et la mutualisation des industries de fabrication des circuits intégrés impliquent de nombreuses interrogations concernant l'intégrité des circuits fabriqués. On se retrouve alors confronté au problème d'insertion d'une fonctionnalité dissimulée pouvant agir de façon cachée : on parle de Cheval de Troie Matériel (CTM). En raison de la complexité d'un circuit intégré, repérer ce genre de modification se révèle particulièrement difficile. Le travail proposé dans ce manuscrit s'oriente vers une technique de détection non destructrice de CTM. L’approche consiste à utiliser les temps de calculs internes du système étudié comme canal permettant de détecter des CTM. Dans ces travaux, un modèle décrivant les temps de calcul est défini. Il prend notamment en compte deux paramètres importants que sont les conditions expérimentales et les variations de procédés.Des attaques en faute par glitchs d’horloge basée sur la violation de contraintes temporelles permettent de mesurer des temps de calcul internes. Des cartes fiables sont utilisées pour servir de référence. Après avoir validé la pertinence de ce canal d’étude concernant l’obtention d’informations sur le comportement interne du circuit cible, on procède à des détections expérimentales de CTM insérés à deux niveaux d’abstraction (niveau RTL et après l'étape de placement/routage). Des traitements avec prise en compte des variations de procédés permettent d'identifier si les cartes testées sont infectées par un CTM. / The globalization of integrated circuits fabrication involves several questions about the integrity of the fabricated circuits. Malicious modifications called Hardware Trojans (HT) can be introduced during the circuit production process. Due to the complexity of an integrated circuit, it is really difficult to find this kind of alterations.This work focuses on a non-destructive method of HT detection. We use the paths delays of the studied design as a channel to detect HT. A model to describe paths delays is defined. It takes into account two important parameters which are the experimental conditions and the process variations.Faults attacks by clock glitches based on timing constraints violations have been performed to measure data paths delays. Reliable circuits are used for reference. After validating the relevance of this channel to get information on the internal behavior of the targeted design, experimental detections of HT inserted on two different abstraction levels (RTL and after place and route) were achieved. Process variations are taken into consideration in the studies to detect if the tested circuits are infected.

De nombreuses applications industrielles spécifiques dans les secteurs tels que l'automobile, le médical et le spatial, requièrent un très haut niveau de fiabilité. Ce type d'applications fonctionnant sous des contraintes sévères (haute température, corrosion, vibration, radiations,…) impose aux industriels des spécifications particulières en termes de fiabilité et de consommation d'énergie. Dans ce contexte, les travaux menés ont pour objectif d'étudier la fiabilité des mémoires Flash embarquées pour des applications faible consommation et à forte contrainte de fiabilité. Après une introduction orientée sur les deux volets d'étude que sont la caractérisation électrique et le test de mémoires non volatiles, un modèle physique capable de modéliser le courant de SILC a été développé. Cet outil permet de répondre à la problématique de perturbations en lecture (read disturb) et donne aux designers et technologues un moyen d'estimer le taux de défaillance de cellules mémoires en fonction de paramètres physiques, géométriques et électriques ainsi que des moyens d'action afin de minimiser ce phénomène indésirable. La fiabilité (oxyde tunnel, endurance) et les performances (consommation énergétique) de la cellule Flash sont ensuite étudiées en explorant les variations de paramètres du procédé de fabrication et des conditions électriques de fonctionnement. Enfin, une étude originale menée en temps réel sur plus de 15 mois est consacrée à la fiabilité en rétention des mémoires Flash soumises aux effets des particules radiatives présentes dans l'environnement naturel terrestre. / Many specific applications used in automotive, medical and spatial activity domains, require a very high level of reliability. These kinds of applications, working under severe constraints (high temperature, corrosion, vibration, radiations…) challenge memory manufacturers and impose them particular specifications in terms of reliability and energy consumption. In this context, work presented in this thesis aim at studying embedded Flash memories reliability for low power and high reliability applications. After an introduction oriented on areas of electrical characterizations and Test of non-volatile memories, a physical model of SILC leakage current is developed. This tool is used to answer to disturbs problematic and gives to designers and technologists a way to estimate the failure rate of memory cells according to physical, geometrical and electrical parameters, giving leads to minimize this unwanted phenomenon. Reliability (tunnel oxide, cell endurance) and performances (energy consumption) of Flash memory cell are then studied exploring process parameters variations and electrical conditions optimizations. Finally, an original real-time experiment over more than 15 months is focused on Flash memories retention reliability due to irradiative particles effects of natural terrestrial environment.