Modern microprocessors require low supply voltage (about 1V), but very high current (maximum current is 300A in servers, 100A in desktop PCs and 70A in notebook PCs), and tighter voltage regulation. However, the size of a CPU Voltage Regulator (VR) needs to be reduced. To achieve much higher power density with decent efficiency in VR design is a major challenge. Moreover, the CPU current rating can vary from 40A to 300A for different kinds of computers, and CPU power supply specifications change quickly even for the same type of computers. Since the maximum power rating of one channel converter is limited, the VR channel number may vary over a large range to meet VR specifications. Traditionally, VR design with different channel numbers needs different types of VR controllers. To reduce the developing cost of different control ICs, and to maximize the market share of one design, scalable phase design based on the same type of IC is a new trend in VR design. To achieve higher power density and at the same time to achieve scalable phase design, the concept of Monolithic Voltage Regulator Channel (MVRC) is introduced in this dissertation. MVRC is a power IC with one channel converter's power MOSFETs, drivers and control circuitries monolithically integrated based on lateral device technology and working at high frequency. It can be used alone to supply a POL (Point of Load). And without the need for a separate master controller, multiple MVRC chips can be paralleled together to supply a higher current load such as a CPU. To make MVRC a reality, the key is to develop a fully distributed control scheme and its associated analog IC circuitry, so that it can provide control functions required by microprocessors and the performance must be equal or better than a traditional a centralized VRM controller. These functions includes: multiphase interleaving, Adaptive Voltage Position (AVP) and current sharing. To achieve interleaving, this dissertation introduces a novel distributed interleaving scheme that can easily achieve scalable phase interleaving without channel number limitation. Each channel's interleaving circuitry can be monolithically integrated without any external components. The proposed scheme is verified by a hardware prototype. The key building block is a self-adjusting saw-tooth generator, which can produce accurate saw-tooth waveforms without trimming. The interleaving circuit for each channel has two self-adjusting saw-tooth generators. One behaves as a Phase Lock Loop to produce accurate phase delay, and the other produces carrier signals. To achieve Adaptive Voltage Position and current sharing, a novel distributed control scheme adopting the active droop control for each channel is introduced. Verified by hardware testing and transient simulations, the proposed distributed AVP and current sharing control scheme meets the requirements of Intel's guidelines for today and future's VR design. Monte Carlo simulation and statistics analysis show that the proposed scheme has a better AVP tolerance band than the traditional centralized control if the same current sensing scheme is used, and its current sharing performance is as good as the traditional control. It is critical for the current sensing to achieve a tight AVP regulation window and good current sharing in both the traditional centralized control scheme and the proposed distributed control scheme. Inductor current sensing is widely adopted because of the acceptable accuracy and no extra power loss. However, the Signal-to-Noise Ratio (SNR) of the traditional inductor current sensing scheme may become too small to be acceptable in high frequency VR design where small inductor with small DCR is often adopted. To improve the SNR, a novel current sensing scheme with an accurate V/I converter is proposed. To reduce the complexity of building an accurate V/I converter with traditional Opamps, an accurate monolithic transconductance (Gm) amplifier with a large dynamic range is developed. The proposed Gm amplifier can achieve accurate V/I conversion without trimming. To obtain further verification, above proposed control schemes are monolithically integrated in a dual channel synchronous BUCK controller using TSMC BiCMOS 0.5um process. Testing results show that all the proposed novel analog circuits work as expected. System testing results show good interleaving, current sharing and AVP performance. The silicon size of each channel is 1800×1000um². With proposed current sensing, interleaving, AVP and current sharing, as well as their associated analog IC implementations, the technical barriers to develop a MVRC are overcome. MVRC has the potential to become a generic power IC solution for today and future POL and CPU power management. The proposed distributed interleaving, AVP and current sharing schemes can also be used in any cellular converter system. The proposed analog building blocks like the self-adjusting saw-tooth generator and the accurate transconductance amplifier can be used as basic building blocks in any DC-DC controller. / Ph. D.

As a very special DC-DC converter, VRM (Voltage Regulator Module) design must follow the fast-developing trend of microprocessors. The design challenges are the high current, high di/dt, and stringent load-line requirement. When the energy is transferred from the input of a VRM, through the VRM, then through the power delivery path to the processor, it needs sufficient capacitors to relay this energy. The capacitors' number appears to be unrealistically large if we follow today's approach for the future processors. High frequency VRM with high control bandwidth can solve this problem, however, the degradation of efficiency makes the conventional buck converter and the hard-switching isolated topologies incapable of operating at higher frequency. The research goal is to develop novel means that can help a high-output- current VRM run efficiently at high frequency. A novel Complementary Controlled Bridge (CCB) self-driven concept is proposed. With the proposed self-driven scheme, the combination of the ZVS technique and the self-driven technique recycles the gate driving energy by making use of the input capacitor of the secondary- side synchronous rectifier (SR) as the snubber capacitor of the primary-side switches. Compared to the external driver, the proposed converter can save driving loss and synchronous rectifier body diode conduction loss. Additionally, compared to the existing level-shifted self-driven scheme for bridge-type symmetrical topologies, its gate signal ringing is small and suitable for high-frequency applications. Although the CCB self-driven VRM reduces the switching frequency-related losses significantly, the conduction loss is still high. Inspired by the current-doubler concept, a novel ZVS current-tripler DC-DC converter is proposed in this work. By utilizing more SR devices to share the current during the freewheeling period, the SR conduction loss is reduced. The current-tripler DC-DC converter has a delta/delta connected transformer that can be implemented with integrated magnetics. The transformer then becomes an integrated magnetic with distributed windings, which is preferred in high current applications. The current-tripler DC-DC converter in fact meets the requirements for the CCB self-driven scheme. The two concepts are then combined with an integrated gate drive transformer. The proposed CCB self-driven concept and current-tripler concept can both be applied to the 12V non-isolated VRMs. The proposed topology is basically a buck-derived soft-switching topology with duty cycle extension and SR device self-driven capabilities. Because there is no isolation requirement, the SR gate driving becomes so simple that the voltage at the complementary controlled bridge can be used to directly drive the SR gate. Both the gate driving loss and the SR body diode conduction loss are reduced. The proposed circuit achieves similar overall efficiency to a conventional 300kHz buck converter running at 1MHz. All the circuits proposed in this dissertation can use coupling inductors to improve both the steady-state efficiency and dynamic performances. The essence of the coupling inductors concept is to provide different equivalent inductances for the steady state and the transient. Moreover, when a current loop becomes necessary to achieve proper current sharing among phases, the current loop sample hold effect will make it difficult to push the bandwidth. The sample hold effect is alleviated by the coupling inductors concept. A small-signal model is proposed to study the system dynamic performance difference with different coupling inductor designs. As the verification, the coupling concept is applied to the 12V non-isolated CCB self-driven VRM and the bandwidth as high as one third of the switching frequency is achieved, which means a significant output capacitor reduction. / Ph. D.

With the electronic equipments becoming more and more complicated, the requirements for the power management are more and more strict. Efficient performance, high functionality, small profile, fast transient and low cost are the most wanted features for modern power management ICs, especially for mobile power. In order to reduce profile, the number of external components should be as small as possible, which means that compensator, ramp compensation, current sensor, driver and even power devices should be all implemented on a single chip, i.e. monolithic integration. Comparing with discrete switching DC-DC converter, monolithic integration brings a number of benefits and new design challenges. Besides monolithic integration, high switching frequency is another trend for power management ICs due to its higher bandwidth and the ability to further reduce external passive component size. Comparing with low frequency counterparts, high frequency switching converter design is more difficult in terms of the stability modeling, high switching loss and difficult current sensing etc. The objective of this dissertation is to study the design issues for monolithic integration of high frequency switching DC-DC converter. For this purpose, a high frequency, wide input range monolithic buck converter ASIC with fast transient response is designed based on advanced trench BCD technology. Stability is the fundamental requirement in designing switching converter ASIC. Achieving this requires an accurate loop gain design, especially for monolithically integrated high frequency switching converter since compensator is fixed on silicon and loop delay is comparable with switching cycle. Since DC-DC switching converters are time-varying system, traditional small signal analysis in SPICE cannot be directly used to simulate the loop gain of this kind of system. A periodic small signal analysis based method is proposed to analyze and simulate DC-DC switching converter inside a SPICE like simulator without the need for averaging. This general method is suitable for any switching regulators. The results are accurate comparing with average modeling and experiment results even at high frequency part. A general procedure to design loop gain is proposed. Several novel design concepts are proposed for monolithic integration of high frequency switching DC-DC converter; a novel control scheme-Cotangent Control (Ctg control) is proposed for fast transient response; In order to realize on-chip implementation of the compensator, especially for low frequency zero, active feedback compensator is developed and a general design procedure is proposed. Adaptive compensation concept is proposed to stabilize the whole system for a wide application range. Multi-stage driver and multi-section device concepts are investigated for high efficiency and low noise power stage design. And finally, a new noise insensitive lossless RC sensor is proposed for high speed current sensing. At the end of this dissertation, the test results of the fabricated chip are presented to verify the correctness of these design concepts. / Ph. D.

Since future microprocessors will have higher current in accordance with Moore's law, there are still challenges for voltage regulators (VRs). Firstly, high efficiency is required not only for easy thermal management, but also for saving on electricity costs for data centers, or battery life extension for laptop computers. At the same time, high power density is required due to the increased power of the microprocessors. This is especially true for data centers, since more microprocessors are required within a given space (per rack). High power density is also required for laptop computers to reduce the size and the weight. To improve power density, a high frequency is required to shrink the size of the output inductors and output capacitors of the multi-phase buck VR. It has been demonstrated that the output bulk capacitors can be eliminated by raising the VR control bandwidth to around 350kHz. Assuming the bandwidth is one-third of the switching frequency, a VR should run at 1MHz to ensure a small size. However, the efficiency of a 12V VR is very poor at 1MHz due to high switching losses. As a result, a 12V VR can only run at 300kHz to 600kHz, and the power density is very low. To attain high efficiency and high power density at the same time, two-stage power architecture was proposed. The concept is "Divide and Conquer". A single-stage VR is split into two stages to get better performance. The second stage has about 5V-6V input voltage; thus the duty cycle can be extended and the switching losses are greatly reduced compared with a single-stage VR. Moreover, a sub-20V MOSFET can be used to further improve the efficiency at high frequencies. The first stage of the proposed two-stage architecture is converting 12V to 5-6V. High efficiency is required for the first stage since it is in series with the second stage. Previous first stage which is a buck converter has good efficiency but bulky size due to low frequency operation. Another problem with using a buck converter is that light-load efficiency of the first stage is poor. To solve these problems, switched-capacitor voltage dividers are proposed. Since the first stage does not require voltage regulation, the sweet point for the voltage divider can be determined and high efficiency can be achieved. At the same time, since there are no magnetic components for the switched-capacitor voltage divider, high power density can be achieved. By very careful design, a power density of more than 2000W/in3 with more than 97% efficiency can be achieved for the proposed voltage divider. The light-load efficiency of the voltage divider can be as high as 99% by reducing the switching frequency at light load. As for the second stage, different low-voltage devices are evaluated, and the best device combinations are found for high-frequency operation. It has been demonstrated that 91% efficiency can be achieved with 600kHz frequency, and 89% efficiency can be achieved with a 1MHz frequency for the second stage. Moreover, adaptive on-time control method and a non-linear inductor structure are proposed to improve CCM and DCM efficiency for the second stage respectively. Previously the two-stage VR was only used as a CPU VR. The two-stage concept can also be applied to other systems. In this dissertation, the two-stage power architecture is applied to two different applications: laptop computers and high-end server microprocessors. The common characteristics of the two applications are their thermal design power (TDP) requirement. Thus the first stage can be designed with much lower power than the maximum system power. It has been demonstrated that the two-stage power architecture can achieve either higher efficiency or higher power density and a lower cost when compared with the single-stage VR. To get higher efficiency, a parallel two-stage power architecture, named sigma architecture, is proposed for VR applications. The proposed sigma VR takes advantage of the high-efficiency, fast-transient unregulated converter (DCX) and relies on this converter to deliver most of the output power, while using a low-power buck converter to achieve voltage regulation. Both the DCX converter and the buck converter can achieve around 90% efficiency when used in the sigma VR, which ensures 90% efficiency for the sigma VR. The small-signal model of the sigma VR is studied to achieve adaptive voltage positioning (AVP). The sigma power architecture can also be applied to low-power point of load (POL) applications to reduce the magnetic component size and improve the efficiency. Finally, the two-stage VR and the sigma VR are briefly compared. / Ph. D.

For more than 100 years, the Navier-Stokes equations and various linearizations have been used as a model to study fluid dynamics. Recently, attention has been directed toward studying the nonnormality of linearized problems and developing convergent numerical schemes for simulation of these sytems. Numerical schemes for optimal control problems often require additional properties that may not be necessary for simulation; these properties can be critical when studying nonnormal problems. This research is concerned with approximating infinite dimensional optimal control problems with nonnormal system operators. We examine three different finite element methods for a specific convection-diffusion equation and prove convergence of the infinitesimal generators. Additionally, for two of these schemes, we prove convergence of the associated feedback gains. We apply these three schemes to control problems and compare the performance of all three methods. / Ph. D.

Since the early 80s, the computer industry has undergone great expansion. Processors are becoming faster and more powerful. Power management issues in computing systems are becoming more and more complex and challenging. An evolution began when the high-performance Pentium processor was driven by a non-standard, less-than-5V power supply, instead of drawing its power from the 5V plane on the system board. A so-called Voltage Regulator Module (VRM) is put close to the processor in order to provide the power as quickly as possible. Nowadays, for desktop and workstation applications, VRM input voltage has moved to the 12V output of the silver box. In the meantime, microprocessors will run at very low voltage (below 1V), will consume up to 100A of current, and will have dynamics of about 400A/us. In the near future, VRM will be replaced with VRD because of the parasitic components effect. The specifications requirements for VRD are even more challenging than VRM. With this kind of tight tolerance, high current and fast current slew rate, transient response requirements for VRD design are very challenging, especially for step-down transient. During step-down transient, there is some additional energy stored in inductor. Traditional switching regulator like multi-phase buck can do nothing for this even by saturating the duty cycle to 0. All of the additional energy in inductor will be dumped into output cap and cause a large voltage spike at the output voltage. Even for step-up transient, traditional linear control like voltage loop control can't provide enough bandwidth because of the slow compensation and slow slew rate of the error amplifier. So the voltage drop is still quite large. Comparing with traditional linear controlled switching regulator such as voltage control and current control buck converter, active clamp has a lot of the advantages for the transient response. With proper design, active clamp can generate a very high bandwidth since there is no compensator needed in the control loop. Since active clamp bypasses inductor and is connected directly to the output cap, it can quickly source and sink current from the output cap even during the step-down transient and prevent overshooting of the output voltage. This is the biggest advantage for active clamp comparing with traditional linear control. In this thesis, a new active clamp structure is proposed. Several new concepts are proposed like non-linear Gm, built-in offset Gm, error signal feedback and AVP design. A one-channel buck converter with new active clamp and voltage loop control is implemented and verified using real transistors based on 0.5um CMOS process. / Master of Science

With lower output voltage (lower than 1V) and higher output current (more than 160A) required in the near future, the voltage regulators for the microprocessors, a kind of special power supplies are facing more and more critical challenges to achieve high efficiency and high power density. 90% plus efficiency for CPU VRs is expected from industry not only for the thermal management, but also for saving on electricity costs, especially for the large data-center systems. At the same time, high power density VRs are also desired due to the increasing power consumption of microprocessors as well as the precious space on CPU motherboard. Current multi-phase Buck VR has its limitation to achieve 90% plus efficiency. With the state of art devices, the single-stage 12V/1.2V 600kHz Buck VR achieves 85% to 86% efficiency at full load condition. In addition, for the future lower output voltage application, the Buck efficiency will drop another 3~4% due to the extreme small duty cycle. From the power density point of view, due to the switching frequency limitation (normally, from 300 kHz to 600 kHz for typical CPU VRs) for acceptable efficiency performance, the multi-phase Buck VR is unable to ensure a small size since it needs bulky output capacitors to meet the challenging transient requirement as well as the output impedance requirement with relatively low bandwidth design. To attain high efficiency and high power density at the same time, in-series two-stage power architecture was proposed. By cutting the single stage into two and utilizing the low voltage devices, the in-series two stages can achieve around 87% efficiency which is similar as single stage with second-stage operating at 1 MHz for less cost. Compared with the in-series one, the other two-stage power architecture is called "Sigma" architecture which is composed by an unregulated converter (DCX) and a regulated buck converter, with a special connection where the inputs are in series while outputs are paralleled. Through this topology, unlike the in-series two-stage where both two stages deliver the full load power, the power will be distributed between unregulated DCX and regulated Buck. If the unregulated DCX can achieve high efficiency, let most power be handled by it and just small power from buck, the Sigma architecture can achieve high efficiency performance based on this concept. The design consideration and process had been investigated by CPES previous graduates. By the designed 1.2V/120A Sigma VR circuit, approaching 90% efficiency was achieved which is around 3~4% efficiency higher than state of the art multi-phase Buck VR. However, it is not the optimal design for best efficiency performance, the improvement methods for higher efficiency is deeply considered and the efficiency potential benefit of this special structure will be clarified in this thesis. Besides the efficiency interest, transient performance of Sigma VR is also a challenging issue needed to be addressed. The state of the art Buck VR needs a bunch of output bulk capacitors to meet the stringent output impedance requirement from Intel and those output bulk capacitors occupy too much space in the motherboard. For Sigma architecture, through the help of the low impedance DCX which can achieve faster current dynamic response, some low voltage bulk capacitors could be replaced by smaller input high voltage capacitors. It is still not clear for us to identify how input capacitor impacts the DCX dynamic current response and how to best choose this impact factor. This thesis will investigate the faster DCX dynamic current performance of Sigma VR, and explain the dynamic impacts from input capacitors, from control design and from DCX impedance Lout. The high voltage capacitors could provide energy through low impedance DCX to deal with the transient load with smaller capacitance, resulting less total cost and footprint with conventional Buck solution. Low impedance DCX is also a desire for achieving fast current response for providing a "non-obstacle" path when energy transferring from input capacitors. The control also has the impact to the DCX current response when the bandwidth is higher than certain frequency. The transient benefit will also be discussed from impedance perspective. In order to improve the efficiency and power density of Sigma VR, several methods are proposed. As a critical component of DCX, the transformer design determines the performance of Sigma VR both to efficiency and power density. By optimizing the transformer design to achieve lower winding loss and smaller leakage inductance, the higher efficiency and faster transient DCX can be obtained. Changing the output capacitors to ceramic ones is helpful when control bandwidth is greater than 100 kHz for both lower cost and smaller footprint. Continually pushing bandwidth can reduce the required output ceramic capacitor number further. In addition, from the study of the loss breakdown, by adjusting the energy ratio of DCX and Buck can achieve higher efficiency based on current device level. What is more, with the same simple concept of adjusting power ratio of DCX and Buck, with the development of devices in the future as well as higher efficiency DCX, Sigma architecture will be more attractive for future's lower output voltage VR application. And it will also be more efficient considering higher than 12V input bus voltage by letting high efficiency DCX handle more power. Utilizing this characteristic, changing the power system delivery architecture from AC input to the microprocessors, the end to end efficiency could be improved. / Master of Science

Prohexadione-calcium (P-ca), as ApogeeTM, was evaluated in 2000 and 2001 for impact to grape vegetative and reproductive development. In 2000, P-ca (250 mg/L) was applied to Seyval, Cabernet Sauvignon, and Cabernet franc (125, 250, and 375 mg/L). P-ca reduced primary shoot growth for all cultivars and decreased cane pruning weight of Seyval. P-ca (375 mg/L) increased Cabernet franc canopy gaps but increased Cabernet Sauvignon lateral leaf area and leaf layer number. P-ca reduced components of yield for all cultivars. In 2001, P-ca (250 mg/L) was applied singularly at weekly intervals to Cabernet Sauvignon clusters and pre and post-bloom to Cabernet franc and Chardonnay canopies. Application at E-L stages 21 and 23 decreased Cabernet Sauvignon fruit set whereas application at E-L stages 26, 27, and 29 reduced berry weight without impacting fruit set. Berry weight reduction correlated to higher color intensity (420+520 nm), anthocyanins, total phenols and phenol-free glycosyl-glucose (PFGG). Cabernet franc vegetative and reproductive development was generally not affected yet treatment increased absorbance at 280, 420, and 520 nm, color intensity, anthocyanins and total phenols. Pre-bloom applications inhibited Chardonnay vegetative development, and reduced components of yield, and fruit chemistry values: hydroxycinnamates, total phenols, flavonoids, PPFG and absorbance at 280 and 320 nm. Post-bloom applications did not affect Chardonnay vegetative or reproductive development, yet increased PFGG. Treatment did not affect Chardonnay wine chemistry but two post-bloom applications increased Cabernet franc wine anthocyanins and total phenols. Wine aroma and flavor triangle difference tests did not indicate significant treatment differences. / Master of Science

The use of computers in the modern world has become prevalent in all aspects of life. The size of these machines has decreased dramatically while the capability has increased exponentially. A special DC-DC converter called a VRM (Voltage Regulator Module) is used to power these machines. The VRM faces the task of supplying high current and high di/dt to the microprocessor while maintaining a tight load regulation. As computers have advanced, so have the VRM's used to power them. Increasing the current and di/dt of the VRM to keep up with the increasing demands of the microprocessor does not come without a cost. To provide the increased di/dt, the VRM must use a higher number of capacitors to supply the transient energy. This is an undesirable solution because of the increased cost and real estate demands this would lead to in the future. Another solution to this problem is to increase the switching frequency and control bandwidth of the VRM. As the switching frequency increases the VRM is faced with efficiency and thermal problems. The current buck topologies suffer large drops in efficiency as the frequency increases from high switching losses. Resonant or soft switching topologies can provide a relief from the high switching loss for high frequency power conversion. One disadvantage of the resonant schemes is the increased conduction losses produced by the circulating energy required to produce soft switching. As the frequency rises, the additional conduction loss in the resonant schemes can be smaller than the switching loss encountered in the hard switched buck. The topology studied in this work is the 12V non-isolated ZVS self-driven presented in [1]. This scheme offered an increased efficiency over the state of the art industry design and also increased the switching frequency for capacitor reduction. The goal of this research was to study this topology and improve the magnetic design to decrease the cost while maintaining the superior performance. The magnetics used in resonant converters are very important to the success of the design. Often, the leakage inductance of the magnetics is used to control the ZVS or ZCS switching operation. This work presents a new improved magnetic solution for use in the 12V non-isolated ZVS self-driven scheme which increases circuit operation, flexibility, and production feasibility. The improved magnetic structure is simulated using 3D FEA verification and verified in hardware design. / Master of Science

O tratamento de infecções por Staphylococcus aureus tem sido problemático devido ao surgimento de cepas resistentes a múltiplios antibióticos. O antibiótico de escolha para o tratamento de infecções por S. aureus resistente a oxacilina é o glicopeptídeo vancomicina. Desde o primeiro isolamento de cepas com sensibilidade reduzida a vancomicina (VISA) em 1997, tem havido crescente preocupação com a disseminação da resistência a este antibiótico. Os mecanismos moleculares que levam à resistência de baixo nível a vancomicina ainda não foram elucidados. A detecção deste fenótipo na rotina de laboratório clínico é laboriosa, pois as técnicas disponíveis são de difícil execução e interpretação. Até agora, não há relato de transmissão horizontal de infecção por VISA, e todas as cepas com este fenótipo foram isoladas de pacientes que faziam o uso prolongado de vancomicina. Uma deficiência no locus regulador de genes acessórios (agr) foi postulado como fator de risco para a aquisição do fenótipo VISA por uma cepa sensível a este antibiótico. Para este estudo, foram selecionadas 47 cepas de S. aureus, com sensibilidades variadas a vancomicina, inclusive 5 cepas VISA isoladas no Brasil. Determinou-se nas cepas as concentrações inibitórias mínimas de vancomicina e oxacilina, a atividade hemolítica em ágar sangue de carneiro e de coelho, a capacidade de aderir ao poliestireno e o polimorfismo do locus agr. Determinou-se a integridade do locus agr por PCR-RFLP e sequenciamento de bases em 13 cepas representativas das 47 estudadas. A integridade do locus regulador acessório sarA também foi avaliada por sequenciamento de bases nestas 13 cepas. Foram escolhidas 18 cepas sensíveis a vancomicina com variadas características fenotípicas e estas foram submetidas à indução de resistência a vancomicina através da passagem seriada em concentrações crescentes deste antibiótico. A taxa de mutação que leva à capacidade de crescimento em 6 µg/mL de vancomicina foi avaliada em 8 cepas através de ensaios de flutuação. Não observou-se correlação entre a aquisição de resistência a vancomicina com as atividades hemolíticas ou capacidade de adesão das cepas. A maioria das cepas (82,9%) apresentou-se como pertencente ao grupo polimórfico agr I, inclusive as cepas VISA. Duas cepas não conseguiram ser induzidas à resistência a vancomicina. O tempo levado para a aquisição de resistência não se correlacionou com nenhuma característica fenotípica ou genotípica de um grupo de cepas. A taxa de mutação que leva à capacidade de crescimento em 6µg/mL de vancomicina apresentou-se maior para uma cepa pertencente ao clone endêmico brasileiro (CEB) cujo locus agr pertence ao grupo I e não apresentou variação de acordo com funcionalidade ou tipo do locus agr. Apenas uma das cepas VISA apresentou uma mutação no locus agr que o torna disfuncional. Os loci agr das outras cepas estudadas apresentaram-se íntegros. O locus sarA das cepas estudadas apresentou-se íntegro e com polimorfismos funcionais agrupados de acordo com a linhagem clonal das cepas. Pôde-se concluir que a integridade funcional do locus agr não é uma condição sine qua non para a aquisição de resistência de baixo nível a vancomicina por parte de uma cepa sensível a este antibiótico. O grupo polimórfico agr II não tem maior predisposição à aquisição de resistência de baixo nível a vancomicina, como havia sido sugerido por alguns trabalhos disponíveis na literatura. / The treatment of staphylococcal infections has lately been a strenuous undertaking due to the resistance of Staphylococcus aureus to multiple antibiotics. The antimicrobial drug of choice for the treatment of methicillin resistant S. aureus (MRSA) is the glycopeptide vancomycin. Since the first isolation of S. aureus with reduced susceptibility to vancomycin (VISA) in 1997, there has been growing concern as to the dissemination of this resistance phenotype among isolates of this species. The molecular mechanisms that result in low level resistance to vancomycin have not yet been completely elucidated. The correct detection of this phenotype in the clinical laboratory is tricky, for the techniques available for this purpose are hard to execute and interpret. Until now, lateral transmission (dissemination) of VISA has not been reported and all strains bearing this phenotype have been isolated from patients who had been making prolonged use of vancomycin. A deficiency in the accessory gene regulator (agr) has been proposed as a risk factor for the acquisition of a VISA phenotype by a susceptible strain. For this study, 47 nosocomial VISA strains, that had been isolated in another study, were used. These strains were isolated from multiple geographical regions of Brazil, and included 5 VISA strains. The minimal inhibitory concentrations (MIC) of vancomycin and oxacillin, as well as haemolysis in sheep and rabbit agar, adhesion to polystyrene and agr polymorphism were determined in all of these strains. The integrity of the agr locus was determined by PCR-RFLP and by nucleotide sequencing in a sample of 13 strains chosen to be representative of the 47 strains studied. The integrity of the Staphylococcal accessory regulator sarA was also determined by nucleotide sequencing in these 13 strains. Another representative sample of 18 strains that were susceptible to vancomycin were submitted to induction of resistance to vancomycin by serial passage in increasing concentrations of this drug. The mutation rate of a mutation that leads to the ability of growing in a concentration of 6 µg/mL of vancomycin was determined for 8 strains by fluctuation assays. There was no correlation between the acquisition of resistance to vancomycin with either haemolysis or adhesion to polystyrene. Most strains (82.9%) bore a group I agr polymorphism, including all of the VISA strains. Two strains could not be induced to resistance. The time taken for each strain to acquire resistance to vancomycin did not correlate with any phenotypic or genotypic characteristic pertaining to a group of strains. The rate of mutation that leads to the ability of growing in 6µg/mL of vancomycin proved to be higher for a strain belonging to the Brazilian Endemic Clone (BEC) bearing an agr group I polymorphism, and did not vary according to presence or type of agr locus. Only one of the VISA strains presented a mutation in the agr locus that renders it disfunctional. The agr loci of the other strains studied presented themselves to be intact. The sarA loci of the strains evaluated were intact however presented functional polymorphisms that were groups according to the clonal lineage of the strains. It can thus be concluded that the functional integrity of the agr locus is not a sine qua non condition for the acquisition of low level resistance to vancomycin by a susceptible strain. Bearing of an agr group II polymorphism does not predispose a strain to acquire resistance to vancomycin, as has been previously suggested in literature.