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The Large Hadron Collider at CERN is scheduled to undergo upgrades in 2026-2028 to significantly increase its luminosity. These upgrades, while providing the experiments with a higher collision rate, pose a number of challenges to the design of the hardware and software in the detectors. The Tile Calorimeter (a scintillating sampling calorimeter read out by photomultiplier tubes) at the ATLAS experiment will have its read-out electronics completely replaced to enable performance and reliability improvements.  Advances in electronics, new requirements due to the luminosity upgrade as well as lessons learned from the current readout scheme drove development with the goals to partition the readout into small independent units with full granularity readout and a robust mitigation strategy for radiation induced errors. To verify the functionality of the new system while retaining backward compatibility a "Demonstrator'' has been developed to emulate the current functionality while using new and improved hardware. The board responsible for managing digitized calorimeter data and communicating with the off-detector electronics, called the DaughterBoard, is the main focus of this thesis. It has two electrically isolated sides for redundancy where each side consists of voltage regulators, two optical transceivers, a GigaBit transceiver chip (for clocking and configuration) and a Kintex FPGA for data processing. In addition to data management and transmission, the FPGA (and every other component) needs to be able to withstand the effects of radiation both in terms of total dose (ionization and displacement damage) and due to single event effects. The DaughterBoard was developed with this in mind and has undergone several radiation tests during its development to verify reliability and fault tolerance. / CERN

En raison de leur impact sur la fiabilité des systèmes, les effets du rayonnement cosmique sur l’électronique ont été étudiés dès le début de l’exploration spatiale. Néanmoins, de récentes évolutions industrielles bouleversent les pratiques dans le domaine, les technologies standard devenant de plus en plus attrayantes pour réaliser des circuits durcis aux radiations. Du fait de leurs fréquences élevées, des nouvelles architectures de transistor et des temps de durcissement réduits, les puces fabriquées suivant les derniers procédés CMOS posent de nombreux défis. Ce travail s’attelle donc à la simulation des aléas logiques permanents (SEU) et transitoires (SET), en technologies FD-SOI et bulk Si avancées. La réponse radiative des transistors FD-SOI 28 nm est tout d’abord étudiée par le biais de simulations TCAD, amenant au développement de deux modèles innovants pour décrire les courants induits par particules ionisantes en FD-SOI. Le premier est principalement comportemental, tandis que le second capture des phénomènes complexes tels que l’amplification bipolaire parasite et la rétroaction du circuit, à partir des premiers principes de semi-conducteurs et en accord avec les simulations TCAD poussées.Ces modèles compacts sont alors couplés à une plateforme de simulation Monte Carlo du taux d’erreurs radiatives (SER) conduisant à une large validation sur des données expérimentales recueillies sous faisceau de particules. Enfin, des études par simulation prédictive sont présentées sur des cellules mémoire et portes logiques en FD-SOI 28 nm et bulk Si 65 nm, permettant d’approfondir la compréhension des mécanismes contribuant au SER en orbite des circuits intégrés modernes / The effects of cosmic radiation on electronics have been studied since the early days of space exploration, given the severe reliability constraints arising from harsh space environments. However, recent evolutions in the space industry landscape are changing radiation effects practices and methodologies, with mainstream technologies becoming increasingly attractive for radiation-hardened integrated circuits. Due to their high operating frequencies, new transistor architectures, and short rad-hard development times, chips manufactured in latest CMOS processes pose a variety of challenges, both from an experimental standpoint and for modeling perspectives. This work thus focuses on simulating single-event upsets and transients in advanced FD-SOI and bulk silicon processes.The soft-error response of 28 nm FD-SOI transistors is first investigated through TCAD simulations, allowing to develop two innovative models for radiation-induced currents in FD-SOI. One of them is mainly behavioral, while the other captures complex phenomena, such as parasitic bipolar amplification and circuit feedback effects, from first semiconductor principles and in agreement with detailed TCAD simulations.These compact models are then interfaced to a complete Monte Carlo Soft-Error Rate (SER) simulation platform, leading to extensive validation against experimental data collected on several test vehicles under accelerated particle beams. Finally, predictive simulation studies are presented on bit-cells, sequential and combinational logic gates in 28 nm FD-SOI and 65 nm bulk Si, providing insights into the mechanisms that contribute to the SER of modern integrated circuits in orbit

In this Ph.D. thesis, a new methodology for the fault tolerant system state synchronization design and its recovery from faults is presented. A state synchronization method designed by means of the proposed methodology allows to repair the state of sequential logic elements implemented in the FPGA application logic, which cannot be repaired by the partial dynamic reconfiguration. The proposed methodology describes possible state synchronization design methods with respect to TMR granularity, dependence of the system function on its previous states and the system architecture. The methodology focuses on coarse-grained TMR architectures and state synchronization in the systems controlled by means of finite state machines or a processor. The use of the methodology is demonstrated on the CAN bus control system and the microcontroller NEO430, for which specific synchronization methods were designed. The systems reliability and new ability of the systems for recovery from faults were verified in the presence of simulated SEU faults. The experimental results and the contribution of this thesis are discussed in the conclusion.

Softcore processors are an attractive alternative to using expensive radiation-hardened processors for space-based applications. Since they can be implemented in the latest SRAM-based FPGA technologies, they are fast, flexible and significantly less expensive. However, unlike ASIC-based processors, the logic and routing of a softcore processor are vulnerable to the effects of single-event upsets (SEUs). To protect softcore processors from SEUs, this dissertation explores the processor design-space for the LEON3 softcore processor implemented in a commercial SRAM-based FPGA. The traditional mitigation techniques of triple modular redundancy (TMR) and duplication with compare (DWC) and checkpointing provide reliability to a softcore processor at great spatial cost. To reduce the spatial cost, terrestrial ASIC-based processor protection techniques are applied to the LEON3 processor. These techniques come at the cost of time instead of area. The software fault-tolerance techniques used to protect the logic and routing of the LEON3 softcore processor include a modified version of software implemented fault tolerance (SWIFT), consistency checks, software indications, and checkpointing. To measure the reliability of a mitigated LEON3 softcore processor, an updated hardware fault-injection model is created, and novel reliability metrics are employed. The improvement in reliabilty over an unmitigated LEON3 is measured using four metrics: architectural vulnerability factor (AVF), mean time to failure (MTTF), mean useful instructions to failure (MuITF), and reliability-area-performance (RAP). Traditional reliability techniques provide the best reliability: DWC with checkpointing improves the MTTF and MuITF by almost 35x and TMR with triplicated input and outputs improves the MTTF and MuITF by almost 6000x. Software fault-tolerance provides significant reliability for a much lower area cost. Each of these techniques provides greater processor protection than a popular state-of-the-art rad-hard processor.

Triple modular redundancy (TMR) with repair is commonly used to improve the reliability of systems. TMR is often employed for circuits implemented on field programmable gate arrays (FPGAs) to mitigate the radiation effects of single event upsets (SEUs). This has proven to be an effective technique by improving a circuit's sensitive cross-section by up to 100x. However, testing has shown that the improvement offered by TMR is limited by upsets in single configuration bits that cause TMR to fail.This work proposes a variety of mitigation techniques that improve the effectiveness of TMR on FPGAs. These mitigation techniques can alter the circuit's netlist and how the circuit is placed and routed on the FPGA. TMR with repair showed a neutron cross-section improvement of 100x while the best mitigation technique proposed in this work showed an improvement of 700x.This work demonstrates both some causes behind single bit SEU failures for TMR circuits on FPGAs and mitigation techniques to address these failures. In addition to these findings, this work also shows that the majority of radiation failures in these circuits are caused by multiple cell upsets, laying the path for future work to further enhance the effectiveness of TMR on FPGAs.

Este trabalho tem dois objetivos principais. Primeiramente, estudamos as cópias complementadas de co(T) em espaços de Banach, onde T é um cardinal infinito. Estendemos ao caso não-enumerável um resultado clássico obtido por T. Schlumprecht que caracteriza as cópias complementadas de co em um espaço de Banach X. Usamos esta nova caracterização para estender resultados de G. Emmanuele, F. Bombal, D. Leung e F. Räbiger envolvendo as cópias complementadas de co nos espaços de Banach clássicos `p(I,X), onde p T[1, &#8734 ] e I é um conjunto não-vazio. Nós também provamos um novo resultado sobre as cópias complementadas de co(T) nos espaços Co(K,X), onde K é um espaço de Hausdor localmente compacto. Em seguida, estudamos uma extensão vetorial do clássico Teorema de Banach-Stone obtida por K. Jarosz. Estudando várias constantes introduzidas por R. James, J. Schäer, M. Baronti, E. Casini e P. Pappini, nós provamos uma nova relação entre os módulos de convexidade dos espaços Xe X*, que possui interesse independente. Esta relação é usada para provar uma nova reneralização vetorial do Teorema de Banach-Stone que simultaneamente estende o Teorema de Jarosz e também mostra que este último resultado é, de fato, uma consequência de um teorema obtido recentemente por F. Cidral, E. Galego e M. RincónVillamizar. / The goal of this work is two-fold. First, we study the complemented copies of co(T) in Banach spaces, where T is an innite cardinal. We extend to the uncountable case a classical result by T. Schulmprecht that characterizes the complemented copies of co in a Banach space X. We use this new characterization to extend results by G. Emmanuele, F. Bombal, D. Leung and F. Räbiger concerning the complemented copies of co in the classical Banach spaces `p(I,X), where p T[1, &#8734 ] and I is a non-empty set. We also obtain a new result involving the complemented copies of co(T) in Co(K,X) spaces, where Kis a locally compact Hausdor space. Next, we turn our attention to a vector-valued extension of the classical Banach-Stone theorem obtained by K. Jarosz. Studying several constants introduced by R. James, J. Schäffer, M. Baronti, E. Casini and P. Pappini, we obtain a new relationship between the moduli of convexity of Xand X*, which has independent interest. We then apply this relationship to prove a new X-valued generalization of the Banach-Stone theorem that simultaneously extends the aforementioned result by Jarosz and also shows that this result is, in fact, a consequence of a theorem obtained recently by F. Cidral, E. Galego and M. Rincón-Villamizar.

Este trabalho tem dois objetivos principais. Primeiramente, estudamos as cópias complementadas de co(T) em espaços de Banach, onde T é um cardinal infinito. Estendemos ao caso não-enumerável um resultado clássico obtido por T. Schlumprecht que caracteriza as cópias complementadas de co em um espaço de Banach X. Usamos esta nova caracterização para estender resultados de G. Emmanuele, F. Bombal, D. Leung e F. Räbiger envolvendo as cópias complementadas de co nos espaços de Banach clássicos `p(I,X), onde p T[1, &#8734 ] e I é um conjunto não-vazio. Nós também provamos um novo resultado sobre as cópias complementadas de co(T) nos espaços Co(K,X), onde K é um espaço de Hausdor localmente compacto. Em seguida, estudamos uma extensão vetorial do clássico Teorema de Banach-Stone obtida por K. Jarosz. Estudando várias constantes introduzidas por R. James, J. Schäer, M. Baronti, E. Casini e P. Pappini, nós provamos uma nova relação entre os módulos de convexidade dos espaços Xe X*, que possui interesse independente. Esta relação é usada para provar uma nova reneralização vetorial do Teorema de Banach-Stone que simultaneamente estende o Teorema de Jarosz e também mostra que este último resultado é, de fato, uma consequência de um teorema obtido recentemente por F. Cidral, E. Galego e M. RincónVillamizar. / The goal of this work is two-fold. First, we study the complemented copies of co(T) in Banach spaces, where T is an innite cardinal. We extend to the uncountable case a classical result by T. Schulmprecht that characterizes the complemented copies of co in a Banach space X. We use this new characterization to extend results by G. Emmanuele, F. Bombal, D. Leung and F. Räbiger concerning the complemented copies of co in the classical Banach spaces `p(I,X), where p T[1, &#8734 ] and I is a non-empty set. We also obtain a new result involving the complemented copies of co(T) in Co(K,X) spaces, where Kis a locally compact Hausdor space. Next, we turn our attention to a vector-valued extension of the classical Banach-Stone theorem obtained by K. Jarosz. Studying several constants introduced by R. James, J. Schäffer, M. Baronti, E. Casini and P. Pappini, we obtain a new relationship between the moduli of convexity of Xand X*, which has independent interest. We then apply this relationship to prove a new X-valued generalization of the Banach-Stone theorem that simultaneously extends the aforementioned result by Jarosz and also shows that this result is, in fact, a consequence of a theorem obtained recently by F. Cidral, E. Galego and M. Rincón-Villamizar.

Over the past couple of decades Field Programmable Gate Arrays (FPGAs) have become increasingly useful in a variety of domains. This is due to their low cost and flexibility compared to custom ASICs. This increasing interest in FPGAs has driven the need for tools that both qualify and improve the reliability of FPGAs for applications where the reconfigurability of FPGAs makes them vulnerable to radiation upsets such as in aerospace environments. Such tools ideally work with a wide variety of devices, are highly programmable but simple to use, and perform tasks at relatively high speeds. Of the various FPGA configuration interfaces available, the Joint Test Action Group (JTAG) standard for serial communication is the most universally compatible interface due to its use for verifying integrated circuits and testing printed circuit board connectivity. This universality makes it a good interface for tools seeking to access FPGA configuration memory. This thesis introduces a new tool architecture for high-speed, programmable JTAG access to FPGA configuration memory. This tool, called the JTAG Configuration Manager (JCM), is made up of a large C++ software library that runs on an embedded micro-processor coupled with a hardware JTAG controller module implemented in programmable logic. The JCM software library allows for the development of custom JTAG communication of any kind, although this thesis focuses on applications related to FPGA reliability. The JCM hardware controller module allows these software-generated JTAG sequences to be streamed out at very high speeds. Together the software and hardware provide the high-speed and programmability that is important for many JTAG applications.

En la presente tesis se propone una metodología de desarrollo de estrategias híbridas para la mitigación de fallos inducidos por radiación en los sistemas empotrados modernos. La propuesta se basa en los principios del co-diseño de sistemas y consiste en la combinación selectiva, incremental y flexible de enfoques de tolerancia a fallos basados en hardware y software. Es decir, la exploración del espacio de soluciones se fundamenta en una estrategia híbrida de grano fino. El flujo de diseño está guiado por los requisitos de la aplicación. Esta metodología se ha denominado: co-endurecimiento. De esta forma, es posible diseñar sistemas embebidos confiables a bajo coste, donde no sólo se satisfagan los requisitos de confiabilidad y las restricciones de diseño, sino que también se evite el uso excesivo de costosos mecanismos de protección (hardware y software).