La demande d’objets connectés dans notre société est très importante, au vu du marché florissant des smartphones. Ces nouveaux objets technologiques ont pour avantage de regrouper plusieurs fonctions en un seul objet ultra compact. Cette diversité est possible grâce à l’avènement des systèmes-sur-puce (SoC, System-on-Chip) et à la miniaturisation extrême des composants. Les SoC s’intègrent dans l’approche « More than Moore » et demande une superficie importante des puces. Celle-ci peut-être réduite par l’utilisation d’une autre approche appelée « More Moore » qui fut largement utilisée ces dernières années pour miniaturiser la taille des transistors. Cependant cette approche tend vers ses limites physiques puisque la réduction drastique de la taille des MOSFETs (« Metal Oxide Semicondutor Field Effect Transistor ») ne pourra pas être poursuivie à long terme. En outre, les transistors de taille réduite présentent des effets parasites, liés aux effets de canaux courts et à une mauvaise dissipation de la chaleur dégagée lors du fonctionnement des MOSFETs miniaturisés. Les effets de canaux courts peuvent-être minimisés grâce à de nouvelles architectures, telles que l’utilisation de nanofils, qui permettent d’obtenir une grille totalement enrobante du canal. Mais le problème de la puissance de consommation reste un frein pour le passage au prochain nœud technologique et pour l’augmentation des fonctions dans les appareils nomades. En effet, la puissance de consommation des MOSFETs ne fait qu’augmenter à chaque nouvelle génération, ce qui est en partie dû à l’accroissement des pertes énergétiques induites par la puissance statique de ces transistors. Pour diminuer celle-ci, la communauté scientifique a proposée plusieurs solutions, dont une des plus prometteuses est le transistor à effet tunnel (TFET). Car ce dispositif est peu sensible aux effets de canaux courts, et il peut fonctionner à de faibles tensions de drain et avoir un inverse de pente sous le seuil inférieur à 60mV/dec. L’objectif de la thèse est donc de fabriquer et de caractériser des transistors à effet tunnel à base de nanofil unique en silicium et silicium germanium. Nous présenterons la croissance et l’intégration des nanofils p-i-n en TFET. Puis nous avons étudié l’influence de certains paramètres sur les performances de ces transistors, et en particulier, l’effet du niveau de dopage de la source et du contrôle électrostatique de la grille sera discuté. Ensuite, l’augmentation des performances des TFETs sera montrée grâce à l’utilisation de semiconducteur à petit gap. En effet, nous insérons du germanium dans la matrice de silicium pour en diminuer le gap et garder un matériau compatible avec les techniques de fabrication de l’industrie de la microélectronique. Un modèle de simulation du courant tunnel bande à bande a été réalisé, se basant sur le modèle de Klaassen. Les mesures électriques des dispositifs seront comparées aux résultats obtenus par la simulation, afin d’extraire le paramètre B de la transition tunnel pour chacun des matériaux utilisés. Enfin nous présenterons les améliorations possibles des performances par une intégration verticale des nanofils. / The connected objects demand in our society is very important , given the successfull smartphone market. These newtechnological objects have the advantage to combine several functions in one ultra compact object. This diversity is possibledue to the advent of system-on-chip (SoC) and the components scaling down. The SoCs are into the More than Mooreapproach and require a large chips area, which can be reduced by the use of "More Moore" approach which was widelyused in recent years to scale down the transistors. However, this approach tends to physical limitations since the drasticscaling down of the MOSFETs ("Metal Oxide Field Efect Transistor Semicondutor") can not be continued in the future. Inaddition, the nanoŰMOSFET have parasitic efects, related to short-channel efects and a low heating dissipation. Theshort channel efects can be minimized thanks to new architectures, such as the use of nanowires, which enable a gate allaround of the channel. But the power consumption problem still drag on the transition to the next technology node and theaddition of new functions in mobile devices. Indeed, the MOSFETŠs consumed power increases with each new generation,which is mainly due to the static power increase of these transistors. To reduce it, the scientiĄc community has proposedseveral solutions, and one of the most promising is a tunnel efect transistor (TFET). Because this device exhibit lessshort-channel efects compared to the conventional MOSFET, it can operate at low drain voltages and their subthresholdslope could be lower than 60 mV/dec. The thesis aims are to fabricate and characterize tunneling transistors based onsingle silicon nanowire and silicon germanium. We will present the growth and integration of pŰiŰn nanowires TFET. Thenwe investigated the inĆuence of some parameters on the electrical performance of these transistors, in particular, the efectof the source doping level and the electrostatic gate control will be discussed. In the next part, the increase of TFETsperformance will be shown thanks to the small band-gap semiconductor use. Indeed, we insert germanium in the silicon dieto reduce the bandgap and keep a material compatible with the CMOS manufacturing. A band to band tunneling modelwas used to calculate the device current, based on the model Klaassen. Electrical measurements will be compared to thesimulated results, in order to extract the B parameter of tunnel transition for each materials used. Finally we will presentthe possible performance improvements thanks to the vertical nanowires integration.

La récupération d’énergie par effet thermoélectrique est une technologie fiable avec un grand potentiel. Dans la gamme des hautes températures, il est nécessaire que les générateurs thermoélectriques soient fabriqués à partir d’un matériau massif pour gagner en puissance électrique. Dans la littérature, la nanostructuration baisse la conductivité thermique et permet d’augmenter le rendement de conversion. Par contre, l’effet de la porosité n’est pas clarifié. Par contre, l’effet de la porosité est sujette à controverse.Dans ce travail, l’alliage Si80Ge20 type n est élaboré par mécanosynthèse. Ce matériau est typique pour les applications aux hautes températures (vers 800◦C). La poudre nanocristalline est compactée en matrice, `a froid puis `a chaud. En plus de la caractérisation microstructurale, l’évolution de la microstructure est caractérisée par microscopie fine et par diffraction des rayons X. Les propriétés thermoélectriques et mécaniques sont identifiées expérimentalement. Cette étude montre que la nanostructuration du matériau est préservée et que le meilleur facteur de mérite obtenu est légèrement supérieur à l’unité pour un état dense. Cependant, les échantillons poreux ont une faible conductivité électrique dû à la taille macroscopique des pores, ce qui limite leurs rendu thermoélectrique final.Par la suite, le comportement mécanique de la poudre est modélisé au moyen de simulations fondées sur la méthode des éléments discrets (DEM, Discrete Element Method). Cette démarche permet de suivre l’évolution de l’empilement de particules pendant la densification et d’accéder aux paramètres microstructuraux clés. Les microstructures numériques obtenues par la DEM sont ensuite utilisées pour des calculs de conductivités thermiques et électriques. Les échantillons sont modélisés par trois phases dépendantes de leurs propriétés : la matrice SiGe, les pores et les joints de grains. Contrairement aux mesures expérimentales, le rendement thermoélectrique est maximal pour 30% de nanoporosité résiduelle. Ce résultat peut être expliqué par un modèle analytique qui prend en compte la résistance thermique des joints de grains ainsi que l’évolution de la microstrcuture pendant le procédé de densification. Une alternative au procédé de mise en forme actuel est proposée pour synthétiser la microstructure optimale. / Energy recovery by thermoelectric effect is a promising technology which offers greatreliability. In the range of high temperatures, it is necessary that the thermoelectric generatorshave to be made of bulk material to increase electrical power. In the literature,nanostructuring decreases the thermal conductivity and therefore enhances the conversionefficiency. On the contrary, the effect of porosity is a matter of debate.In this work, n-type Si80Ge20 alloy prepared by mechanical alloying is investigated. It isa typical material for high temperature applications (around 800◦C). The nanocrystallinepowder is compacted uniaxially at room temperature and then hot pressed. In addition tothe microstructural characterization, thermoelectrical and mechanical properties are identifiedexperimentally. This study shows that the grain size is kept below 200nm. The bestmeasured figure of merit is slightly slightly larger than one for dense specimens. However,the porous samples have low electrical conductivity which limits their final thermoelectricrendering.The mechanical behaviour of the powder is modelled through simulations using thediscrete element method (DEM). This approach has the advantage of following the evolutionof particle rearrangement during densification and provides useful information onmicrostructural parameters. Numerical microstructures obtained from DEM simulationsare then used for calculations of thermal and electrical conductivities. The samples aremodelled by three phases according to their properties : SiGe matrix, pores and grainboundaries. The conductivities ratio is maximal for 30% of residual porosity. This resultis explained by the analytical model that takes into account the thermal resistance ofthe grain boundaries as well as microstructure evolution during the densification process.Based on these findings, an alternative processing route is proposed to build an optimizedmicrostructure.

Heteroepitaxial SiGeC layers have attracted immenseattention as a material for high frequency devices duringrecent years. The unique properties of integrating carbon inSiGe are the additional freedom for strain and bandgapengineering as well as allowing more aggressive device designdue to the potential for increased thermal budget duringprocessing. This work presents different issues on epitaxialgrowth, defect density, dopant incorporation and electricalproperties of SiGeC epitaxial layers, intended for variousdevice applications. Non-selective and selective epitaxial growth of Si1-x-yGexCy(0≤x≤30, ≤y≤0.02) layershave been optimized by using high-resolution x-ray reciprocallattice mapping. The incorporation of carbon into the SiGematrix was shown to be strongly sensitive to the growthparameters. As a consequence, a much smaller epitaxial processwindow compared to SiGe epitaxy was obtained. Differentsolutions to decrease the substrate pattern dependency (loadingeffect) of SiGeC growth have also been proposed. The key pointin these methods is based on reduction of surface migration ofthe adsorbed species on the oxide. In non-selective epitaxy,this was achieved by introducing a thin silicon polycrystallineseed layer on the oxide. The thickness of this seed layer had acrucial role on both the global and local loading effect, andon the epitaxial quality. Meanwhile, in selective epitaxy,polycrystalline stripes introduced around the oxide openingsact as migration barriers and reduce the loading effecteffectively. Chemical mechanical polishing (CMP) was performedto remove the polycrystalline stripes on the oxide. Incorporation and electrical properties of boron-doped Si1-x-yGexCylayers (x=0.23 and 0.28 with y=0 and 0.005) with aboron concentration in the range of 3x1018-1x1021atoms/cm3 have also been investigated. In SiGeClayers, the active boron concentration was obtained from thestrain compensation. It was also found that the boron atomshave a tendency to locate at substitutional sites morepreferentially compared to carbon. These findings led to anestimation of the Hall scattering factor of the SiGeC layers,which showed good agreement with theoretical calculations. Keywords:Silicon germanium carbon (SiGeC), Epitaxy,Chemical vapor deposition (CVD), Loading effect, Highresolution x-ray diffraction (HRXRD), Hall measurements, Atomicforce microscopy (AFM).

This thesis provides also a detailed stepwise guideline on the data analysis for scanning X-ray diffraction experiments at a modern synchrotron radiation source. / Halbleiterbasierte Spin-Qubits in elektrostatischen Quantenpunkten haben vor Kurzem ein technologisches Niveau erreicht, welches lange Kohärenzzeiten und hohe Fidelitäten ermöglicht. Diese Eigenschaften sind wichtig, um eine große Anzahl von Qubits zu realisieren, welche durch adiabatische Ladungstransporte miteiander verbunden werden sollen. Allerdings können lokale Fluktuationen der Gitterverspannung im aktiven Material die Spinzustände stören, da sie das elektrostatische Potential beeinflussen. Diese Arbeit untersucht die Gitterverspannung in funktionalen Loch-Spin-Qubits und in Bauelementen für kohärenten Elektronentransport, welche auf epitaktischen Ge/Si0.20Ge0.80 und Si/Si0.66Ge0.34 Heterostrukturen mit metallischen Elektroden basieren. Die experimentelle Herausforderung besteht darin, zugleich eine hohe Sensitivität für die Gitterdeformation und eine räumliche Auflösung auf der Nanometerskala zu erreichen. Dies wird durch rasternde Röntgenbeugungsmikroskopie an der Strahllinie ID01/ESRF ermöglicht, welche eine Abbildung des Verspannungstensors mit einer lateralen Auflösung von ≤ 50 nm in bis zu 10 nm-dünnen epitaktischen Quantentöpfen ermöglicht. Die Untersuchung von vier verschiedenen Quantenbauteilen zeigt Modulationen der Gitterverspannung von 10−4 − 10−3 auf, welche durch die Elektroden und die plastische Entspannung der Heterostruktur verursacht sind. Diese Modulationen werden in räumliche Fluktuationen der Bandkantenniveaus von einer Größenordnung von mehreren meV übersetzt, die damit ähnlich zu den Abständen der orbitalen Energieniveaus der Quantenpunkte sind. Folglich stellt diese Arbeit wichtige Informationen für die Realisierung eines skalierbaren Quantenprozessors durch eine Berücksichtigung der lokalen Materialeigenschaften bereit / Semiconductor spin qubits featuring gate-defined electrostatic quantum dots have recently reached a maturity level enabling long spin coherence times and high fidelity. These characteristics are of paramount importance in the realization of large arrays of qubits interconnected by adiabatic charge shuttling. However, spin coherence can be strongly affected by local fluctuations of the lattice strain in the active material, since they impact the electrostatic potential. This work explores strain fluctuations in functional hole spin qubits and coherent electron shuttling devices based on epitaxial Ge/Si0.20Ge0.80 and Si/Si0.66Ge0.34 heterostructures with metallic electrodes. The main experimental challenge is to simultaneously achieve high sensitivity to the lattice deformation together with nanoscale spatial resolution. These requirements are met by Scanning X-ray Diffraction Microscopy at the synchotron beamline ID01/ESRF, which allows spatial mapping with ≤ 50 nm lateral resolution of the strain tensor in quantum well layers as thin as 10 nm. The analysis of four different devices highlights local modulations of the strain tensor components in the range of 10−4 − 10−3 induced by the gate electrodes and the plastic relaxation of the heterostructure. By means of band perturbation calculations, these strain fluctuations are translated into spatial modulations of the band edge energy levels. These perturbations are found to be of a few meV and thus on a similar magnitude as the orbital energy of the quantum dots. As such, this work provides important information for the realization of a scalable quantum processor with coherent interconnects by considering local material properties.

SiGe is a significant enabling technology for therealization of integrated circuits used in high performanceoptical networks and radio frequency applications. In order tocontinue to fulfill the demands for these applications, newmaterials and device structures are needed. This thesis focuseson new materials and their integration into heterojunctionbipolar transistor (HBT) structures as well as using devicesimulations to optimize and better understand the deviceoperation. Specifically, a SiGeC HBT platform was designed,fabricated, and electrically characterized. The platformfeatures a non-selectively grown epitaxial SiGeC base,in situdoped polysilicon emitter, nickel silicide,LOCOS isolation, and a minimum emitter width of 0.4 μm.Alternately, a selective epitaxy growth in an oxide window wasused to form the collector and isolation regions. Thetransistors exhibited cutoff frequency (fT) and maximum frequency of oscillation (fMAX) of 40-80 GHz and 15-45 GHz, respectively.Lateral design rules allowed the investigation of behavior suchas transient enhanced diffusion, leakage current, and theinfluence of parasitics such as base resistance and CBC. The formation of nickel silicide on polysiliconSiGe and SiGeC films was also investigated. The formation ofthe low resistivity monosilicide phase was shown to occur athigher temperatures on SiGeC than on SiGe. The stability of themonosilicide was also shown to improve for SiGeC. Nickelsilicide was then integrated into a SiGeC HBT featuring aselectively grown collector. A novel, fully silicided extrinsicbase contact was demonstrated along with the simultaneousformation of NiSi on thein situdoped polysilicon emitter. High-resolution x-ray diffraction (HRXRD) was used toinvestigate the growth and stability of SiGeC base layers forHBT integration. HRXRD proved to be an effective, fast,non-destructive tool for monitoring carbon out-diffusion due tothe dopant activation anneal for different temperatures as wellas for inline process monitoring of epitaxial growth of SiGeClayers. The stability of the SiGe layer with 0.2-0.4 at% carbonwhen subjected to dopant activation anneals ranging from1020-1100&#176C was analyzed by reciprocal lattice mapping.It was found that as the substitutional carbon increases theformation of boron clusters due to diffusion is suppressed, buta higher density of carbon clusters is formed. Device simulations were performed to optimize the DC and HFperformance of an advanced SiGeC HBT structure with low baseresistance and small dimension emitter widths. The selectivelyimplanted collector (SIC) was studied using a design ofexperiments (DOE) method. For small dimensions the lateralimplantation straggle has a significant influence on the SICprofile (width). A significant influence of the SIC width onthe DC gain was observed. The optimized structure showedbalanced fT/fMAXvalues of 200+ GHz. Finally, SOI BJT transistorswith deep trench isolation were fabricated in a 0.25μmBiCMOS process and self-heating effects were characterized andcompared to transistors on bulk silicon featuring deep trenchand shallow trench isolation. Device simulations based on SEMcross-sections and SIMS data were performed and the resultscompared to the fabricated transistors. Key words:Silicon-Germanium(SiGe), SiGeC,heterojunction bipolar transistor(HBT), nickel silicide,selectively implanted collector(SIC), device simulation, SiGeClayer stability, high resolution x-ray diffraction(HRXRD),silicon-on-insulator(SOI), self-heating.

No description available.

This thesis evaluates the suitability of silicon-germanium technology for electronic systems intended for extreme environments, such as ambient temperatures outside of military specification (-55 degC to 125 degC) range and intense exposures to ionizing radiation. Silicon-germanium devices and circuits were characterized at cryogenic and high-temperatures (up to 300 degC) and exposed to ionizing radiation, providing empirical evidence that silicon-germanium is an excellent platform for terrestrial and space-based electronic applications.

Using bandgap engineering, silicon-germanium (SiGe) BiCMOS technology effectively combines III-V transistor performance with the cost and integration advantages associated with CMOS manufacturing. The suitability of SiGe technology for cryogenic and radiation-intense environments is well known, yet SiGe has been generally overlooked for applications involving extreme high temperature operation. This work is an investigation into the potential capabilities of SiGe technology for operation up to 300°C, including the development of packaging and testing procedures to enable the necessary measurements. At the device level, SiGe heterojunction bipolar transistors (HBTs), field-effect transistors (FETs), and resistors are verified to maintain acceptable functionality across the temperature range, laying the foundation for high temperature circuit design. This work also includes the characterization of existing bandgap references circuits, redesign for high temperature operation, validation, and further optimization recommendations. In addition, the performance of temperature sensor, operational amplifier, and output buffer circuits under extreme high temperature conditions is presented. To the author's knowledge, this work represents the first demonstration of functional circuits from a SiGe technology platform in ambient temperatures up to 300°C; furthermore, the optimized bandgap reference presented in this work is believed to show the best performance recorded across a 500°C range in a bulk-silicon technology platform.

No description available.

<p>SiGe is a significant enabling technology for therealization of integrated circuits used in high performanceoptical networks and radio frequency applications. In order tocontinue to fulfill the demands for these applications, newmaterials and device structures are needed. This thesis focuseson new materials and their integration into heterojunctionbipolar transistor (HBT) structures as well as using devicesimulations to optimize and better understand the deviceoperation. Specifically, a SiGeC HBT platform was designed,fabricated, and electrically characterized. The platformfeatures a non-selectively grown epitaxial SiGeC base,<i>in situ</i>doped polysilicon emitter, nickel silicide,LOCOS isolation, and a minimum emitter width of 0.4 μm.Alternately, a selective epitaxy growth in an oxide window wasused to form the collector and isolation regions. Thetransistors exhibited cutoff frequency (f_T) and maximum frequency of oscillation (f_MAX) of 40-80 GHz and 15-45 GHz, respectively.Lateral design rules allowed the investigation of behavior suchas transient enhanced diffusion, leakage current, and theinfluence of parasitics such as base resistance and C_BC. The formation of nickel silicide on polysiliconSiGe and SiGeC films was also investigated. The formation ofthe low resistivity monosilicide phase was shown to occur athigher temperatures on SiGeC than on SiGe. The stability of themonosilicide was also shown to improve for SiGeC. Nickelsilicide was then integrated into a SiGeC HBT featuring aselectively grown collector. A novel, fully silicided extrinsicbase contact was demonstrated along with the simultaneousformation of NiSi on the<i>in situ</i>doped polysilicon emitter.</p><p>High-resolution x-ray diffraction (HRXRD) was used toinvestigate the growth and stability of SiGeC base layers forHBT integration. HRXRD proved to be an effective, fast,non-destructive tool for monitoring carbon out-diffusion due tothe dopant activation anneal for different temperatures as wellas for inline process monitoring of epitaxial growth of SiGeClayers. The stability of the SiGe layer with 0.2-0.4 at% carbonwhen subjected to dopant activation anneals ranging from1020-1100&#176C was analyzed by reciprocal lattice mapping.It was found that as the substitutional carbon increases theformation of boron clusters due to diffusion is suppressed, buta higher density of carbon clusters is formed.</p><p>Device simulations were performed to optimize the DC and HFperformance of an advanced SiGeC HBT structure with low baseresistance and small dimension emitter widths. The selectivelyimplanted collector (SIC) was studied using a design ofexperiments (DOE) method. For small dimensions the lateralimplantation straggle has a significant influence on the SICprofile (width). A significant influence of the SIC width onthe DC gain was observed. The optimized structure showedbalanced f_T/f_MAXvalues of 200+ GHz. Finally, SOI BJT transistorswith deep trench isolation were fabricated in a 0.25μmBiCMOS process and self-heating effects were characterized andcompared to transistors on bulk silicon featuring deep trenchand shallow trench isolation. Device simulations based on SEMcross-sections and SIMS data were performed and the resultscompared to the fabricated transistors.</p><p><b>Key words:</b>Silicon-Germanium(SiGe), SiGeC,heterojunction bipolar transistor(HBT), nickel silicide,selectively implanted collector(SIC), device simulation, SiGeClayer stability, high resolution x-ray diffraction(HRXRD),silicon-on-insulator(SOI), self-heating.</p>