This thesis is composed of two designs: a PT (process, temperature) detector for 2¡ÑVDD output buffer with slew rate compensation, and a slew rate self-adjusting 2¡ÑVDD output buffer with PVT compensation. In the first topic, a PT detector for 2¡ÑVDD output buffer with slew-rate compensa-tion is proposed. The driving current of 2¡ÑVDD output stages varies provided that the process and temperature conditions are different. For example, the driving current of 2¡ÑVDD output stage will be low at poor PVT corners. By contrast, the driving current will be high at good PVT corners. The process corner and temperature of NMOS and PMOS should be detected by threshold voltage variation thereof, respectively, such that the slew rate compensation is feasible. The proposed sensors will carry out the PT de-tection and compensate the driving current based on the detected corner, such that the slew rate variation of the output stage will be reduced. The second topic is a slew rate self-adjusting 2¡ÑVDD output buffer with PVT compensation. An NMOS and PMOS process detector is proposed to detect the process corners of NMOS and PMOS, respectively, while the voltage and temperature sensor is proposed to detect the voltage and temperature variations by body effect.

This thesis is composed of two parts : a 3¡ÑVDD bidirectional mixed-voltage-tolerant I/O buffer, and a 2¡ÑVDD output buffer with process and temperature compensation. In the first topic, a 3¡ÑVDD bidirectional mixed-voltage-tolerant I/O buffer, which is able to tolerate 3¡ÑVDD using stacking transistors in the output stage, is proposed. These transistors are biased by corresponding voltage levels which are generated by a dynamic gate bias generator and a floating N-well circuit when transmitting or receiving signals. In order to prevent the input stage transistors from gate-oxide overstress, an NMOS clamping technique is used to block high input voltages. This design can receive and transmit 0.9 V to 5.0 V (0.9/1.2/1.8/2.5/3.3/5.0 V) signals, which has been implemented using TSMC 1P6M 0.18 £gm CMOS process. The second topic shows a 2¡ÑVDD output buffer with process and temperature compensation using 1P6M 0.18 £gm CMOS process. In this design, a novel process and temperature variation detector is proposed to detect the corners of NMOS and PMOS, respectively. The driving capability of the output stage is enhanced at those corners with low output currents. By contrast, the driving currents is reduced at those corners with high output currents to reduce the variation of output slew rate.

This thesis work primarily focuses on the applicability of sub-threshold source coupled logic (STSCL) for building digital circuits and systems that run at very low voltage and promise to provide desirable performance with excellent energy savings. Sectors like bio-engineering and smart sensors require the energy consumption to be effectively very low for long battery life. Alongside meeting the ultra-low power specification, the system must also be reliable, robust, and perform well under harsh conditions. In this thesis work, logic gates are designed and analyzed, using STSCL. These gates are further used for implementation of digital subsystems in small-sized smart dust sensors which would operate at very low supply voltages and consume extremely low power. For understanding the performance of STSCL with respect to ultra-low power and energy; a seven-stage ring oscillator, a 4-by-4 array multiplier, a fifth-order FIR filter and finally a fifty-fifth-order FIR filter were designed. The subcircuits and systems have been simulated for different supply voltages, scaling down to 0.2 V, at different temperature values (-20oC and 70oC) in both 45 nm and 65 nm process technologies. The chosen architectures for the FIR filters and array multiplier were conventional and essentially taken from traditional CMOS-based designs. The simulated results are studied, analyzed and compared with same CMOS-based digital circuits. The results show on the advantage of STSCL-based digital systems over CMOS. Simulation results provide an energy consumption of 1.1388 nJ for a fifty-fifth-order FIR filter, at low temperatures (-20oC), using STSCL logic, which is comparatively less than for the corresponding CMOS logic implementation.

This thesis is composed of two parts: a 3¡ÑVDD mixed-voltage-tolerant I/O buffer with 1¡ÑVDD CMOS standard device, and a PVT detector for 2¡ÑVDD output buffer with slew-rate compensation. In the first topic, a 3¡ÑVDD bidirectional mixed-voltage-tolerant I/O buffer, which has been implemented using a typical TSMC 0.18 £gm CMOS process, is proposed with a Dynamic gate bias voltage generator to provide appropriate gate drives for the stacked output stage. Besides, a Gate-tracking circuit and a Floating N-well technique are adopted to prevent 1¡ÑVDD device from gate-oxide overstress problems and leakage currents. The maximum data rate is simulated to be 166/166/166/100/80 MHz when VDDIO is 5.0/3.3/1.8/1.2/0.9 V, respectively, given an equivalent probe capacitive load of 10pF. The second topic is a process, voltage, and temperature¡]PVT¡^detector for 2¡ÑVDD output buffer with slew-rate compensation. The threshold voltage¡]Vth¡^ of PMOSs and NMOSs varying with process variation could be detected, respectively. In addition, the voltage and temperature variations could be monitored, respectively, by detecting different charging and discharging times of delay buffers at each PVT corner. By adjusting output currents, the slew rate of output signals could be compensated over 24¢H. Moreover, the maximum data rate with compensation is 133 MHz in contrast with 100 MHz without compensation when VDDIO ¡× 1.8 V, in transmitting mode.

abstract: As wireless communication enters smartphone era, more complicated communication technologies are being used to transmit higher data rate. Power amplifier (PA) has to work in back-off region, while this inevitably reduces battery life for cellphones. Various techniques have been reported to increase PA efficiency, such as envelope elimination and restoration (EER) and envelope tracking (ET). However, state of the art ET supply modulators failed to address high efficiency, high slew rate, and accurate tracking concurrently. In this dissertation, a linear-switch mode hybrid ET supply modulator utilizing adaptive biasing and gain enhanced current mirror operational transconductance amplifier (OTA) with class-AB output stage in parallel with a switching regulator is presented. In comparison to a conventional OTA design with similar quiescent current consumption, proposed approach improves positive and negative slew rate from 50 V/µs to 93.4 V/µs and -87 V/µs to -152.5 V/µs respectively, dc gain from 45 dB to 67 dB while consuming same amount of quiescent current. The proposed hybrid supply modulator achieves 83% peak efficiency, power added efficiency (PAE) of 42.3% at 26.2 dBm for a 10 MHz 7.24 dB peak-to-average power ratio (PAPR) LTE signal and improves PAE by 8% at 6 dB back off from 26.2 dBm power amplifier (PA) output power with respect to fixed supply. With a 10 MHz 7.24 dB PAPR QPSK LTE signal the ET PA system achieves adjacent channel leakage ratio (ACLR) of -37.7 dBc and error vector magnitude (EVM) of 4.5% at 26.2 dBm PA output power, while with a 10 MHz 8.15 dB PAPR 64QAM LTE signal the ET PA system achieves ACLR of -35.6 dBc and EVM of 6% at 26 dBm PA output power without digital pre-distortion (DPD). The proposed supply modulator core circuit occupies 1.1 mm2 die area, and is fabricated in a 0.18 µm CMOS technology. / Dissertation/Thesis / Doctoral Dissertation Electrical Engineering 2017

abstract: A wideband hybrid envelope tracking modulator utilizing a hysteretic-controlled three-level switching converter and a slew-rate enhanced linear amplifierer is presented. In addition to smaller ripple and lower losses of three-level switching converters, employing the proposed hysteresis control loop results in a higher speed loop and wider bandwidth converter, enabling over 80MHz of switching frequency. A concurrent sensor circuit monitors and regulates the flying capacitor voltage VCF and eliminates conventional required calibration loop to control it. The hysteretic-controlled three-level switching converter provides a high percentage of power amplifier supply load current with lower ripple, reducing the linear amplifier high-frequency current and ripple cancellation current, improving the overall system efficiency. A slew-rate enhancement (SRE) circuit is employed in the linear amplifier resulting in slew-rate of over 307V/us and bandwidth of over 275MHz for the linear amplifier. The slew-rate enhancement circuit provides a parallel auxiliary current path directly to the gate of the class-AB output stage transistors, speeding-up the charging or discharging of out- put without modifying the operating point of the remaining linear amplifier, while maintaining the quiescent current of the class-AB stage. The supply modulator is fabricated in 65nm CMOS process. The measurement results show the tracking of LTE-40MHz envelope with 93% peak efficiency at 1W output power, while the SRE is disabled. Enabling the SRE it can track LTE-80MHz envelope with peak efficiency of 91%. / Dissertation/Thesis / Doctoral Dissertation Electrical Engineering 2019

Active transient voltage compensator (ATVC) has been proposed to improve VR transient response at high slew rate load, which engages in transient periods operating in MHZ to inject high slew rate current in step up load and recovers energy in step down load. Main VR operates in low switching frequency mainly providing DC current. Parallel ATVC has largely reduced conduction and switching losses. Parallel ATVC also reduces the number of VR bulk capacitors. Combined linear and adaptive nonlinear control has been proposed to reduce delay times in the actual controller, which injects one nonlinear signal in transient periods and simplifies the linear controller design. Switching mode current compensator with nonlinear control in secondary side is proposed to eliminate the effect of opotocoupler, which reduces response times and simplifies the linear controller design in isolated DC-DC converters. A novel control method has been carried out in two-stage isolated DC-DC converter to simplify the control scheme and improve the transient response, allowing for high duty cycle operation and large step-down voltage ratio with high efficiency. A balancing winding network composed of small power rating components is used to mitigate the double pole-zero effect in complementary-controlled isolated DC-DC converter, which simplifies the linear control design and improves the transient response without delay time. A parallel post regulator (PPR) is proposed for wide range input isolated DC-DC converter with secondary side control, which provides small part of output power and most of them are handled by unregulated rectifier with high efficiency. PPR is easy to achieve ZVS in primary side both in wide range input and full load range due to 0.5 duty cycle. PPR has reduced conduction loss and reduced voltage rating in the secondary side due to high turn ratio transformer, resulting in up to 8 percent efficiency improvement in the prototype compared to conventional methods.

This master’s thesis deals with problems of analog differential converters, which are used in measuring circuits working in the current mode. The aim of this thesis is to propose a new voltage to current and current to voltage converter, that should influence measured frequency properties as little as possible. Commercial active elements are use to design converters. Active components are compared on the basis of properties as bandwidth and slew rate. Designed converters are simulated in Orcad PSpice program. Converters, of the best behavior are practically implemented and measured. Measured and simulated values are compared.

Testability is crucial in today’s complex industrial system on chips (SoCs), where sensitive on-chip analog voltages need to be measured. In such cases, an operational amplifier (opamp) is required to sufficiently buffer the signals before they can drive the chip pad and probe parasitics. A single-stage opamp offers an attractive choice since it is power efficient and eliminates the need for frequency compensation. However, it has to satisfy demanding specifications on its stability, input common mode range, output swing, settling time, closed-loop gain and offset voltage. In this work, the settling time performance of a conventional folded-cascode (FC) opamp is substantially improved. Settling time of an opamp consists of two major components, namely the slewing period and the linear settling period. In order to reduce the settling time significantly without incurring excessive area and power penalty, a prudent circuit implementation that minimizes both these constituents is essential. In this work, three different slew rate enhancement (SRE) circuits have been evaluated through extensive simulations. The SRE candidate providing robust slew rate improvement was combined with a current recycling folded cascode structure, resulting in lower slewing and linear settling time periods. Exhaustive simulations on a FC cascode amplifier with complementary inputs illustrate the effectiveness of these techniques in settling time reduction over all envisaged operating conditions.

ITC/USA 2015 Conference Proceedings / The Fifty-First Annual International Telemetering Conference and Technical Exhibition / October 26-29, 2015 / Bally's Hotel & Convention Center, Las Vegas, NV / Over the past several years DoD imposed constraints on test deliverables, requiring objective measures of test results, i.e., statistically defensible test and evaluation (SDT&E) methods and results. These constraints force the tester to employ statistical hypotheses, analyses and perhaps modeling to assess test results objectively, i.e., based on statistical metrics, probability of confidence and logical inference to supplement rather than rely solely on expertise, which is too subjective. Experts often disagree on interpretation. Numbers, although interpretable, are less variable than opinion. Logic, statistical inference and belief are the bases of testable, repeatable and refutable hypothesis and analyses. In this paper we apply linear regression modeling and analysis of variance (ANOVA) to time-space position information (TSPI) to determine if a telemetry (TM) antenna control unit (ACU) under test (AUT) tracks statistically, thus as efficiently, in C-band while receiving both C- and S-band signals. Together, regression and ANOVA compose a method known as analysis of covariance (ANCOVA). In this, the second of three papers, we use data from a range test, but make no reference to the systems under test, nor to causes of error. The intent is to present examples of tools and techniques useful for SDT&E methodologies in testing.