Advancements in power semiconductor and power converter technology have enabled new low-voltage (LV) and medium-voltage (MV) direct current (DC) distribution systems for a variety of applications. Power electronics converters and DC circuit breakers (DCCBs) are the key components of a DC system and are hence the focus of this work. The combination of growing power density requirements and higher voltages can result in enhanced electric field (E-field) intensities, leaving the system vulnerable to partial discharges (PDs). The manifestation of such PD events gradually degrades the insulation system of the equipment, reducing its lifetime and ultimately leading to total insulation failure. Therefore, inception E-field based insulation design guidelines are developed to help achieve zero-PD operation of power electronics systems with considerations for internal as well as external (surface) E-field distribution. Additionally, surface E-field mitigation methods are experimentally investigated using representative PCB coupons to provide suitable solutions for low air pressure applications. Consequently, E-field management methods consisting of geometry-based techniques are proposed for PCB-based systems to mitigate E-field magnitudes in areas of the system that are prone to peak stresses (e.g. surface interconnections and triple junctions, conductor discontinuities, critical airgaps etc.). Successful design examples are provided including that of a 16 kV rated PCB-based DC bus and a 540 V, 100 kW aircraft generator rectifier unit operating at up to 50,000 ft cruising altitudes. DC circuit breaker (DCCB) technology, though crucial to ensure the safety of DC systems, is still in the early stages of development. As protection devices, their reliable operation is paramount and the selection and sizing of their components are not trivial. In this regard, comprehensive design guidelines are developed for the DC solid-state circuit breaker (SSCB) to ensure that its functional requirements can be met. System analyses and modeling are performed to understand the interactions between the various components, i.e. solid-state device, metal oxide varistor (MOV), and their impact on the breaker operation. A 2.5 kV, 400 A SSCB prototype is designed and verified with experimental results to validate the design approach. Traditional MOV based voltage clamping circuits (VCC) used in solid-state circuit breakers (SSCBs) impose a high interruption voltage on the main solid-state device. The voltage burden arises from the material properties of the MOV which fixes its clamping voltage at a value more than twice its maximum continuous dc voltage rating. A novel and reliable VCC termed as the electronic MOV (eMOV) is proposed to decouple the peak clamping voltage of the MOV from the nominal dc voltage of the system aiming to improve the voltage suppression index (V SI = Vpk/Vdc) of the VCC, thereby reducing the peak system voltage and allowing easier insulation design. By virtue of the proposed circuit, a lower voltage rated device can be used for the main switch enabling higher system efficiency and power density. In all, this work aims to address insulation system design for power electronics converters and systems, ultimately to eliminate PD under specified working voltage conditions for improved electrical safety and insulation lifetime. The implications of high-density integration, unsuitable ambient conditions and higher system voltages are considered to develop a suitable design and assessment methodology for practicing engineers. Techniques to mitigate/ manage E-Field inside and outside (surface) solid dielectric are proposed to attain the above goal. Additionally, design guidelines are formulated for DC SSCBs which are essential to the safety of DC distribution systems and an enhanced VCC is proposed for the same to limit its clamping voltage for easier insulation design. / Doctor of Philosophy / The recent advancements in power conversion technology have promoted the development and use of DC distribution networks for a variety of applications (e.g. electric ships, aircrafts, electric vehicle charging stations etc.). The insulation system of typical power electronics equipment consists of multiple solid insulating media (e.g. PCB dielectric, potting material, conformal coat etc.) separated by air gaps in the assembly. The combination of higher operating voltages, power density targets and unfavorable ambient conditions (e.g. low air pressure) can pose a risk to the insulation system of the equipment, if not addressed. The electric field (E-Field) stresses at certain vulnerable areas can exceed breakdown values of the corresponding media, initiating localized electrical discharge events also called as partial discharges (PD). Internal discharges generally occur in the vicinity of material defects, conductor discontinuities or sharp geometric features, while surface discharges may occur along exposed conductor metallizations on insulator surfaces (at the interface of multiple media) or critical air gaps in the assembly. PD events, while not posing any imminent threat, can degrade the surrounding area over time to reduce the operating life of the system and in some cases may cause catastrophic failures. Therefore, irrespective of location, such PD events must be eliminated to improve the overall system lifetime and reliability. Therefore, the main focus of this work is to develop insulation design guidelines and methodologies to achieve zero-PD operation of power converters and DC circuit breakers (DCCBs), both of which are key components of DC systems. A generalized design guideline is proposed to help with the insulation design of power electronics systems. Design techniques are developed to reduce E-field magnitude at critical areas to avoid over-designing the insulation system. Successful converter-level design examples are provided to validate the proposed approaches. DCCB technology is still in the early stages of development. As a protection device, its reliable operation is paramount and the selection and sizing of its components are not trivial. Therefore, in addition to the above insulation design methodology, comprehensive design guidelines are developed for the solid-state device and voltage clamping circuit (VCC) of the DC solid-state circuit breaker (SSCB), to ensure that its functional requirements can be met. Additionally, a novel VCC is proposed for the same to limit its fault interruption voltage for easier insulation design. Both SSCB and VCC prototypes are built and successfully demonstrated in a fault current breaking application. Overall, this dissertation provides a reference for the design and assessment of next generation power electronics converters and DC circuit breakers, to address, specifically, the challenges to their insulation systems.

This dissertation presents a systematic design and demonstration of a novel solid-state DC circuit breaker. The mechanical circuit breaker is widely used in power systems to protect industrial equipment during fault or abnormal conditions. Compared with the slow and high-maintenance mechanical circuit breaker, the solid-state circuit breaker is capable of high-speed interruption of high currents without generating an arc, hence it is maintenance-free. Both the switch and the tripping unit are solid-state, which meet the requirements of precise protection and high reliability. The major challenge in developing and adopting a solid-state circuit breaker has been the lack of power semiconductor switches that have adequate current-carrying capability and interruption capability. The high-speed, high-current solid-state DC circuit breaker proposed and demonstrated here uses a newly-emerging power semiconductor switch, the emitter turn-off (ETO) thyristor as the main interruption switch. In order to meet the requirement of being a high-current circuit breaker, ETO parallel operation is needed. Therefore the major effort of this dissertation is dedicated to the development of a high-current (5000A) DC switch module that utilizes multiple ETOs in parallel. This work can also be used to develop an AC switch module by changing the asymmetrical ETOs used to symmetrical ETOs. An accurate device model of the ETO is needed for the development of the high-current DC switch module. In this dissertation a novel physics-base lumped charge model is developed for the ETO thyristor for the first time. This model is verified experimentally and used for the research and development of the emitter turn-off (ETO) thyristor as well as the DC switch module discussed in this dissertation. With the aid of the developed device model, the device current sharing between paralleled multiple ETO thyristors is investigated. Current sharing is difficult to achieve for a thyristor-type device due to the large device parameter variations and strong positive feedback mechanism in a latched thyristor. The author proposes the "DirectETO" concept that directly benefits from the high-speed capability of the ETO and strong thermal couplings among ETOs. A high-current DC switch module based on the DirectETO can be realized by directly connecting ETOs in parallel without the bulky current sharing inductors used in other current-sharing solutions. In order to achieve voltage stress suppression under high current conditions, the parasitic parameters, especially parasitic inductance in a high-current ETO switch module are studied. The Partial Element Equivalent Circuit (PEEC) method is used to extract the parasitics. Combined with the developed device model, the electrical interactions among multiple ETOs are investigated which results in structural modification for the solid-state DC switch module. The electro-thermal model of the DC switch module and the heatsink subsystem is used to identify the "thermal runaway" phenomenon in the module that is caused by the negative temperature coefficient of the ETO's conduction drop. The comparative study of the electro-thermal coupling identifies a strongly-coupled thermal network that increases the stability of the thermal subsystem. The electro-thermal model is also used to calculate the DC and transient thermal limit of the DC switch module. The high-current (5000A) DC switch module coupled with a solid state tripping unit is successfully applied as a high-speed, high-current solid-state DC circuit breaker. The experimental demonstration of a 5000A current interruption shows an interruption time of about 5 microseconds. This high-speed, high-current DC switch module can therefore be used in DC circuit breaker applications as well as other types of application, such as AC circuit breakers, transfer switches and fault current limiters. Since the novel solid-state DC circuit breaker is able to extinguish the fault current even before it reaches an uncontrollable level, this feature provides a fast-acting, current-limiting protection scheme for power systems that is not possible with traditional circuit breakers. The potential impact on the power system is also discussed in this dissertation. / Ph. D.

Cette thèse présente l'étude et la réalisation d'un disjoncteur statique tout silicium et intelligent pouvant fonctionner à haute température (200°C) pour des applications de type DC basse et moyenne tensions. Plusieurs applications dans l’aéronautique, l’automobile et les transports ferroviaires poussent les composants à semi-conducteur de puissance à être utilisés à haute température. Cependant, les Si-IGBT et Si-CoolMOSTM actuellement commercialisés ont une température de jonction spécifiée et estimée à 150°C et quelque fois à 175°C. L’une des faiblesses des convertisseurs provient de la réduction du rendement avec l’augmentation de la température de jonction des composants à semiconducteur de puissance qui peut amener à leur destruction. La solution serait d’utiliser des composants grand-gap (SiC, GaN), qui autorisent un fonctionnement à une température de jonction plus élevée ;mais ces technologies en plein essor ont un coût relativement élevé. Une solution alternative serait de faire fonctionner des composants en silicium à une température de jonction voisine de 200°C afin de conserver l’un des principaux intérêts du silicium en termes de coût. Avant de commencer, le premier chapitre portera sur un état de l’art des différentes techniques de protection aussi bien mécanique que statique afin d’identifier les éléments essentiels pour la réalisation du circuit de protection. Les disjoncteurs hybrides seront aussi abordés afin de voir comment ceux-ci arrivent à combler les lacunes des disjoncteurs mécaniques et purement électroniques (statiques). A partir du chapitre précédent, un disjoncteur statique intelligent de faible puissance sera réalisé afin de mieux cerner les différentes difficultés qui sont liées à ce type de disjoncteur. Le disjoncteur statique sera réalisé à partir de fonction analogique de telle façon à ce qui soit autonome et bas cout. Il en ressort que les inductances parasites ainsi que la température des composants à base de semi-conducteurs ont un impact significatif lors de la coupure.Le chapitre III portera sur une analyse non exhaustive, vis-à-vis de la température, de différents types d’interrupteurs contrôlés à base de semi-conducteur de puissance en s’appuyant sur plusieurs caractérisations électriques (test de conduction, tension de seuil, etc) afin de sélectionner le type d’interrupteur de puissance qui sera utilisé pour le chapitre IV. Comme il sera démontré, les composants silicium à super jonction peuvent se rapprocher du comportement des composants à base de carbure de silicium pour les basses puissances. Un disjoncteur statique 400V/63A (courant de court-circuit prédictible de 5kA) sera étudié et 4développé afin de mettre en pratique ce qui a été précédemment acquis et pour montrer la compétitivité du silicium pour cette gamme de puissance. / This thesis presents a study about a smart solid state circuit breaker which can work at 200°C forlow and medium voltage continuous applications. Some applications in aeronautics, automotive,railways, petroleum extraction push power semiconductor devices to operate at high junctiontemperature. However, current commercially available Si-IGBT and Si-CoolMOS have basically amaximum junction temperature specified and rated at 150°C and even 175°C. Indeed, the main problemin conventional DC-DC converters is the switching losses of power semiconductor devices (linked to thetemperature influence on carrier lifetime, on-state voltage, on-resistance and leakage current) whichdrastically increase with the temperature rise and may drive to the device failure. Then, the use of wideband gap semiconductor like SiC or GaN devices allows higher junction temperature operation (intheory about 500°C) and higher integration (smaller heatsink, higher switching frequency, smallconverter), but are still under development and are expensive technologies. In order to keep theadvantage of low cost silicon devices, a solution is to investigate the feasibility to operate such devicesat junction temperature up to 200°C.Before starting the first starting chapter is a stat of the art of protectives circuit technics as well asmechanics as statics in order to identify essentials elements to develop the protective circuit. Hybridprotective circuits are approached too.From the precedent chapter, a smart and low power solid state circuit breaker is realized to identifyproblems which are linked with this type of circuit breaker. Solid state circuit breaker is developed withanalog components in a way that is autonomous and low cost. It’s follow that stray inductance andtemperature have an important impact when a default occurs.Chapter III give an analyze on different silicon power semiconductor dice towards temperature5relying on statics and dynamics characteristics in order to find the best silicon power switch which beused in the chapter IV. It has been shown that super junction MOSFET has the same behavior at lowpower than silicon carbide MOSFET.Solid state circuit breaker (400V/63A) has been studied and developed, in order to use all theknowledge previously acquired and to show the competitively of the silicon for this power range.

The swift shift of the automotive industry towards electrification is primarily propelled by technological advancements in battery technology. To stay competitive and meet the new demands of the industry, there is a crucial need for novel ideas and innovation. Higher energy density and lower cost makes Battery Electric Vehicles (BEV) competitive and affordable for a wider range of customers. Component space requirements inside a BEV as well as the growing trend towards increasing the voltage of the system from 400 V to 800 V poses new challenges that has to be overcome. Mechanical contactors have the advantage of being simple and easy to use, with low conductive losses. However, they have some drawbacks, such as poor performance when switching under load, limitedability to interrupt fault currents and large controlpower usage. To address these issues, a bidirectional MOSFET configuration can be used to replace the current system. This configuration provides enhanced abilities to quickly suppress fault current, improve robustness, eliminate mechanical failure points, and perform pre-charge sequences without the need for a dedicated branch. Additionally, this configuration maintains current performance in a smaller volume. Within the Battery distribution unit (BDU), this configuration replaces several components, such as thermal fuses, HV contactors, pre-charge relays,pre-charge resistors, and breaker/pyro-fuses with high voltage solid-state components. This study aims to propose potential mitigation methods through a combination of literature survey and comprehensive analysis using Simscape/-MATLAB Simulink models of a fully operational BDU utilizing readily available market components for a 1.2 kV system. The developed model illustrates the thermaland electrical performance of solid-state components in diverse testing scenarios, while maintaining their expected lifecycle. Additionally, sensitivity analysis is conducted using the proposed model to identify themost crucial design parameters within the system. The resulting system performs satisfactory during normal operations, albeit with ten times higher conductive losses attributed to the elevated junction resistance when compared to contactors.Consequently, additional cooling measures are required during harsh operations and DC fast charge. However, the required magnitization energy for a contactor does over time equate or even surpass the MOSFETs conductive losses. The design has established the feasibility of leveraging the primary switchfor pre-charge sequence execution, thus eliminating the need for a dedicated pre-charge branch. The system exhibits strong potential for interrupting both resistive and direct shorts at various locations in the model. However, the low system inductance and the need to avoid introducing any additional inductance into the system renders fault scenarios heavily dependent on said parameter. In conclusion, the proposed model exhibits considerable potential to eliminate numerous auxiliary components therefore reducing losses and offer a more adaptable and consolidated solution. Resulting in a smaller physical footprint and more favorable positioning within the BDU. Moreover, the financial analysis of the system highlights promising prospects for its integration into the drivetrain with the growingmarket trends.

Desire for low-power, high performance computing has been at core of the symbiotic union between digital circuits and CMOS scaling. While digital circuit performance improves with device scaling, analog circuits have not gained these benefits. As a result, it has become necessary to leverage increased digital circuit performance to mitigate analog circuit deficiencies in nanometer scale CMOS in order to realize world class analog solutions. In this thesis, both circuit and system enhancement techniques to improve performance of clock generators are discussed. The following techniques were developed: (1) A digital PLL that employs an adaptive and highly efficient way to cancel the effect of supply noise, (2) a supply regulated DPLL that uses low power regulator and improves supply noise rejection, (3) a digital multiplying DLL that obviates the need for high-resolution TDC while achieving sub-picosecond jitter and excellent supply noise immunity, and (4) a high resolution TDC based on a switched ring oscillator, are presented. Measured results obtained from the prototype chips are presented to illustrate the proposed design techniques. / Graduation date: 2013 / Access restricted to the OSU Community at author's request from July 16, 2012 - July 16, 2014