Metal-oxide-semiconductor field-effect transistors (MOSFETs) are major devices inintegrated circuit, extensively used in various electronic products. In order to improve the electrical characteristics, scaling channel width and length, using high-£e gate dielectric insulator, and strained silicon may be utilized to increase the driving current and circuit speed. Nevertheless, the scaling of the channel width and length must overcome the limitation of the photolithographytechnology and cost. Once the method is employed, the MOSFETs will face a serious short-channel effect and gate leakage current. In the aspect of high-£e gate dielectric insulator, there still have problems, containing the trap states, phonon scattering, dipole-induced threshold voltage variation, needed to be solved. This dissertation focuses on the properties of MOSFETs experienced an external-mechanical strain, where the channel will be strained. Hence, the mobility, driving current, and circuit speed will increase. Our research can be divided into three topics: fabricating process-induced strained Si, external mechanical stress-induced strained Si, and the properties of strained Si MOSFETs at different temperatures. Except the electrical measurement, we also used the ISE-TCAD to simulate the electrical characteristic of MOSFETs under stress. Firstly, we apply the stress on n-MOSFETs by utilizing the nitride-capping layer. Once the lattice is strained, the mobility will increase, hence resulting in the operating speed. Secondly, the electrical characteristics under external stress is explored by introduced the external mechanical stress along the channel length of nMOSFETs. In addition to the fabricating process-induced strain, the fabricating process condition will also influence the device characteristics. As a result, we propose a new strain technology for our following research. Thirdly, the device performance of strained Si under different temperatures is investigated. Finally, we discuss the gate leakage current in strained Si depending on the ultra-thin gate oxide layer.

abstract: Nanoscale semiconductors with their unique properties and potential applications have been a focus of extensive research in recent years. There are many ways in which semiconductors change the world with computers, cell phones, and solar panels, and nanoscale semiconductors having a promising potential to expand the efficiency, reduce the cost, and improve the flexibility and durability of their design. In this study, theoretical quantum mechanical simulations were performed on several different nanoscale semiconductor materials, including graphene/phosphorene nanoribbons and group III-V nanowires. First principles density functional theory (DFT) was used to study the electronic and structural properties of these nanomaterials in their fully relaxed and strained states. The electronic band gap, effective masses of charge carriers, electronic orbitals, and density of states were most commonly examined with strain, both from intrinsic and external sources. For example, armchair graphene nanoribbons (AGNR) were found to have unprecedented band gap-strain dependence. Phosphorene nanoribbons (PNRs) demonstrate a different behavior, including a chemical scissors effect, and studies revealed a strong relationship between passivation species and band gap tunability. Unlike the super mechanical flexibility of AGNRs and PNRs which can sustain incredible strain, modest yet large strain was applied to group III-V nanowires such as GaAs/InAs. The calculations showed that a direct and indirect band gap transition occurs at some critical strains and the origination of these gap transitions were explored in detail. In addition to the pure nanowires, GaAs/InAs core/shell heterostructure nanowires were also studied. Due to the lattice mismatch between GaAs and InAs, the intrinsic strain in the core/shell nanowires demonstrates an interesting behavior on tuning the electronic properties. This interesting behavior suggests a mechanical way to exert compressive strain on nanowires experimentally, and can create a finite quantum confinement effect on the core. / Dissertation/Thesis / Doctoral Dissertation Physics 2016

Este trabalho apresenta o estudo do efeito de elevação atípica da transcondutância na região linear de polarização devido ao efeito de corpo flutuante induzido pela porta (Gate Induced Floating Body Effect - GIFBE) de transistores da tecnologia SOI nMOSFET. Este estudo foi realizado com base em resultados experimentais e em simulações numéricas, as quais foram essenciais para o entendimento físico deste fenômeno. Além de contribuir com a explicação física deste fenômeno, este trabalho explora o efeito de corpo flutuante em diferentes estruturas (transistor de porta única, transistor de porta gêmea, transistor de múltiplas portas e transistores de canal tensionado), diferentes tecnologias e em função da temperatura (100K a 450K). A partir do estudo realizado em dispositivos SOI de porta única analisouse a influência das componentes da corrente de porta que tunelam através do óxido de porta do dispositivo, o potencial da região neutra do corpo do transistor, a taxa de recombinação de portadores, o impacto da redução da espessura do óxido de porta e também as dimensões físicas do transistor. Na análise feita da redução do comprimento de canal, verificou-se também que o GIFBE tende a ser menos significativo para dispositivos ultra-submicrométricos. Analisou-se também o efeito da elevação atípica da transcondutância para transistores SOI totalmente depletados, para os quais, este efeito ocorre apenas quando a segunda interface está acumulada, para as duas tecnologias estudadas (65nm e 130nm). A análise dos dispositivos de porta gêmea, que tradicionalmente são usados com a finalidade de minimizar o efeito de elevação abrupta de corrente de dreno, mostrou uma redução do GIFBE para este tipo de estrutura quando comparada à de porta única devido ao aumento da resistência série intrínseca à estrutura. O efeito de corpo flutuante também foi avaliado em função da temperatura de operação dos dispositivos. Para temperaturas variando de 100K a 450K, notou-se que o valor do limiar de GIFBE aumentou tanto para temperaturas acima de 300K quanto abaixo da mesma. Quando estes resultados são apresentados graficamente, observa-se que o comportamento do limiar de GIFBE com a temperatura resulta no formato de uma letra C, onde o valor mínimo está a 300K. Este comportamento se deve à competição entre o processo de recombinação e a degradação efetiva da mobilidade. Uma primeira análise do GIFBE em diferentes estruturas de transistores também foi realizada. Apesar dos transistores de canal tensionado apresentarem o efeito para valores menores de tensão de porta, este efeito se manifesta com menor intensidade nestes transistores, devido a alta degradação da mobilidade efetiva apresentada pelo mesmo. Entretanto, quando o foco são os transistores de múltiplas portas, os resultados obtidos demonstram que apesar destes dispositivos terem sido fabricados com dielétrico de porta de alta constante dielétrica, o GIFBE ainda ocorre. Esta ocorrência do GIFBE em FinFETs é fortemente dependente da largura do Fin, da dopagem da região de canal e conseqüentemente do acoplamento das portas laterais com a superior. / This work presents the study of the Gate Induced Floating Body Effect (GIFBE) that occurs in the SOI MOSFET technology. This study has been performed based on experimental results and on numerical simulations, which were an essential auxiliary tool to obtain a physical insight of this effect. Besides the contribution on the physical explanation of this phenomenon, in this work, the floating body effect was evaluated for different structures (single gate and twin-gate transistors), different technologies (130nm and 65nm SOI CMOS technology) and as a function of the temperature (100K to 450K). From the study of the single gate devices, it was evaluated the gate tunneling current influence on GIFBE, the body potential in the neutral region, the recombination rate, the front gate oxide thickness reduction impact, besides the physical dimensions of the transistor. In the performed analysis, taking into account the channel length reduction, it was verified that the GIFBE tends to be less important for ultra-submicron devices. The GIFBE only occurs for fully depleted devices when the second interface is accumulated. In this situation, the floating body effect influence on fully depleted devices was also studied for both technologies (65nm and 130nm). The twin-gate devices analysis, that traditionally are used in order to minimize the Kink effect, show a GIFBE reduction for this structure when it is compared to the single gate one. This enhance in the electrical characteristics is due to the series resistance increase that is intrinsic of this structures. When the temperature variation from 100K to 450K was analyzed, it was obtained the C shape behavior for the floating body effect due to a competition between the recombination process and the effective mobility degradation factor. A first evaluation of the GIFBE occurrence in new devices was also performed. When the focus is the strained silicon transistor, a occurrence of GIFBE was obtained for a lower gate voltage. Although, the GIFBE occurs earlier for strained transistor. This effect is less pronounced in this device because it presents strong effective mobility degradation. When the focus is FinFETs, the results show that although this device was fabricated with a high-k gate dielectric, the GIFBE still occurs and is strongly dependent on the device channel width.

We present a comprehensive investigation of the low-¯eld hole mobility in strained Ge and III-V (GaAs, GaSb, InSb and In1¡xGaxAs) p-channel inversion layers with both SiO2 and high-· insulators. The valence (sub)band structure of Ge and III-V channels, relaxed and under strain (tensile and compressive) is calculated using an effcient self-consistent method based on the six-band k ¢ p perturbation theory. The hole mobility is then computed using the Kubo-Greenwood formalism accounting for non-polar hole-phonon scattering (acoustic and optical), surface roughness scatter- ing, polar phonon scattering (III-Vs only), alloy scattering (alloys only) and remote phonon scattering, accounting for multi-subband dielectric screening. As expected, we find that Ge and III-V semiconductors exhibit a mobility significantly larger than the \universal" Si mobility. This is true for MOS systems with either SiO2 or high-k insulators, although the latter ones are found to degrade the hole mobility compared to SiO2 due to scattering with interfacial optical phonons. In addition, III-Vs are more sensitive to the interfacial optical phonons than Ge due to the existence of the substrate polar phonons. Strain { especially biaxial tensile stress for Ge and biaxial compressive stress for III-Vs (except for GaAs) { is found to have a significant beneficial effect with both SiO2 and HfO2. Among strained p-channels, we find a large enhancement (up to a factor of 10 with respect to Si) of the mobility in the case of uniaxial compressive stress added on a Ge p-channel similarly to the well-known case of Si. InSb exhibits the largest mobility enhancement. In0:7Ga0:3As also exhibits an increased hole mobility compared to Si, although the enhancement is not as large. Finally, our theoretical results are favorably compared with available experimental data for a relaxed Ge p-channel with a HfO2 insulator.

Origami-based approaches for the folding of thick materials for specific application to large deployable space arrays is explored in this work. The folding approaches presented utilize strain energy, spatial kinematics, membranes, compliant mechanisms, and or in combination together to fold finite-thickness materials viewed through the lens of origami-based engineering. Novel architectures and behaviors of mechanisms are developed to achieve packaging efficiency, deployment, and self-stiffening. A method for the folding of monolithic thick-sheet materials is developed by incorporating compliant mechanisms into the material itself to strategically add degrees of freedom. The design and characterization of the compliant mechanisms with consideration to stress, material selection, and stiffness is given. Other folding approaches developed include a bistable vertex and a double-membrane method.The folding approaches derived are applied to larger tessellations and folding patterns. The fold patterns developed and used lend themselves well to large reconfiguration and the combination of the folding approaches with the patterns create opportunities to fabricate products out of thick, functional materials. Of specific interest is the application of these approaches and patterns to the field of deployable space arrays. Spatial kinematics, computational dynamics, physical tests, and systems engineering are used to develop an array architecture that is self-deployable, self-stiffening, and retractable. This architecture is shown to open the design space of large deployable arrays by increasing packaging efficiency and mass.The method, approaches, and architectures developed by this dissertation contribute to the fields origami-based engineering and deployable space arrays. While a focus of this work is the advancement of space technologies, the depth of the analyses provided are transferable to other origami-based and compliant-mechanism disciplines.

Este trabalho apresenta o estudo do comportamento da resistência série de fonte e dreno em transistores SOI FinFET de porta tripla e com canal tensionado. Nos dispositivos SOI FinFETs há um aumento da resistência série de fonte e dreno devido ao estreitamento dessas regiões, sendo esse parâmetro considerado como uma das limitações quanto à introdução desses dispositivos em tecnologias futuras. O uso de tensão mecânica no canal dos dispositivos surge como alternativa para aumentar a condução de corrente através do aumento da mobilidade dos portadores do canal, reduzindo assim, a resistência total dos transistores e, conseqüentemente, a resistência série de fonte e dreno. Inicialmente, foi feito o estudo de alguns métodos de extração da resistência série de fonte e dreno existentes na literatura, com o objetivo de se obter o mais adequado para aplicação e análise posterior. Esse trabalho foi realizado baseado em resultados experimentais e em simulações numéricas que possibilitaram o entendimento físico do fenômeno estudado. A resistência série de fonte e dreno foi explorada em diferentes tecnologias, como transistores SOI FinFETs de porta tripla convencionais e sob influência de tensionamento uniaxial e biaxial. O uso do crescimento seletivo epitaxial (SEG) nas regiões de fonte e dreno altamente dopadas das diferentes tecnologias também foi analisado, pois com essa técnica, a resistência série de fonte e dreno é reduzida substancialmente não comprometendo a condução de corrente e a transcondutância. Os resultados obtidos das diferentes tecnologias com e sem o uso de SEG foram analisados e comparados mostrando que em transistores SOI FinFETs de porta tripla, com crescimento seletivo epitaxial, apresentam o menor valor da resistência série de fonte e dreno mesmo para aqueles sem tensão mecânica na região do canal. / This work presents the study of the source and drain series resistance behavior in standard and strained SOI FinFETs triple gate transistors. In SOI FinFETs transistors there is an increase of the source and drain series resistance due to the narrow of these regions, being this parameter a key limiting factor to the next generations. The use of strained transistors is one of the potential technologies to the next generation high performance because it increase the drive current through an enhance in the carrier mobility, decreasing the transistors total resistance and, therefore, the source and drain series resistance. Initially, a study of some series resistance extraction methods, present in the literature was done, in order to obtain the most appropriate for applications and analysis subsequent. This work was done based on experimental results and numerical simulations, enabling the physical understanding of the phenomenon studied. The series resistance was explored in different technologies, as standard SOI FinFETs triple gates and with uniaxial and biaxial strain. The use of selective epitaxial growth (SEG) in the source and drain regions, with high doping levels, was also studied in the different technologies, because with the use of this technique, the series resistance decreases substantially without compromising the drive current and transconductance. The obtained results from the different technologies with and without the use of SEG were analyzed and compared showing that, SOI FinFETs triple gate transistors with SEG present the lower values of series resistance even for standard devices if compared with strained ones without the use of SEG.

Este trabalho apresenta o estudo da influência do tensionamento mecânico (strain) no efeito de abaixamento de barreira induzido pelo dreno (DIBL) em dispositivos SOI FinFETs de porta tripla com e sem crescimento seletivo epitaxial. Também é analisada a influência do uso de crescimento seletivo epitaxial nesses dispositivos em relação ao efeito de canal curto mencionado. O uso de transistores verticais de múltiplas portas tem permitido a continuidade do escalamento dos dispositivos, apresentando melhora nos níveis de corrente bem como a supressão dos efeitos de canal curto. No entanto, ao reduzir a largura do canal, aumenta-se a resistência total do transistor, diminuindo seu desempenho. A fim de melhorar essa característica, as técnicas de tensionamento mecânico e crescimento de fonte e dreno tem sido empregadas. No primeiro caso, ao se deformar mecanicamente a estrutura do canal, altera-se o arranjo das camadas eletrônicas que ocasiona o aumento da mobilidade dos portadores. Conseqüentemente, a corrente aumenta tal como a transcondutância do dispositivo. A técnica de crescimento de fonte e dreno chamada de crescimento seletivo epitaxial (SEG) tem como finalidade reduzir ainda mais a resistência elétrica total da estrutura, uma vez que a área dessas regiões aumenta, possibilitando o aumento das áreas de contato, que são responsáveis pela maior parcela da resistência total. Esse trabalho baseia-se em resultados experimentais e simulações numéricas tridimensionais que analisam o comportamento dos transistores com as tecnologias acima apresentadas em função do efeito de DIBL. / This work presents a study about the influence of strain in the drain induced barrier lowering effect (DIBL) in triple gate SOI FinFETs. Also it is analyzed the selective epitaxial growth used in that structures, comparing their behavior in relation to DIBL effect. Using the vertical multi-gate devices become possible the downscale whereas they present higher current level and suppressed short channel effects. However, reducing the channel width, the transistors total resistance increases and consequently its performance decreases. In order to improve this feature, the strained technology and the Source/Drains growth technique has been employed. In the first case, the mechanical deformation causes a change in the electron shell, which improves the carrier mobility. Consequently, the current level and the transconductance also improve. The selective epitaxial growth technique aims to reduce the devices total resistance since these regions areas increase, allowing large contacts which are responsible for the main parcel of the total resistance. This work is based on experimental results and tridimensional simulations that analyze the transistor behavior using the technologies above presented as a function of DIBL effect.

Este trabalho apresenta o estudo do comportamento da resistência série de fonte e dreno em transistores SOI FinFET de porta tripla e com canal tensionado. Nos dispositivos SOI FinFETs há um aumento da resistência série de fonte e dreno devido ao estreitamento dessas regiões, sendo esse parâmetro considerado como uma das limitações quanto à introdução desses dispositivos em tecnologias futuras. O uso de tensão mecânica no canal dos dispositivos surge como alternativa para aumentar a condução de corrente através do aumento da mobilidade dos portadores do canal, reduzindo assim, a resistência total dos transistores e, conseqüentemente, a resistência série de fonte e dreno. Inicialmente, foi feito o estudo de alguns métodos de extração da resistência série de fonte e dreno existentes na literatura, com o objetivo de se obter o mais adequado para aplicação e análise posterior. Esse trabalho foi realizado baseado em resultados experimentais e em simulações numéricas que possibilitaram o entendimento físico do fenômeno estudado. A resistência série de fonte e dreno foi explorada em diferentes tecnologias, como transistores SOI FinFETs de porta tripla convencionais e sob influência de tensionamento uniaxial e biaxial. O uso do crescimento seletivo epitaxial (SEG) nas regiões de fonte e dreno altamente dopadas das diferentes tecnologias também foi analisado, pois com essa técnica, a resistência série de fonte e dreno é reduzida substancialmente não comprometendo a condução de corrente e a transcondutância. Os resultados obtidos das diferentes tecnologias com e sem o uso de SEG foram analisados e comparados mostrando que em transistores SOI FinFETs de porta tripla, com crescimento seletivo epitaxial, apresentam o menor valor da resistência série de fonte e dreno mesmo para aqueles sem tensão mecânica na região do canal. / This work presents the study of the source and drain series resistance behavior in standard and strained SOI FinFETs triple gate transistors. In SOI FinFETs transistors there is an increase of the source and drain series resistance due to the narrow of these regions, being this parameter a key limiting factor to the next generations. The use of strained transistors is one of the potential technologies to the next generation high performance because it increase the drive current through an enhance in the carrier mobility, decreasing the transistors total resistance and, therefore, the source and drain series resistance. Initially, a study of some series resistance extraction methods, present in the literature was done, in order to obtain the most appropriate for applications and analysis subsequent. This work was done based on experimental results and numerical simulations, enabling the physical understanding of the phenomenon studied. The series resistance was explored in different technologies, as standard SOI FinFETs triple gates and with uniaxial and biaxial strain. The use of selective epitaxial growth (SEG) in the source and drain regions, with high doping levels, was also studied in the different technologies, because with the use of this technique, the series resistance decreases substantially without compromising the drive current and transconductance. The obtained results from the different technologies with and without the use of SEG were analyzed and compared showing that, SOI FinFETs triple gate transistors with SEG present the lower values of series resistance even for standard devices if compared with strained ones without the use of SEG.

The continuous and aggressive dimensional miniaturization ofthe conventional complementary-metal-oxide semiconductor (CMOS)architecture has been the main impetus for the vast growth ofIC industry over the past decades. As the CMOS downscalingapproaches the fundamental limits, unconventional materials andnovel device architectures are required in order to guaranteethe ultimate scaling in device dimensions and maintain theperformance gain expected from the scaling. This thesisinvestigates both unconventional materials for the gate stackand the channel and a novel notched-gate device architecture,with the emphasis on the challenging issues in processintegration. High-κ gate dielectrics will become indispensable forCMOS technology beyond the 65-nm technology node in order toachieve a small equivalent oxide thickness (EOT) whilemaintaining a low gate leakage current. HfO2and Al2O3as well as their mixtures are investigated assubstitutes for the traditionally used SiO2in our MOS transistors. These high-κ filmsare deposited by means of atomic layer deposition (ALD) for anexcellent control of film composition, thickness, uniformityand conformality. Surface treatments prior to ALD are found tohave a crucial influence on the growth of the high-κdielectrics and the performance of the resultant transistors.Alternative gate materials such as TiN and poly-SiGe are alsostudied. The challenging issues encountered in processintegration of the TiN or poly-SiGe with the high-k are furtherelaborated. Transistors with TiN or poly-SiGe/high-k gate stackare successfully fabricated and characterized. Furthermore,proof-of-concept strained-SiGe surface-channel pMOSFETs withALD high-κ dielectrics are demonstrated. The pMOSFETs witha strained SiGe channel exhibit a higher hole mobility than theuniversal hole mobility in Si. A new procedure for extractionof carrier mobility in the presence of a high density ofinterface states found in MOSFETs with high-κ dielectricsis developed. A notched-gate architecture aiming at reducing the parasiticcapacitance of a MOSFET is studied. The notched gate is usuallyreferred to as a local thickness increase of the gatedielectric at the feet of the gate above the source/drainextensions. Two-dimensional simulations are carried out toinvestigate the influence of the notched gate on the static anddynamic characteristics of MOSFETs. MOSFETs with optimizednotch profile exhibit a substantial enhancement in the dynamiccharacteristics with a negligible effect on the staticcharacteristics. Notched-gate MOSFETs are also experimentallyimplemented with the integration of a high-κ gatedielectric and a poly-SiGe/TiN bi-layer gate electrode. Key words:CMOS technology, MOSFET, high-κ, gatedielectric, ALD, surface pre-treatment, metal gate, poly-SiGe,strained SiGe, surface-channel, buried-channel, notchedgate.

<p>The continuous and aggressive dimensional miniaturization ofthe conventional complementary-metal-oxide semiconductor (CMOS)architecture has been the main impetus for the vast growth ofIC industry over the past decades. As the CMOS downscalingapproaches the fundamental limits, unconventional materials andnovel device architectures are required in order to guaranteethe ultimate scaling in device dimensions and maintain theperformance gain expected from the scaling. This thesisinvestigates both unconventional materials for the gate stackand the channel and a novel notched-gate device architecture,with the emphasis on the challenging issues in processintegration.</p><p>High-κ gate dielectrics will become indispensable forCMOS technology beyond the 65-nm technology node in order toachieve a small equivalent oxide thickness (EOT) whilemaintaining a low gate leakage current. HfO₂and Al₂O₃as well as their mixtures are investigated assubstitutes for the traditionally used SiO₂in our MOS transistors. These high-κ filmsare deposited by means of atomic layer deposition (ALD) for anexcellent control of film composition, thickness, uniformityand conformality. Surface treatments prior to ALD are found tohave a crucial influence on the growth of the high-κdielectrics and the performance of the resultant transistors.Alternative gate materials such as TiN and poly-SiGe are alsostudied. The challenging issues encountered in processintegration of the TiN or poly-SiGe with the high-k are furtherelaborated. Transistors with TiN or poly-SiGe/high-k gate stackare successfully fabricated and characterized. Furthermore,proof-of-concept strained-SiGe surface-channel pMOSFETs withALD high-κ dielectrics are demonstrated. The pMOSFETs witha strained SiGe channel exhibit a higher hole mobility than theuniversal hole mobility in Si. A new procedure for extractionof carrier mobility in the presence of a high density ofinterface states found in MOSFETs with high-κ dielectricsis developed.</p><p>A notched-gate architecture aiming at reducing the parasiticcapacitance of a MOSFET is studied. The notched gate is usuallyreferred to as a local thickness increase of the gatedielectric at the feet of the gate above the source/drainextensions. Two-dimensional simulations are carried out toinvestigate the influence of the notched gate on the static anddynamic characteristics of MOSFETs. MOSFETs with optimizednotch profile exhibit a substantial enhancement in the dynamiccharacteristics with a negligible effect on the staticcharacteristics. Notched-gate MOSFETs are also experimentallyimplemented with the integration of a high-κ gatedielectric and a poly-SiGe/TiN bi-layer gate electrode.</p><p><b>Key words:</b>CMOS technology, MOSFET, high-κ, gatedielectric, ALD, surface pre-treatment, metal gate, poly-SiGe,strained SiGe, surface-channel, buried-channel, notchedgate.</p>