Broadband wireless communication systems demand power-efficient analog-to-digital converters (ADCs) in the GHz and medium resolution regime. While high-speed architectures such as the flash and pipelined ADCs are capable of GHz operations, their high-power consumption reduces their attractiveness for mobile applications. On the other hand, the successive-approximation-register (SAR) ADC has an excellent power efficiency, but its slow speed has traditionally limited it to MHz applications. This dissertation puts forth several novel techniques to significantly increase the speed and power efficiency of the SAR architecture and demonstrates them in a low-power 10-GHz SAR ADC suitable for broadband wireless communications. The proposed 8-bit, 10-GHz, 8× time-interleaved SAR ADC utilizes a constant-matching DAC with symmetrically grouped unit finger capacitors to maximize speed by reducing the total DAC capacitance to 32 fF and minimizing the bottom plate parasitic capacitance. The capacitance reduction also saves power as both the DAC size and the driving logic size are reduced. An optimized asynchronous comparator loop and smaller driver logic push the single channel speed of the SAR ADC to 1.25 GHz, thus minimizing the total number of timeinterleaved channels to 8 to reach 10 GHz. A dual-path bootstrapped switch improves the spurious-free dynamic range (SFDR) of the sampling by creating an auxiliary path to drive the non-linear N-well capacitance apart from the main signal path. Using these techniques, the ADC achieves a measured signal-to-noise-and-distortion ratio (SNDR) and SFDR of 36.9 dB and 59 dB, respectively with a Nyquist input while consuming 21 mW of power. The ADC demonstrates a record-breaking figure-of-merit of 37 fJ/conv.-step, which is more than 2× better than the next best published design, among reported ADCs of similar speeds and resolutions.

Time-Interleaved Analog to Digital Converters (TI ADC) consist of several individual sub-converters operating at a lower sampling rate, working in parallel, and in a circular loop. Thereby, they are increasing the sampling rate without compromising on the resolution during conversion, at high sampling rates. The latter is the main requirement in the area of radio frequency sampling. However, they suffer from mismatches caused by the different characteristics in each sub-converter and the TI structure. The output of the TI ADC under consideration contains a lot of harmonics and spurious tones due to the non-linearities mismatch between the sub-converters. Therefore, previously extensive frequency planning was performed to avoid the input signal from coinciding with these harmonic bins. More importance has been given to digital calibration in recent years where algorithms are developed and implemented outside ADC in a Digital signal processor (DSP), whereas the compensation is done in real time. In this work, we model the distortions and the harmonics present in the TI ADC output to get a clear understanding of the TI ADC. A post-correction block is developed for the cancellation of the characterized harmonics. The suggested method is tested on the TI ADCs working at radio frequencies, but is valid also for other types of ADCs, such as pipeline ADCs and sigma-delta ADCs.

The work explores extending time interleaving in A/D converters, by applying a high-level of parallelism to one of the slowest and simplest types of data-converters, the counter ADC. The motivation for the work is to realise high-performance re-configurable A/D converters for use in multi-standard and multi-PHY communication receivers with signal bandwidths in the 10s to 100s of MHz. The counter ADC requires only a comparator, a ramp signal, and a digital counter, where the comparator compares the sampled input against all possible quantisation levels sequentially. This work explores arranging counter ADCs in large time-interleaved arrays, building a Time Interleaved Counter (TIC) ADC. The key to realising a TIC ADC is distributed sampling and a global multi-phase ramp generator realised with a novel figure-of-8 rotating resistor ring. Furthermore Counter ADCs allow for re-configurability between effective sampling rate and resolution due to their sequential comparison of reference levels in conversion. A prototype TIC ADC of 128-channels was fabricated and measured in 0.13μm CMOS technology, where the same block can be configured to operate as a 7-bit 1GS/s, 8-bit 500MS/s, or 9-bit 250MS/s dataconverter. The ADC achieves a sub 400fJ/step FOM in all modes of configuration.

Les convertisseurs analogique-numérique à entrelacement temporel (TIADC) semblent être une solution prometteuse dans le monde de la conversion analogique-numérique. Leur fréquence d’échantillonnage peut théoriquement être augmentée en augmentant le nombre de convertisseurs en parallèle. En réalité, des désappariements entre les convertisseurs peuvent fortement dégrader les performances, particulièrement à haute fréquence d’échantillonnage ou à haute résolution. Ces défauts d’appariement peuvent être réduits en utilisant des techniques de calibration en arrière-plan. La première partie de cette thèse est consacrée à l’étude des sources et effets des différents types de désappariements dans un TIADC. Des indicateurs de performance tels que le SNDR ou la SFDR sont exprimés en fonction du niveau des désappariements. Dans la deuxième partie, des nouvelles techniques de calibration sont proposées. Ces techniques permettent de réduire les effets des désappariements d’offset, de gain, d’instant d’échantillonnage et de bande passante. Les désappariements sont estimés en se basant sur des propriétés statistiques du signal et la reconstruction des échantillons de sortie se fait en utilisant des filtres numériques. La troisième partie démontre les performance d’un TIADC fonctionnant a une fréquence d’échantillonnage de 1.6 GE/s et comprenant les calibration d’offset, de gain et d’instant d’échantillonnage proposées. Les raies fréquentielles dues aux désappariements sont réduites à un niveau de -70dBc jusqu’à une fréquence d’entrée de 750 MHz. Ce circuit démontre une meilleure correction de désappariements que des circuits similaires récemment publiés, et ce avec une augmentation de puissance consommée et de surface relativement faible. / Time-interleaved analog-to-digital converters (TIADC) seem to be the holy grail of analog-to-digital conversion. Theoretically, their sampling speed can be increased, very simply, by duplicating the sub-converters. The real world is different because mismatches between the converters strongly reduce the TIADC performance, especially when trying to push forward the sampling speed, or the resolution of the converter. Using background digital mismatch calibration can alleviate this limitation. The first part of the thesis is dedicated to studying the sources and effects of mismatches in a TIADC. Performance metrics such as the SNDR and the SFDR are derived as a function of the mismatch levels. In the second part, new background digital mismatch calibration techniques are presented. They are able to reduce the offset, gain, skew and bandwidth mismatch errors. The mismatches are estimated by using the statistical properties of the input signal and digital filters are used to reconstruct the correct output samples. In the third part, a 1.6 GS/s TIADC circuit, implementing offset, gain and skew mismatch calibration, demonstrates a reduction of the mismatch spurs down to a level of -70 dBFS, up to an input frequency of 750 MHz. The circuit achieves the lowest level of mismatches among TIADCs in the same frequency range, with a reasonable power and area, in spite of the overhead caused by the calibration.

The growth of digital systems underscores the need to convert analog information to the digital domain at high speeds and with great accuracy. Analog-to-Digital Converter (ADC) calibration is often a limiting factor, requiring longer calibration times to achieve higher accuracy. The goal of this dissertation is to perform a fully digital background calibration using an arbitrary input signal for A/D converters. The work presented here adapts the cyclic "Split-ADC" calibration method to the time interleaved (TI) and successive approximation register (SAR) architectures. The TI architecture has three types of linear mismatch errors: offset, gain and aperture time delay. By correcting all three mismatch errors in the digital domain, each converter is capable of operating at the fastest speed allowed by the process technology. The total number of correction parameters required for calibration is dependent on the interleaving ratio, M. To adapt the "Split-ADC" method to a TI system, 2M+1 half-sized converters are required to estimate 3(2M+1) correction parameters. This thesis presents a 4:1 "Split-TI" converter that achieves full convergence in less than 400,000 samples. The SAR architecture employs a binary weight capacitor array to convert analog inputs into digital output codes. Mismatch in the capacitor weights results in non-linear distortion error. By adding redundant bits and dividing the array into individual unit capacitors, the "Split-SAR" method can estimate the mismatch and correct the digital output code. The results from this work show a reduction in the non-linear distortion with the ability to converge in less than 750,000 samples.

Les convertisseurs analogique-numérique à entrelacement temporel (TIADC) semblent être une solution prometteuse dans le monde de la conversion analogique-numérique. Leur fréquence d’échantillonnage peut théoriquement être augmentée en augmentant le nombre de convertisseurs en parallèle. En réalité, des désappariements entre les convertisseurs peuvent fortement dégrader les performances, particulièrement à haute fréquence d’échantillonnage ou à haute résolution. Ces défauts d’appariement peuvent être réduits en utilisant des techniques de calibration en arrière-plan. La première partie de cette thèse est consacrée à l’étude des sources et effets des différents types de désappariements dans un TIADC. Des indicateurs de performance tels que le SNDR ou la SFDR sont exprimés en fonction du niveau des désappariements. Dans la deuxième partie, des nouvelles techniques de calibration sont proposées. Ces techniques permettent de réduire les effets des désappariements d’offset, de gain, d’instant d’échantillonnage et de bande passante. Les désappariements sont estimés en se basant sur des propriétés statistiques du signal et la reconstruction des échantillons de sortie se fait en utilisant des filtres numériques. La troisième partie démontre les performance d’un TIADC fonctionnant a une fréquence d’échantillonnage de 1.6 GE/s et comprenant les calibration d’offset, de gain et d’instant d’échantillonnage proposées. Les raies fréquentielles dues aux désappariements sont réduites à un niveau de -70dBc jusqu’à une fréquence d’entrée de 750 MHz. Ce circuit démontre une meilleure correction de désappariements que des circuits similaires récemment publiés, et ce avec une augmentation de puissance consommée et de surface relativement faible. / Time-interleaved analog-to-digital converters (TIADC) seem to be the holy grail of analog-to-digital conversion. Theoretically, their sampling speed can be increased, very simply, by duplicating the sub-converters. The real world is different because mismatches between the converters strongly reduce the TIADC performance, especially when trying to push forward the sampling speed, or the resolution of the converter. Using background digital mismatch calibration can alleviate this limitation. The first part of the thesis is dedicated to studying the sources and effects of mismatches in a TIADC. Performance metrics such as the SNDR and the SFDR are derived as a function of the mismatch levels. In the second part, new background digital mismatch calibration techniques are presented. They are able to reduce the offset, gain, skew and bandwidth mismatch errors. The mismatches are estimated by using the statistical properties of the input signal and digital filters are used to reconstruct the correct output samples. In the third part, a 1.6 GS/s TIADC circuit, implementing offset, gain and skew mismatch calibration, demonstrates a reduction of the mismatch spurs down to a level of -70 dBFS, up to an input frequency of 750 MHz. The circuit achieves the lowest level of mismatches among TIADCs in the same frequency range, with a reasonable power and area, in spite of the overhead caused by the calibration.

The demand for efficient and reliable high rate communication is ever increasing. In this thesis we study different challenges in such systems, and their possible solutions. A goal for many years has been to implement as much as possible of a radio system in the digital domain, the ultimate goal being so called software defined radio (SDR) where the inner workings of a radio standard can be changed completely by changing the software. One important part of an SDR receiver is the high speed analog-to-digital converter (ADC) and one path to reach this high speed is to use a number of parallel, time-interleaved, ADCs. Such ADCs are, however, sensitive to sampling instant offsets, DC level offsets and gain offsets. This thesis discusses estimators based on fractional-delay filters and one application of these estimmators is to estimate and calibrate the relative delay, gain, and DC level offset between the ADCs comprising the time interleaved ADC. In this thesis we also present a technique for carrier frequency offset (CFO) estimation in orthogonal frequency division multiplexing (OFDM) systems. OFDM has gone from a promising digital radio transmission technique to become a mainstream technique used in several current and future standards. The main attractive property of OFDM is that it is inherently resilient to multipath reflections because of its long symbol time. However, this comes at the cost of a relatively high sensitivity to CFO. The proposed estimator is based on locating the spectral minimas within so-called null or virtual subcarriers embedded in the spectrum.~The spectral minimas are found iteratively over a number of symbols and is therefore mainly useful for frequency offset tracking or in systems where an estimate is not immediately required, such as in TV or radio broadcasting systems. However, complexity-wise the estimator is relatively easy to implement and it does not need any extra redundancy beside a nonmodulated subcarrier. The estimator performance is studied both in a channel with additive white Gaussian noise and in a multipath frequency selective channel environment. Interpolators and decimators are an important part of many systems, e.g. radio systems, audio systems etc. Such interpolation (decimation) is often performed using cascaded interpolators (decimators) to reduce the speed requirements in different parts of the system. In a fixed-point implementation, scaling is needed to maximize the use of the available word lengths and to prevent overflow. In the final part of the thesis, we present a method for scaling of multistage interpolators/decimators using multirate signal processing techniques. We also present a technique to estimate the output roundoff noise caused by the internal quantization.

This thesis strives to enhance the performance of delta-sigma modulators in two areas: increasing their speed and enabling their operation in a low voltage environment. Parallelism based on time-interleaving can be used to increase the speed of delta-sigma modulators. A novel single-path time-interleaved architecture is derived and analyzed. Finite opamp gain and bandwidth result in a mismatch between the noise transfer functions of the internal quantizers which degrades the performance of the new modulator. Two techniques are presented to mitigate the mismatch problem: a hybrid topology where the first stage uses multiple integrators while the rest of the modulator uses a single path of integrators and a digital calibration method. The input-feedforward technique removes the input-signal component from the internal nodes of delta-sigma modulators. The removal of the signal component reduces the signal swing and distortion requirements for the opamps. These characteristics enable the reliable implementation of delta-sigma modulators in modern CMOS technology. Two implementation issues for modulators with input-feedforward are considered. First, the drawback of the analog adder at the quantizer input is identified and the capacitive input feedforward technique is introduced to eliminate the adder. Second, the double sampled input technique is proposed to remove the critical path generate by the input feedforward path. Novel input-feedforward delta-sigma architecture is proposed. The new digital input feedforward (DIFF) modulator maintains the low swing and low distortion requirements of the input feedforward technique, it eliminates the analog adder at the quantizer input, and it improves the achievable resolution. To demonstrate these advantages, a configurable delta-sigma modulator which can operate as a feedback topology or in DIFF mode is implemented in 0.18μm CMOS technology. Both modulators operate at 20MHz clock with an oversampling ratio of 8. The power consumption in the DIFF mode is 22mW and in feedback mode is 19mW. However, the DIFF mode achieves a peak SNDR of 73.7dB (77.1dB peak SNR) while the feedback mode achieves a peak SNDR of 64.3dB (65.9dB peak SNR). Therefore, the energy required per conversion step for the DIFF architecture (2.2 pJ/step) is less than half of that required by the feedback architecture (5.7 pJ/step).

This thesis strives to enhance the performance of delta-sigma modulators in two areas: increasing their speed and enabling their operation in a low voltage environment. Parallelism based on time-interleaving can be used to increase the speed of delta-sigma modulators. A novel single-path time-interleaved architecture is derived and analyzed. Finite opamp gain and bandwidth result in a mismatch between the noise transfer functions of the internal quantizers which degrades the performance of the new modulator. Two techniques are presented to mitigate the mismatch problem: a hybrid topology where the first stage uses multiple integrators while the rest of the modulator uses a single path of integrators and a digital calibration method. The input-feedforward technique removes the input-signal component from the internal nodes of delta-sigma modulators. The removal of the signal component reduces the signal swing and distortion requirements for the opamps. These characteristics enable the reliable implementation of delta-sigma modulators in modern CMOS technology. Two implementation issues for modulators with input-feedforward are considered. First, the drawback of the analog adder at the quantizer input is identified and the capacitive input feedforward technique is introduced to eliminate the adder. Second, the double sampled input technique is proposed to remove the critical path generate by the input feedforward path. Novel input-feedforward delta-sigma architecture is proposed. The new digital input feedforward (DIFF) modulator maintains the low swing and low distortion requirements of the input feedforward technique, it eliminates the analog adder at the quantizer input, and it improves the achievable resolution. To demonstrate these advantages, a configurable delta-sigma modulator which can operate as a feedback topology or in DIFF mode is implemented in 0.18μm CMOS technology. Both modulators operate at 20MHz clock with an oversampling ratio of 8. The power consumption in the DIFF mode is 22mW and in feedback mode is 19mW. However, the DIFF mode achieves a peak SNDR of 73.7dB (77.1dB peak SNR) while the feedback mode achieves a peak SNDR of 64.3dB (65.9dB peak SNR). Therefore, the energy required per conversion step for the DIFF architecture (2.2 pJ/step) is less than half of that required by the feedback architecture (5.7 pJ/step).

Time-interleaved analog-to-digital converters are an attractive architecture for achieving a high speed, high resolution ADC in a power efficient manner. However, due to process and manufacturing variations, timing skews occur between the sampling clocks of the sub ADCs within the TI-ADC. These timing skews compromise the spurious free dynamic range of the converter. In addition, jitter on the sampling clocks, degrades the signal-to-noise ratio of the TI-ADC. Therefore, in order to maintain an acceptable spurious free dynamic range and signal to noise ratio, it is necessary to correct the timing skews while adding minimal jitter. Two analog-based architectures for correcting timing skews were investigated, with one being selected for implementation. The selected architecture and additional test circuitry were designed and fabricated in a 0.18??m CMOS process and tested using a 125 MSPS 16 bit ADC. The circuit achieves a correction precision on the order of 10???s of femtoseconds for timing skews as large as approximately 180 picoseconds, while adding less than 200 femtoseconds of rms jitter.