Les composants optoélectroniques sont de plus en plus utilisés dans les systèmes micro-ondes. Les liaisons par fibres optiques, permettent par exemple une réduction significative de la taille et de la masse des systèmes de distribution de signaux à bord des systèmes embarqués (avion, satellite, radar,&). Cependant, les performances de ces systèmes dépendent des performances des dispositifs utilisés pour les conversions électrique/optique et optique/électrique, de la technique de modulation optique choisie, des amplificateurs micro-ondes utilisés, de la qualité de la fibre optique et, finalement, de la topologie choisie pour réaliser le système entier. Ceci explique l'importance de développer une approche de modélisation efficace pour ces systèmes. Cette thèse nous a permis de développer une telle approche basée sur un logiciel de simulation de circuits hyperfréquences, comprenant différentes méthodes d'analyse des systèmes non-linéaires (dont la balance harmonique) et du bruit dans ces systèmes (conversion de bruit entre les harmoniques). L'originalité de ce travail consiste en l'utilisation de ce logiciel pour simuler des composants optoélectroniques, qui sont décrits par des équivalents électriques ou mathématiques. Grâce à cette étude, nous avons pu modéliser dans un premier temps une liaison optique utilisant un modulateur de Mach-Zehnder et incluant les différentes composantes de bruit du système. Un modèle est également proposé pour un discriminateur de fréquence micro-ondes à ligne à retard optique et enfin pour un discriminateur de fréquence optique. Sur la base de cette étude, un discriminateur de fréquence micro-onde utilisant une ligne à retard optique de plusieurs kilomètres a été conçu et réalisé. Ce système présente des performances en bruit de phase à l'état de l'art.

With rising fuel prices, increasing electrification, and imminent fines on CO2 emission within the EU, the requirement for energy and cost efficient supply concepts is becomingmore and more important in the automotive industry. This thesis presents an assessmentof, and improvement for energy and cost efficient power supply concepts for low-end automotiveand light e-mobility electronic control units, containing small µCs, and analogand logic components. Specifically, linear regulators, synchronous and non-synchronous buck converters, andswitched capacitor converters are investigated and assessed theoretically. The mostpromising concept, namely a discrete buck converter, is further studied using theoreticalassessment, experiment, and simulations. The key result of this work is a concept for replacing commonly used linear regulatorsin small electronic control units (ECUs) by a more efficient supply with only a smallcost adder. Specifically, since no low-end switched converter ICs are available today, wedeveloped a buck converter with discrete control circuit. This concept provides a cheap,yet efficient alternative to linear regulators for a wide range of applications. In addition,the application of this concept is supported by component selection criteria, and also bythe developed simulation models.

Este trabalho apresenta o estudo comparativo do desempenho de três topologias de conversores do sistema monofásico para o sistema trifásico com número reduzido de componentes, para o acionamento de um motor de indução do tipo rotor gaiola de esquilo. O funcionamento de cada topologia é descrito e simulado digitalmente. O desempenho desses conversores é avaliado em diferentes modos de operação, com sequência de fase positiva ou negativa, com ênfase na qualidade de energia em termos de redução da distorção harmônica total e da melhoria do fator de potência na fonte. Com vistas à redução de custos, foi desenvolvido um protótipo experimental baseado no uso de módulo integrado de chaves semicondutoras de potência e de um microcontrolador de baixo custo. Os resultados experimentais se equiparam aos resultados obtidos por simulação. / This work presents the comparative performance of three topologies of single-phase to three-phase converters with reduced number of components while driving an induction motor of type squirrel-cage. The operation of each topology is described by means of simulation results. The performance of these converters is evaluated in different modes of operation, according to the positive or negative sequence, with an emphasis on power quality in terms of reduced total harmonic distortion and improved power factor at the input source. With a viewpoint for achieving reduced costs, an experimental prototype has been developed, based on the use of integrated module of power semiconductor switches and a cheap microcontroller. Experimental results comparable to those obtained by simulations are obtained.

Les réseaux de capteurs sans fils linéaires (RdCSL) sont un cas particulier de réseaux de capteurs sans fils où les nœuds de capteurs sont déployés le long de multiples lignes. les RdCSL sont utilisés pour la surveillance des infrastructures routières, ferroviaires, des conduites de gaz, d’eau, de pétrole et de cours d’eau. Les solutions classiques de formation de topologie et d’adressage proposées ne sont pas adaptées à l’environnement des RdCSFL. En effet les paramètres initiaux utilisés par ces protocoles tels que le nombre maximum de nœuds fils (Cm), nombre maximum de nœuds routeurs fils Rm, profondeur maximum de l’arbre (Lm), occasionnent un gaspillage de l’espace d’adressage disponible pour les nœuds et limitent la profondeur de l’arbre adressable (15 sauts pour ZigBee). D’autres solutions adaptées pour les RdCSFL utilisent une organisation en cluster des nœuds du réseau et sont basées elles aussi sur des paramètres fixés à l’avance tels quel le nombre maximum de cluster fils par cluster. De plus, ces solutions requièrent beaucoup d’interventions manuelles sur les nœuds de capteurs (choix des chefs de cluster par exemple) et ne favorisent pas une adaptation face aux changements du RdCSL tels que l’ajout d’un ensemble de nœuds de capteurs. Dans cette thèse, nous proposons donc des protocoles permettant la construction automatique de topologies logiques, l’adressage et le routage pour des réseaux de capteurs sans fil linéaires. Nos protocoles fournissent aussi des mécanismes de gestion dynamique d’un RdSFL avec l’ajout de nouveaux nœuds, la réallocation d’adresses pour les nœuds en cas d’épuisement de blocs d’adresses et la gestion du routage vers plusieurs puits du réseau. Nos différents protocoles sont évalués grâce au simulateur Castalia/Omnet++. Les résultats de nos simulations montrent que nos protocoles permettent de construire un RdCSFL connecté avec peu de nœuds orphelins (nœuds sans adresses logiques) et sans limitations de profondeur. Nous montrons aussi, grâce à nos simulations, que nos contributions permettent d’ajouter un grand nombres de nœuds à un RdCSFL existant de n’importe quelle taille et s’adaptent au déploiement de plusieurs puits et au routage multi-puits et permettent d’améliorer le ratio et la latence de paquets livrés dans les RdCSFL. / Linear wireless sensor network (LWSN) are a sub-case of wireless sensor network where sensor nodes are roughly deployed through multiple long lines with branches. LWSN are used to monitor infrastructures such as roads, pipelines, and naturals entities such as rivers.Classical solutions of topology construction and addressing are inefficient on LWSN . Indeed, with initials networks parameters such as the maximum number of children per node (Cm), the maximum number of children routers per node (Rm), and the maximum tree depth, a solution like ZigBee causes a waste of available address space of network nodes and limit the depth of the addressable tree to 15 hops. Other solutions proposed for LWSN use a cluster-tree organisation and are based on initial network parameters such as the maximum number of children clusters per cluster. In addition, these solutions require a lot of manual intervention on different sensor nodes and do not allow adaptation for a network extension (addition of a set of new sensor nodes). In this thesis, we propose protocols to allow the automatic construction of topologies, the addressing and the data routing for linear wireless sensor networks. Our contribution also provides mechanisms for dynamic management of LWSN (addition of new nodes, addresses reallocation, and data routing to multiple sink nodes). Our different protocols are evaluated using Castalia/Omnet++ simulator. Results of our simulations show that our protocols allow a construction of connected LWSN with very few orphan nodes and without depth limitations. We also show that our contribution allows to add many new nodes on different LWSN, and adapts to the deployment of multiple sinks to improve the ratio and the latency of data delivery packets.

Este trabalho apresenta o estudo comparativo do desempenho de três topologias de conversores do sistema monofásico para o sistema trifásico com número reduzido de componentes, para o acionamento de um motor de indução do tipo rotor gaiola de esquilo. O funcionamento de cada topologia é descrito e simulado digitalmente. O desempenho desses conversores é avaliado em diferentes modos de operação, com sequência de fase positiva ou negativa, com ênfase na qualidade de energia em termos de redução da distorção harmônica total e da melhoria do fator de potência na fonte. Com vistas à redução de custos, foi desenvolvido um protótipo experimental baseado no uso de módulo integrado de chaves semicondutoras de potência e de um microcontrolador de baixo custo. Os resultados experimentais se equiparam aos resultados obtidos por simulação. / This work presents the comparative performance of three topologies of single-phase to three-phase converters with reduced number of components while driving an induction motor of type squirrel-cage. The operation of each topology is described by means of simulation results. The performance of these converters is evaluated in different modes of operation, according to the positive or negative sequence, with an emphasis on power quality in terms of reduced total harmonic distortion and improved power factor at the input source. With a viewpoint for achieving reduced costs, an experimental prototype has been developed, based on the use of integrated module of power semiconductor switches and a cheap microcontroller. Experimental results comparable to those obtained by simulations are obtained.

Multilevel voltage source inverters have been receiving more and more attention from the industry and academia as a choice for high voltage and high power applications. The high voltage multilevel inverters can be constructed with existing low voltage semiconductor switches, which already have a mature technology for handling low voltages, thus improving the reliability of the overall inverter system. These multilevel inverters generate the output voltage in the form of multi-stepped waveform with smaller amplitude. This will result in less dv/dt at the motor inputs and electromagnetic interference (EMI) caused by switching is considerably less. Because of the multi-stepped waveform, the instantaneous error in the output voltage will be always less compared to the conventional two-level inverter output voltage. It will reduce the unwanted harmonic content in the output voltage, which will enable to switch the inverter at lower frequencies. Many interesting multi level inverter topologies are proposed by various research groups across the world from industry and academic institutions. But apart from the conventional 3-level NPC and H-bridge topology, others are not yet highly preferred for general high power drives applications. In this respect, two different five-level inverter topologies and one three-level inverter topology for high power induction motor drive applications are proposed in this work. Existing knowledge from published literature shows that, the three-level voltage space vector diagram can be generated for an open-end winding induction motor by feeding the motor phase windings with two two-level inverters from both sides. In such a configuration, each inverter is capable of assuming 8 switching states independent of the other. Therefore a total of 64 switching combinations are possible, whereas the conventional NPC inverter have 27 possible switching combinations. The main drawback for this configuration is that, it requires a harmonic filter or isolated voltage source to suppress the common mode currents through the motor phase winding. In general, the harmonic filters are not desirable because, it is expensive and bulky in nature. Some topologies have been presented, in the past, to suppress the common mode voltage on the motor phase windings when the both inverters are fed with a single voltage source. But these schemes under utilize the dc-link voltage or use the extra power circuit. The scheme presented in chapter-3 eliminates the requirement of harmonic filter or isolated voltage source to block the common mode current in the motor phase windings. Both the two-level inverters, in this scheme, are fed with the same voltage source with a magnitude of Vdc/2 where Vdc is the voltage magnitude requires for the NPC three-level inverter. In this scheme, the identical voltage profile winding coils (pole pair winding coils), in the four pole induction motor, are disconnected electrically and reconnected in two star groups. The isolated neutrals, provided by the two star groups, will not allow the triplen currents to flow in the motor phase windings. To apply identical fundamental voltage on disconnected pole pair winding, decoupled space vector PWM is used. This PWM technique eliminates the first center band harmonics thereby it will allow the inverters to operate at lower switching frequency. This scheme doesn’t require any additional power circuit to block the triplen currents and also it will not underutilize the dc-bus voltage. A five-level inverter topology for four pole induction motor is presented in chapter-3. In this topology, the disconnected pole pair winding coils are effectively utilized to generate a five-level voltage space vector diagram for a four pole induction motor. The disconnected pole pair winding coils are fed from both sides with conventional two-level inverters. Thereby the problems like capacitor voltage balancing issues are completely eliminated. Three isolated voltage sources, with a voltage magnitude of Vdc/4, are used to block the triplen current in the motor phase windings. This scheme is also capable of generating 61 space vector locations similar to conventional NPC five-level inverter. However, this scheme has 1000 switching combinations to realize 61 space vector locations whereas the NPC five-level inverter has 125 switching combinations. In case of any switch failure, using the switching state redundancy, the proposed topology can be operated as a three-level inverter in lower modulation index. But this topology requires six additional bi-directional switches with a maximum voltage blocking capacity of Vdc/8. However, it doesn’t require any complicated control algorithm to generate the gating pulses for bidirectional switches. The above presented two schemes don’t require any special design modification for the induction machine. Although the schemes are presented for four pole induction motor, this technique can be easily extend to the induction motor with more than four poles and thereby the number of voltage levels on the phase winding can be further increased. An alternate five-level inverter topology for an open-end winding induction motor is presented in chapter-4. This topology doesn’t require to disconnect the pole pair winding coils like in the previous propositions. The open-end winding induction motor is fed from one end with a two-level inverter in series with a capacitor fed H-bridge cell, while the other end is connected to a conventional two-level inverter to get a five voltage levels on the motor phase windings. This scheme is also capable of generating a voltage space vector diagram identical to that of a conventional five-level inverter. A total of 2744 switching combinations are possible to generate the 61 space vector locations. With such huge number switching state redundancies, it is possible to balance the H-bridge capacitor voltage for full modulation range. In addition to that, the proposed topology eliminates eighteen clamping diode having different voltage ratings compared to the NPC inverter. The proposed topology can be operated as a three-level inverter for full modulation range, in case of any switch failure in the capacitor fed H-bridge cell. All the proposed topologies are experimentally verified on a 5 h.p. four pole induction motor using V/f control. The PWM signals for the inverters are generated using the TMS320F2812 and GAL22V10B/SPARTAN XC3S200 FPGA platforms. Though the proposed inverter topologies are suggested for high-voltage and high-power industrial IM drive applications, due to laboratory constraints the experimental results are taken on the 5h.p prototypes. But all the proposed schemes are general in nature and can be easily implemented for high-voltage high-power drive applications with appropriate device ratings.

This dissertation aims at designing a three-phase voltage source inverter based on the SiC devices and mainly the SiC-MOSFET. The designed inverter offers a possibility to drive the power inverter with a very high efficiency, which can reach up to 99% for 16 kW rated power. The design is dedicated to the electric vehicle application, and it aims at • Providing a comparative study on some of the current discrete SiC devices in terms of the total losses and the thermal conductivity. In addition, a behavioral study of the effective channel mobility with temperature variation in the SiC MOSFET will be investigated. • Designing a gate driver which fits with the driving requirements of the SiC-MOSFET and provides a trade-off between the switching losses and the EMI behavior. • Designing a three-phase voltage source inverter with 16 kW rated power; the design includes minimizing the inverter losses and extracts the EMI model of the power inverter by considering the effects of the parasitic parameters; moreover a short guideline for selecting the heat-sink based on the static network is introduced. • Proposing a new and simplified carried-based PWM, this will reduce the harmonics in the output waveforms and enhance the utilization of the DC-link voltage. • Proposing a new strategy for compensating the dead-time effect in carrier based-PWM and to find out the proper dead-time level in VSI based on SiC –MOSFET. • Designing faults diagnosis and protection circuits in order to protect the power inverter from the common faults; overcurrent, short-circuit, overvoltage, and overtemperature faults.

While it is important for systems intended to enhance musical creativity to define and explore musical ideas conceived by individual users, many limit musical freedom by focusing on maintaining musical structure, thereby impeding the user's freedom to explore his or her individual style. This dissertation presents a comprehensive body of work that introduces a new musical representation that allows users to explore a space of musical rules that are created from their own melodies. This representation, called functional scaffolding for musical composition (FSMC), exploits a simple yet powerful property of multipart compositions: The pattern of notes and rhythms in different instrumental parts of the same song are functionally related. That is, in principle, one part can be expressed as a function of another. Music in FSMC is represented accordingly as a functional relationship between an existing human composition, or scaffold, and an additional generated voice. This relationship is encoded by a type of artificial neural network called a compositional pattern producing network (CPPN). A human user without any musical expertise can then explore how these additional generated voices should relate to the scaffold through an interactive evolutionary process akin to animal breeding. The utility of this insight is validated by two implementations of FSMC called NEAT Drummer and MaestroGenesis, that respectively help users tailor drum patterns and complete multipart arrangements from as little as a single original monophonic track. The five major contributions of this work address the overarching hypothesis in this dissertation that functional relationships alone, rather than specialized music theory, are sufficient for generating plausible additional voices. First, to validate FSMC and determine whether plausible generated voices result from the human-composed scaffold or intrinsic properties of the CPPN, drum patterns are created with NEAT Drummer to accompany several different polyphonic pieces. Extending the FSMC approach to generate pitched voices, the second contribution reinforces the importance of functional transformations through quality assessments that indicate that some partially FSMC-generated pieces are indistinguishable from those that are fully human. While the third contribution focuses on constructing and exploring a space of plausible voices with MaestroGenesis, the fourth presents results from a two-year study where students discuss their creative experience with the program. Finally, the fifth contribution is a plugin for MaestroGenesis called MaestroGenesis Voice (MG-V) that provides users a more natural way to incorporate MaestroGenesis in their creative endeavors by allowing scaffold creation through the human voice. Together, the chapters in this dissertation constitute a comprehensive approach to assisted music generation, enabling creativity without the need for musical expertise.

Les structures de conversion multiniveaux permettent de convertir en moyenne tension et forte puissance. Celles-ci sont construites à partir de cellules de commutations et permettent d’augmenter le courant et la tension en entrée ou en sortie. Ces structures sont appelées multiniveaux car les formes d’ondes des tensions en sortie permettent d’avoir plus de deux niveaux de tension différents. Les différentes structures peuvent être classées dans différentes catégories tel que la mise en série de pont en H, les convertisseurs multicellulaires série ou parallèle ou encore les structures utilisant le fractionnement du bus continu. Toutes ces structures ont des propriétés et applications différentes, même si certaines structures ont des propriétés communes. Il est aussi possible de créer de nouvelles structures en mixant les différentes structures de bases des différentes familles de convertisseurs multiniveaux ou en assemblant les structures de base de la conversion statique. Même si l’utilisation de structure de conversion multiniveaux permet de convertir à forte puissance, celle-ci n’est pas toujours aisée. En effet l’augmentation du nombre de niveaux ou de la tension d’entrée implique également une augmentation du nombre de composants semiconducteurs. Ceci peut être un frein à l’utilisation de convertisseur multiniveaux. Pour cela une nouvelle structure utilisant des composants partagés entre les différentes phases est proposée afin de limiter leur nombre. Un autre problème important lié aux convertisseurs multiniveaux est l’équilibrage des tensions des condensateurs du bus continu si celui-ci est composé de plus de deux condensateurs mis en série. Pour cela plusieurs solutions sont possibles : soit en utilisant une commande spécifique utilisant la modulation vectorielle, soit en utilisant des structures auxiliaires qui ont pour but d’équilibrer les différentes tensions des condensateurs. Dans une dernière partie ont été proposées de nouvelles structures qui permettent à la fois d’augmenter le courant de sortie et la tension en entrée en utilisant les principes des structures de base des convertisseurs multicellulaires série et parallèle. De plus, ces structures ont des propriétés intéressantes sur les formes d’ondes de sortie. De ces structures a été conçu un prototype permettant de valider les résultats de simulation. Une commande numérique implantée sur FPGA a été réalisée et a permis d’avoir des résultats expérimentaux intéressants. / This PhD Thesis deals with the study of new multilevel structures. At the beginning of this work, a new methodology to create new multilevel structures has been conceived. To evaluate the performances of these structures, there are many possibilities: number of output voltage levels, number of components, and the quality of the converters’ output waveforms. The list of criteria is not exhaustive. One technique to obtain an output multilevel waveform is to split the DC link in several capacitors. There is a limitation since putting more than two capacitors in serial connection leads to an unbalancing of these voltage capacitors. Several solutions are possible to balance these voltages. The first one uses the control of the structure in a three phase application, using a space vector modulation and minimizing the energy stored in the DC link. The second solution consists in using auxiliary circuits, which realize an energy transfer between one capacitor to another through an inductor. The drawback of this method is the high number of components. This problem can be reduced sharing some components between the three phases of the converter. The third part of this study is related to multicell converters, structures with very interesting good properties. New converter structures mix serial and parallel multicell converters, to obtain a hybrid converter with similar performances to the two basic converters. An experimental prototype was built to validate the results of the PhD. The digital control of this hybrid structure was made with a FPGA where two DSP processors were implemented.

Lorsqu'un boson Z de haute impulsion se désintègre en paire e+e-, l'électron et le positron laissent des traces très rapprochées l'une de l'autre, ce qui rend la reconstruction de ce processus peu efficace. L'identification de signature leptoniques d'évènements massifs issus de théories telles l'extension du groupe de jauge électrofaible SU(2)_1 x SU(2)_2 x U(1) pour ajouter des bosons massifs W' et Z' se couplant directement aux bosons vectoriels et aux fermions du modèle standard est important dans l'optique de recherche de nouvelle physique puisque les états finaux leptoniques fournissent le canal de détection de plus pur. Ici, un outil d'identification des paires d'électron-positron issues de bosons Z à haute impulsion basé uniquement sur les variables décrivant les jets est développé en se basant sur des simulations d'évènements massifs produits dans le détecteur ATLAS du LHC au CERN. Une étude topologique des évènements candidats est portée dans un ensemble d'échantillons Monte Carlo. Une série de coupures rectangulaires est optimisée sur un échantillon de bosons Z produits avec une haute impulsion. L'efficacité de reconstruction des paires d'électron-positron est maximisée. Cinq sources de bruit de fonds ont été soumises aux critères de sélection pour l'étude de la suppression du bruit de fonds. Finalement l'outil développé est comparé à l'identification de paires d'électron-positron basé sur la reconstruction usuelle d'objets leptoniques au LHC. Cette comparaison met en évidence le gain significatif de l'outil développé, atteignant une efficacité de reconstruction de 93% dans des échantillons Monte Carlo à haute énergie, avec un bruit de fond négligeable. / When a Z boson with high transverse momentum desintegrates into an e+e- pair, the electron and the positron leave nearly superimposed tracks which makes the detection process very difficult. The identification of massive events arising from theories like the extension of the electroweak gauge group SU(2)_1 x SU(2)_2 x U(1) leading to the existence of massive W' and Z' bosons coupling directly to standard model vector bosons and fermions is more readily performed through leptonic channel. Here, a series of rectangular cuts comprising a purely jet substructure based electron positron pair arising from the decay of a Z boson identification in boosted topologies (p_T(Z)>1TeV) is presented. The selection process of the cuts is done through a topology study of candidate events in various Monte Carlo simulation samples. The reconstruction efficiency of the electron-positron pairs is maximised. Five background sources were tested against the selection criteria to study the background rejection efficiency of the methodology. Finally, it is found that the reconstruction tool developped nearly triples electron positron identification, reaching 93% efficiency in high energy Monte Carlo samples, with insignificant background noise.