Let G be a subset of the dual of a real Banach space X and F ⊂ G. Then F is a James boundary of G if each w∗ -continuous linear functional on X attains its supremum over G on an element of the set F. We ask whether a norm bounded subset of X which is countably compact for the topology generated by F is ne- cessary sequentially compact for the topology generated by G. The main content of our work is a positive solution to this problem. As a corollary we obtain James characterization of weakly compact subsets of a real Banach space. Due to the Eberlein-Šmuljan theorem a positive solution to the so called boundary problem is shown as a special case of the affirmative answer to the question raised above. The question is further discussed for a case of Banach spaces defined over the complex field. In this case we cannot use the old definition of the James boun- dary but by a "natural" way it is possible to redefine the term James boundary and then we are able to answer our question positively again. 1

Το ερευνητικό αντικείμενο και ο στόχος της διδακτορικής διατριβής είναι η πρόταση μιας ολοκληρωμένης λύσης για την υποστήριξη τηλεπικοινωνιακών εφαρμογών σε ασύρματα δίκτυα τα οποία δεν στηρίζονται σε σταθερές δικτυακές υποδομές. Ένα τέτοιο δίκτυο, το οποίο αναφέρεται στη διεθνή βιβλιογραφία ως Mobile Ad-hoc Network (MANET), είναι ένα αυτο-οργανώσιμο αυτο-σχηματιζόμενο ασύρματο δίκτυο με διαδρομές πολλαπλών τμημάτων (multi-hop), όπου η δομή του δικτύου αλλάζει δυναμικά λόγω της κινητικότητας των κόμβων ή αλλαγές στην τοπολογία. Η αρχιτεκτονική που προτείνεται για την ικανοποίηση των τιθέμενων απαιτήσεων στηρίζεται στην ανάπτυξη ενός ολοκληρωμένου επικοινωνιακού αρχιτεκτονικού πλαισίου για MANET δίκτυα το οποίο περιλαμβάνει μηχανισμούς μείωσης της κατανάλωσης ενέργειας που οφείλεται σε επικοινωνιακές λειτουργίες, την ανάπτυξη ενός εξειδικευμένου πρωτοκόλλου δρομολόγησης, τροποποιήσεις του πρωτοκόλλου TCP στο επίπεδο μεταφοράς και την υλοποίηση ενός νέου πρωτόκολλου διαχείρισης δικτύου. Η απόδοση της προτεινόμενης επικοινωνιακής διαστρωμάτωσης είναι υψηλή σε περιβάλλον με μεγάλη κινητικότητα των κόμβων και δυναμική αλλαγή της τοπολογίας ενώ παράλληλα η κατανάλωση ενέργειας των κόμβων παραμένει σχετικά χαμηλή. Οι αλγόριθμοι και τα πρωτοκόλλα που παρουσιάζονται σχεδιάστηκαν και υλοποιήθηκαν λαμβάνοντας υπόψη τους περιορισμούς και τις απαιτήσεις ενός ενσωματωμένου συστήματος, ενώ η απόδοση και αξιοπιστία τους τεκμηριώνονται θεωρητικά και με εξομοιώσεις. / The research objective of this thesis is a complete solution so as to support the implementation of telecommunication applications in wireless networks that operate without the presence of fixed infrastructure. Such a network, cited as Mobile Ad-hoc Network (MANET) in international literature, is a self-organized, auto-configured wireless network with multi-hop routing paths where its structure is modified dynamically due to node mobility and topological changes. In order to meet the above requirements a new communication framework for MANET networks is presented, which consists of the adaptation of communication-related energy reduction techniques, development of a specialized routing protocol at the network layer, modifications of the TCP protocol at the transport layer and the implementation of a novel network management protocol. The performance of the proposed protocol stack is satisfactory in dynamic network topologies with increased node mobility, whereas the node energy consumption remains in low levels. The presented algorithms and protocols are designed and implemented considering the constraints and requirements of an embedded system, while their performance and reliability is proved theoretically and by simulation results.

Renewable energy sources normally require power converters to convert their energy into standardized regulated ac output. The motivation for this thesis is to design and control power converters for renewable energy systems to ensure very good power quality, efficiency and reliability. The renewable energy sources considered are low voltage dc sources such as photovoltaic (PV) modules. Two transformer-isolated power circuit topologies with input voltage of less than 50V are designed and developed for low and medium power applications. Various design and control issues of these converters are identified and new solutions are proposed. For low power rating of a few hundred watts, a line-frequency transformer interfaced inverter is developed. In the grid connected operation, it is observed that this topology injects considerable lower order odd and even harmonics in the grid current. The reasons for this are identified. A new current control method using adaptive harmonic compensation technique and a proportional-resonant-integral (PRI) controller is proposed. The proposed current controller is designed to ensure that the grid current harmonics are within the limits set by the IEEE 1547-2003 standard. Phase-locked loops (PLLs) are used for grid synchronization of power converters in grid-tied operation and for closed-loop control reference generation. Analysis and design of synchronous reference frame PLL (SRF-PLL) and second-order generalized integrator (SOGI) based PLLs considering unit vector distortion under the possible non-ideal grid conditions of harmonics, unbalance, dc offsets and frequency deviations are proposed and validated. Both SRF-PLL and SOGI-PLL are low-complexity PLLs. The proposed designs achieve fastest settling time for these PLLs for a given worst-case input condition. The harmonic distortion and dc offsets in the resulting unit vectors are limited to be well within the limits set by the IEEE 1547-2003 standard. The proposed designs can be used to achieve very good performance using conventional low-complexity PLLs without the requirement of advanced PLLs which can be computationally intensive. A high-frequency (HF) transformer interfaced ac link inverter with a lossless snubber is developed medium power level in the order of few kilowatts. The HF transformer makes the topology compact and economical compared to an equally rated line frequency transformer. A new synchronized modulation method is proposed to suppress the possible over-voltages due to current commutation in the leakage inductance of the HF transformer. The effect of circuit non-ideality of turn-on delay time is analyzed. The proposed modulation mitigates the problem of spurious turn-on that can occur due to the turn-on delay time. The HF inverter, rectifier and snubber devices have soft switching with this modulation. A new reliable start-up method is proposed for this inverter topology without any additional start- up circuitry. This solves the problems of over-voltages and inrush currents during start-up. The overall research work reported in the thesis shows that it is possible to have compact, reliable and high performance power converters for renewable energy conversion systems. It is also shown that high control performance and power quality can be achieved using the proposed control techniques of low implementation complexity.

MU LT I L E V E L inverters are becoming the preferred choice for medium voltage high power applications. Multilevel inverters have a number of inherent advantages over conventional two level inverters. The output voltage has multiple steps or levels, resulting in reduced dV/dt, which leads to lower electromagnetic interference, making it easier to meet electromagnetic compatibility (EMC) regulations. Multilevel inverters have a much lower effective switching frequency, which leads to a reduction in switching losses. The output voltage of multilevel inverters has a much lower harmonic content. In applications such as power conversion or grid-connection, filters need to be much smaller, or can be eliminated. In motor drive applications, the low harmonic content results in smoother, ripple-free shaft torque. The neutral-point clamped (NPC), cascaded H-bridge (CHB) and flying capacitor (FC) topologies were among the earliest multilevel topologies. NPC topologies require additional clamping diodes to clamp the output to the DC bus midpoint. CHB topologies use a number of isolated DC suplies to generate multilevel output. FC topologies work with a single DC link but use additional floating capacitors. Since then, a number derivatives and improvements to these topologies have been proposed. Topologies with low switch counts are desirable because of the corresponding reduction in system size and cost. A low total component count is also desirable since it results in better reliability. Induction motors in high power applications are often operated in the open-end configuration. Here, the start terminals of the motor phase windings are connected to one three phase inverter, while the end terminals are connected to a second three-phase inverter. The two inverters are typically powered by isolated supplies to prevent the flow of common mode currents through the motor. The open end configuration has a number of advantages It can be used with nearly all high power motors with no need for electrical or mechanical modification, since all six winding terminal are available externally. The two inverters driving the open-end motor are effectively cascaded. As a result, two inverters of lower voltage and power rating can replace a single inverter with higher voltage and power rating. In addition, if one of the inverter fails, it can be bypassed and the system can be operated at reduced power. In many applications such as heating, ventilation and air conditioning (HVAC), the load power is proportional to the cube of the shaft speed, so a 50% reduction in power translates to only 20% reduction in speed, thereby improving overall system reliability. The cascading of inverters also enables multilevel operation, which is exploited for the topologies proposed in this thesis. In the open-end configuration it is important to ensure that both the DC supplies deliver power to the load. Otherwise, power can circulate through the motor windings. In addition, if the two inverters are powered by rectifier supplies, the DC bus of one inverter can charge uncontrollably, resulting in distortion of phase voltages and currents. If DC bus overcharging continues unchecked the DC bus voltage can even exceed the system rating, resulting in permanent damage. This thesis proposes two novel topologies for open-end induction motor drives with low switch counts. Both topologies are powered by two unequal, isolated DC sources having DC voltages in a 3:1 ratio. Multiple levels in the output voltage are obtained using a number of floating capacitors in each phase. Modulation and control schemes are also proposed for both topologies to ensure that DC bus overcharging never occurs, while all the capacitor voltages are kept balanced at their nominal values. The first of these two topologies is a nine level inverter for open end induction motor drives. It consists of two three-level flying capacitor inverters connected to the induction motor in the open end configuration. The two inverters are powered by DC sources of voltage 6VDC/8 and 2VDC/8, which generates an effective phase voltage having nine levels in steps of VDC/8. This topology has only eight switches and two floating capacitors per phase. The space vector structure for this topology is hexagonal, and has 217 space vector locations. A space-vector based formulation is used to determine the pole voltage of the inverter such that DC bus over charging is prevented. In addition, selection of switching states is used to balance the voltages of all floating capacitors. This scheme allows the floating capacitors to be charged up during system startup, thereby eliminating the need for separate pre-charging circuitry. A level-shifted carrier PWM based modulation scheme has been developed, which can be used with both scalar and vector control schemes. The gating signal for switches turning on must be delayed by a small amount (to allow the complementary switch to turn of), failing which current shoot through can occur. This delay is called dead time, during which gate signals to both complementary devices are turned of. Under certain conditions in the flying capacitor topology, the pole voltage can contain large undesirable transients during the dead time which result in phase current distortion, and electromagnetic noise. A novel scheme to eliminate this problem is proposed using a digital state machine approach. The switching state for each subsequent switching interval is determined based on the present switching state such that the pole voltage does not contain a transient, without affecting the phase voltage of the inverter, and irrespective of the current magnitude or direction. The state machine was implemented using an FPGA, and required an additional computation time of just 20ns, which is much smaller than the inverter dead time duration of typically 2.5µs. The second novel topology proposed in this thesis is a seventeen level inverter for an open end induction motor drive. Here, one three-level inverter and one seven-level inverter are connected to the two ends of the induction machine. The three-level inverter is a flying capacitor inverter. The seven-level inverter is a hybrid topology – it consists of an H-bridge cascaded to each phase of a three level flying capacitor inverter. This scheme is also powered by two isolated DC sources in 3:1 ratio with magnitudes 12VDC/16 and 4VDC/16. The effective phase voltage has seventeen levels in steps of VDC/16. This topology has a total of twelve switches and three floating capacitors per phase. The space vector structure for this topology is hexagonal, and has 817 space-vector locations. Space vector analysis was used to determine the pole voltages, and the switching states such that DC bus overcharging is prevented while also balancing the voltages of the floating capacitors. A non-iterative algorithm was developed for determining the switching states, suitable for implementation in digital logic using an FPGA. The scheme is able to charge the all capacitors at startup as well, eliminating the need for separate pre-charging circuits. Hardware prototypes were built for both the topologies described above for experimental verification, and used to drive a three phase 50Hz, 1.5kW, four pole induction motor in V/f control mode. The inverters topologies were built using 1200V, 75A IGBT half-bridge modules (Semikron SKM75GB12T4) with hybrid opto-isolated gate drivers (Mitsubishi M57962). Three phase rectifiers were used to create the asymmetric DC supplies Hall effect sensors were used to sense the DC link and floating capacitor voltages and phase currents (LEM LV20P voltage sensors and LA55 current sensors). Signal conditioning circuitry was built using discrete components. The PWM signals and V/f controller were implemented using a digital signal processor (Texas Instruments TMS320F28335). Synchronous PWM with was used to eliminate sub-harmonics from the phase voltage, and to ensure three-phase and half-wave symmetry. The internal ADC of the DSP was used for sampling all voltages and currents. The remaining digital logic for switch state selection was implemented on a FPGA (Xilinx Spartan3 XC3S200). Dead time functionality was also implemented within the FPGA, eliminating the need for separate dead time hardware. Both topologies were first tested for steady state operation over the full modulation range, and the pole voltages, phase voltages and phase currents were recorded. System startup, and the ability of the controllers to balance all the capacitors at startup was tested next. The capacitor voltages were also observed during sudden loading, by quickly accelerating the motor. Finally, the phenomenon of DC bus overcharging was also demonstrated. These results demonstrate the suitability of the proposed topology for a number of applications, including industrial drives, alternate energy systems, power conversion and electric traction.

I detta examinationsarbetesrapport för högskoleingenjörsexamen inom Elektronik, presenteras en utredning för att svara på vad som skulle vara den mest generiska pulsgeneratorn för ultraljudstestning inom det klassiska intervallet 0.5 till 15 MHz. Det presenteras flera variabler i teorin, som påverkar en testsignal och varför det inte går att beräkna vad en generisk pulsgenerator bör åstadkomma. Denna rapport presenterar vilka pulsgeneratorer det finns och vad de mer högpresterande pulsgeneratorerna beskrivna i vetenskapliga forskningsresultat har presterat. Samt vilka tekniker som finns och varför vissa tekniker inte är lämpliga. Vid slutet av denna examinationsarbetesrapport presenteras, med hjälp av några antaganden om vad en generisk pulsgenerator behöver prestera, dras en slutsats om vilken av de föreslagna pulsgeneratorerna som är mest generisk. / This bachelor thesis, is a trial in answering what would be a generic pulse generator for ultrasonic testing in the classic test range of 0.5 to 15 MHz. It also goes through multiple variables that affects a test signal and why it really isn't possible to precalculate what a generical pulse generators should achive, in the theory chapter. This thesis also goes through what different types of pulse generators there is and what some of the more high performance pulse generators proposed in scientific articles have achieved and what techniques that have been used and why some techniques are not suitable. In the end of this thesis there is a trial with some assumptions about what a generical pulse generator should achieve, to come to a conclusion about which pulse generator from the proposed ones would be the best generical pulse generator to go with.

Computer-generated music composition programs have yet to produce creative, natural sounding music. To date, most approaches constrain the search space heuristically while ignoring the inherent structure of music over time. To address this problem, this thesis introduces NEAT Drummer, which evolves a special kind of artificial neural network (ANN) called compositional pattern producing networks (CPPNs) with the NeuroEvolution of Augmenting Topologies (NEAT) method for evolving increasingly complex structures. CPPNs in NEAT Drummer input existing human compositions and output an accompanying drum track. The existing musical parts form a scaffold i.e. support structure, for the drum pattern outputs, thereby exploiting the functional relationship of drums to musical parts (e.g. to lead guitar, bru:is, etc.) The results are convincing drum patterns that follow the contours of the original song, validating a new approach to computergenerated music composition.

In high-power electric drives, multilevel inverters are generally deployed to address issues such as electromagnetic interference, switch voltage stress and harmonic distortion. The switching frequency of the inverter is always kept low, of the order of 1KHz or even less to reduce switching losses and synchronous pulse width modulation (PWM) is used to avoid the problem of sub-harmonics and beat frequencies. This is particularly important if the switching frequency is very low. The synchronous PWM is getting popularity as its realization is very easy with digital controllers compared to analog controllers. Neutral-point-clamped (NPC) inverters, cascaded H-bridge, and flying-capacitor multilevel inverters are some of the popular schemes used for high-power applications. Hybrids of these multilevel inverters have also been proposed recently to take advantage of the basic configurations. Multilevel inverters can also be realized by feeding the induction motor from both ends (open-end winding) using conventional inverter structures. For controlling the output voltage of these inverters, various PWM techniques are used. Chapter-1 of this thesis provides an over view of the various multilevel inverter schemes preceded by a discussion on basic two-level VSI topology. The inverters used in motor drive applications have to be operated in over-modulation range in order to extract the maximum fundamental output voltage that is possible from the dc-link. Operation in this high modulation range is required to meet temporary overloads or to have maximum power operation in the high speed range (flux weakened region). This, however, introduces a substantial amount of low order harmonics in the Motor phase voltages. Due to these low-order harmonic frequencies, the dynamic performance of the drive is lost and the current control schemes are severely affected especially due to 5th and 7th harmonic components. Further, due to these low-order harmonics and non-linear PWM operation in over-modulation region, frequent over-current fault conditions occur and reliability of the drive is jeopardized. The twelve sided-polygonal space vector diagram (dodecagonal space vectors) can be used to overcome the problem of low order 5th and 7th harmonics and to give more range for linear modulation while keeping the switching frequency at a minimum compared to conventional hexagonal space vector based inverters. Thus, the dodecagonal space-vector switching can be viewed as an engineering compromise between low switching frequency and quality load current waveform. Most of the previous works of dodecagonal space-vector generation schemes are based on NPC inverters. However, sophisticated charge control schemes are required in NPC inverters to deal with the neutral-point voltage fluctuation and the neutral-point voltage shifting issues. The losses in the clamping diodes are another major concern. In the second chapter, a multilevel dodecagonal space-vector generation scheme based on flying capacitor topology, utilizing an open end winding induction motor is presented. The neutral point charge-balancing problem reported in the previous works is not present in this scheme, the clamping diodes are eliminated and the number of power supplies required has been reduced. The capacitors have inherent charge balancing capability, and the charge control is done once in every switching cycle, which gives tight voltage control for the capacitors. For the speed control of induction motors, the space-vector PWM scheme is more advantageous than the sine-triangle PWM as it gives a more linear range of operation and improved harmonic performance. One major disadvantage with the conventional space-vector PWM is that the trigonometric operations demand formidable computational efforts and look-up tables. Carrier based, common-mode injected PWM schemes have been proposed to simplify the PWM process. However, the freedom of selecting the PWM switching sequences is limited here. Another way of obtaining SVPWM is using the reference voltage samples and the nearest vector information to switch appropriate devices for proper time intervals, realizing the reference vector in an average sense. In-formation regarding the sector and nearest vectors can be easily obtained by comparing the instantaneous amplitudes of the reference voltages. This PWM approach is pro-posed for the speed control of the motor in this thesis. The trigonometric operations and the requirement of large look-up tables in the conventional SVPWM are avoided in this method. It has the additional advantage that the switching sequences can be decided at will, which is helpful in reducing further, the harmonic distortion in certain frequency ranges. In this way, this method tries to combine the advantages of vector based methods (conventional SVPWM) and scalar methods (carrier-based methods). The open-end winding schemes allowed the required phase voltage levels to be generated quite easily by feeding from both ends of the windings. Thus, most of the multilevel inverters based on dodecagonal space-vector structures relied on induction motors with open-end windings. The main disadvantage of open-end winding induction motor is that six wires are to be run from the inverter to the motor, which may be unacceptable in certain applications. Apart from the inconvenience of laying six wires, the voltage reflections in the wires can lead to over voltages at the motor terminals, causing insulation failures. Where as the topology presented in chapter-2 of this thesis uses open-end winding motor with flying-capacitor inverters for the generation of dodecagonal space-vectors, the topology presented in chapter-3 utilizes a cascade connection of flying-capacitors and floating H-bridge cells to generate the same set of voltage space-vectors, thus allowing any standard induction motor as the load. Of the methods used for the speed control of induction motors, namely sine-triangle PWM and space vector PWM, the latter that provides extra modulation range is naturally preferred. It is a well-understood fact that the way in which the PWM switching sequences are applied has a significant influence on the harmonic performance of the drive. However, this topic has not been addressed properly for dodecagonal voltage space-vector based multilevel inverter drives. In chapter-4 of the thesis, this aspect is taken into ac-count and the notion of “harmonic flux trajectories” and “stator flux ripple” are used to analyze the harmonic performance of the various PWM switching schemes. Although the PWM method used in this study is similar to that in chapter-2, the modification in the PWM switching sequence in the PWM algorithm yields significant improvements in harmonic performance. The proposed topologies and PWM schemes are extensively simulated and experimentally verified. The control scheme was implemented using a DSP processor running at a clock frequency 150MHz and a four-pole, 3.7kW, 50Hz, 415V three-phase induction motor was used as the load. Since the PWM ports are limited in a DSP, a field-programmable gate array (FPGA) was used to decode the PWM signals from the DSP to generate timing information required for PWM sequencing for all the power devices. The same FPGA was used to generate the dead-time signals for the power devices also.

Σκοπός της παρούσας διπλωματικής εργασίας είναι η μελέτη και ο προσδιορισμός, θεωρητικός και πειραματικός, του συντελεστή Κ της Rician κατανομής σε ένα κανάλι στα 2.4 GHz. Η κατανομή Rice χρησιμοποιείται για την περιγραφή του πλάτους του λαμβανόμενου σήματος σε ένα κανάλι μετάδοσης με ισχυρή επίδραση οπτικής επαφής (Line-of-Sight) μεταξύ κεραίας πομπού και δέκτη. Ο συντελεστής Κ Rice εκφράζει τον λόγο της συνεισφοράς της ισχύος της απευθείας συνιστώσας του σήματος ως προς την συνολική λαμβανόμενη ισχύ λόγω φαινομένων διάχυσης. Χρησιμοποιείται για τον χαρακτηρισμό του καναλιού καθώς και τον υπολογισμό του BER (bit-error-ratio) και της πλέον σημαντικής παραμέτρου των τηλεπικοινωνιών SNR (Signal-to-Noise-Ratio), δηλαδή του λόγου σήματος προς θόρυβο. Στο 1ο κεφάλαιο αναλύονται και περιγράφονται μερικές από τις σημαντικότερες τεχνολογίες ασυρμάτων δικτύων, από την πρώτη στιγμή της εμφάνισής τους (δίκτυα 1ης και 2ης γενιάς) έως τα πιο σύγχρονα δίκτυα 3ης και 4ης γενιάς, και παρουσιάζονται οι ζώνες συχνοτήτων που καταλαμβάνουν αυτές οι τεχνολογίες στο διαθέσιμο ηλεκτρομαγνητικό φάσμα. Στο 2ο κεφάλαιο μελετώνται οι 3 βασικότεροι μηχανισμοί διάδοσης του ηλεκτρομαγνητικού κύματος μέσα σε ένα ασύρματο κανάλι (ανάκλαση, περίθλαση, σκέδαση), περιγράφονται οι τύποι των απωλειών που υφίσταται ένα σήμα κατά την μετάδοση του και τα φαινόμενα των διαλείψεων, που παρατηρούνται πολύ έντονα σε ένα κινητό και μεταβαλλόμενο περιβάλλον διάδοσης. Στο 3ο κεφάλαιο γίνεται περιγραφή του μοντέλου ηλεκτρομαγνητικής μετάδοσης κατά Rice, δηλαδή όταν η απευθείας συνιστώσα του σήματος είναι η ισχυρότερη διαδρομή που ακολουθεί το εκπεμπόμενο σήμα κατά την πορεία του μέχρι τον δέκτη (LoS). Αναλύεται η σημαντικότερη παράμετρος αυτού του τύπου μετάδοσης, δηλαδή ο συντελεστής Κ, και παρουσιάζονται διάφορες μέθοδοι προσδιορισμού του τόσο θεωρητικά όσο και πειραματικά. Στο 4ο κεφάλαιο παρουσιάζονται τα αποτελέσματα των πειραματικών μας μετρήσεων σε διάφορες τοπολογίες μετάδοσης με LoS για ένα δίκτυο Wi-Fi, δηλαδή για συχνότητα λειτουργίας στα 2.4 GHz. Για κάθε τοπολογία, περιγράφεται πλήρως το περιβάλλον μετάδοσης καθώς και ολόκληρη η διαδικασία εκπόνησης των μετρήσεων (μετρητικά όργανα, απαραίτητο λογισμικό, τυχόν προσεγγίσεις κτλ.). Τέλος, στο 5ο και τελευταίο κεφάλαιο, παρουσιάζεται μια μέθοδος υπολογισμού του συντελεστή Κ μέσω των μετρήσεων και με τη βοήθεια του μοντέλου ελευθέρου χώρου, που χρησιμοποιείται για τον υπολογισμό των συνολικών απωλειών διαδρομής του σήματος. Τα αποτελέσματα των υπολογισμών χρησιμοποιήθηκαν, με την βοήθεια του Matlab, για την κατασκευή της CDF των τιμών του Κ αλλά και της γραφικής παράστασης της μεταβολής του Κ συναρτήσει της απόστασης. Οι εμπειρικές CDF συγκριθήκαν και προσεγγιστήκαν με γνωστές θεωρητικές CDF, και η συνάρτηση της μεταβολής του Κ με την απόσταση προσεγγίστηκε με όρους Goodness of Fit με την βοήθεια της γενικής μορφής γνωστών συναρτήσεων. Κλείνοντας, στην τελευταία παράγραφο της εργασίας αφήνεται περιθώριο και δίνεται τροφή για μελλοντική εργασία πάνω στην μελέτη και τον προσδιορισμό του συντελεστή Κ της Rice τόσο για εσωτερικούς όσο και για εξωτερικούς χώρους. / The main purpose of this thesis, is the analysis and estimation , theoretical and empirical, of the Rician K factor for a wireless channel at 2.4 GHz. The Rician power density function is used to describe the amplitude of the received signal when there is a strong LOS component. The Rician K factor expresses the ratio of the power component due to LOS signal propagation and the received signal power due to diffuse components (reflection, scattering, diffraction etc.). It is commonly used for the channel's characterization and the estimation of BER (bit error rate) and SNR (signal to noise ratio), a very important parameter for telecommunications. In the 1st chapter, some of the most important wireless systems are described, since their very first appearance (1G & 2G networks) until the latest 3rd and 4rth generation systems. We also present the current frequency bands and how they are spread at the given electromagnetic spectrum. In the 2nd chapter, the 3 basic propagation mechanisms (reflection, scattering, diffraction) are studied. In addition, we describe all types of signal attenuation within a wireless channel and the fading phenomena that are so commonly seen in mobile and continuously changing propagation environments. In the 3rd chapter, the Rician model of electromagnetic propagation, where LOS is the strongest path of signal components, is analyzed. The most important parameter of this propagation type, the Rician K factor, is also studied. Therefore, various methods of theoretical and empirical estimation of the K factor are presented. In the 4rth chapter, we include the results of our measurements in various LOS propagation topologies for a Wi-Fi system at 2.4 GHz. For each measurement topology, the propagation environment as well as the entire measurement procedure, are thoroughly described. Lastly, in the 5th and final chapter, a K factor estimation method based on the empirical set of data and the Free Space Model, used for the average path loss calculation, is presented. The results of our measurements via the help of the Matlab software were used in order to plot the CDF of K values as well as the K values versus d (distance) curve. Using curve fitting methods, the empirical CDFs and plots were compared to theoretical ones in terms of Goodness of Fit. In the closing section, possible future research in the aforementioned fields is proposed.

La dissémination d'informations (broadcast) est essentielle pour de nombreuses applications réparties. Celle-ci doit être efficace, c'est à dire limiter la redondance des messages, et assurer forte fiabilité et faible latence. Nous considérons ici les algorithmes répartis profitant des propriétés des topologies sous-jacentes. Cependant, ces propriétés et les paramètres dans les algorithmes sont hétérogènes. Ainsi, nous devons trouver une manière pour les comparer équitablement. D'abord, nous étudions les protocoles probabilistes de dissémination d'informations (gossip) exécutées sur trois graphes aléatoires. Les trois graphes représentent les topologies typiques des réseaux à grande-échelle : le graphe de Bernoulli, le graphe géométrique aléatoire et le graphe scale-free. Afin de comparer équitablement leurs performances, nous proposons un nouveau paramètre générique : le fanout effectif. Pour une topologie et un algorithme donnés, le fanout effectif caractérise la puissance moyenne de la dissémination des sites infectés. De plus, il simplifie la comparaison théorique des différents algorithmes sur une topologie. Après avoir compris l'impact des topologies et les algorithmes sur les performances , nous proposons un algorithme fiable et efficace pour la topologie scale-free.

Notre recherche porte sur des méthodes pour garantir la QoS dans les réseaux filaires classiques, optiques, ad hoc et le réseau global Internet au niveau des domaines. Afin de valider les méthodes proposées, nous créons des modèles à partir des outils de la théorie des files d'attente. Nous étudions les méthodes analytiques et les méthodes numériques afin de traiter les générateurs de chaînes de Markov. Nous utilisons également dans nos études la simulation à évènements discrets. Le travail sur le réseau inter-domaine a nécessité le développement d'un outil pour la génération de topologies aléatoires avec une hiérarchie correspondant à celle observée dans l'Internet.