Ce travail se concentre sur la conception de VCO mm-wave pour les applications de Backhaul en BiCMOS 55 nm technologie. Toutes les conceptions de VCO proposées sont par rapport à conventionnel LC-tank oscillateur. La première conception de l'oscillateur proposé fonctionne entre 81-86 GHz. L'innovation est liée à l'utilisation d'une bande coplanaires ondes lentes (S-CPS) comme inducteur différentiel. Grace à facteur de qualité élevé (≈ 33) de S-CPS, le bruit de phase a été amélioré de 20 dBc/Hz à l'offset 10MHz et la consommation d'énergie a été réduite de 14% aussi. La plage de réglage de fréquence (FTR) était de 5,3 GHz seulement. La seconde conception du VCO est sur la base de ligne déphaseur chargé comme un résonateur. Le déphaseur a été conçu en utilisant une topologie dissymétrique de S-CPS, afin de parvenir à une meilleure FTR. Mais la performance réalisée de VCO n'a pas été beaucoup améliorée en raison de la capacité parasite en charge. Ainsi, avec le même dissymétrique résonateur déphaseur sur la base d'un oscillateur d'onde permanente distribuée a été conçu, ce qui a réduit l'effet de charge et de conduire à une FTR de 8 GHz. Enfin, un buffer moins mm-wave oscillateur stationnaire a été conçu. Dans ce proposé moins oscillateur buffer, il a montré que l’impédance caractéristique de sortie peut être envisagé grâce à un choix judicieux de la position de sortie. Par conséquent, aucun buffer de sortie n’est nécessaire dans la conception proposée, en raison de la flexibilité dans le choix de la position long de sortie de SWO. Cette innovation conduit à deux mérites. Tout d'abord une sortie 50 ohms peut-être synthétisé sans consommation d'énergie supplémentaire et d'autre part la taille est réduite si un réseau d'adaptation est nécessaire pour connecter le VCO à un mélangeur ou un autre bloc de construction du système d'émetteur-récepteur. / This work focuses on the design of mm-wave VCO for Backhaul applications in BiCMOS 55 nm technology. All the proposed VCO designs are compared to the conventional LC-tank oscillator. The first proposed oscillator design operates between 81-86 GHz. The innovation is linked to the use of a slow-wave coplanar strip (S-CPS) as a differential inductor. Thanks to high quality factor (≈ 33) of S-CPS, the phase noise was improved by 20 dBc/Hz at 10 MHz offset and the power consumption was reduced by 14 % as well. The achieved frequency tuning range (FTR) was 5.3 GHz only. The second VCO design is based on loaded line phase shifter as a resonator. The phase shifter has been designed using an unsymmetric topology of S-CPS in order to achieve better FTR. But the achieved VCO performance was not improved a lot due to the loading parasitic capacitance. So, with the same unsymmetric phase shifter based resonator a distributed standing wave oscillator was designed, which reduced the loading effect and lead to a FTR of 8 GHz. Finally, a buffer less mm-wave standing wave oscillator was designed. In this proposed buffer less oscillator it is shown that any output characteristic impedance can be envisaged thanks to a careful choice of the output position. Hence, no output buffer is needed in the proposed design, due to the flexibility in choosing the output position along the SWO. This innovation leads to two merits. Firstly a 50 ohms output can be synthesized without any additional power consumption and secondly the size is reduced if a matching network is needed to connect the VCO to a mixer or another building block of the transceiver system.

Les oscillateurs sont des blocs qui figurent dans presque tous les circuits. En effet,ils sont utilisés pour générer les signaux de synchronisation (les horloges), les signauxmodulés et démodulés ou récupérer des signaux noyés dans du bruit (détection synchrone).Les caractéristiques de ces oscillateurs dépendent de l'application. Dans le cas des boucles àverrouillage de phase (PLL), il existe de fortes exigences en matière de stabilité et de bruitde phase. En outre, face aux avancées des technologies nanométriques, il est égalementnécessaire de prendre en compte les effets liés à la variabilité des procédés de fabrication.Aujourd'hui, de nombreuses études sont menées sur les oscillateurs asynchrones en anneauqui présentent des caractéristiques bien adaptées à la gestion de la variabilité et qui offrentune structure appropriée pour limiter le bruit de phase. A ce titre, les anneaux asynchronessont considérés comme une solution prometteuse pour générer des horloges.Cette thèse étudie les avantages et les potentiels offerts par les oscillateursasynchrones en anneau. Deux applications principales ont été identifiées. D’une part, cesoscillateurs sont une solution prometteuse pour la génération d’horloges polyphasées àhaute fréquence et à faible bruit de phase. D’autre part, ils constituent une alternativesimple, dans une certaine mesure aux oscillateurs plus conventionnels et aux DLLs, car ilssont programmables en fréquence numériquement et sont susceptibles de fournir lesfonctionnalités d’arrêt de type gated clock de façon native. Plusieurs oscillateurs ont étéconçus, implémentés, fabriqués en technologie CMOS 65 nm de STMicroelectronics et,finalement, caractérisés sous pointes. Ces travaux ont notamment permis de démontrer lapertinence de ces oscillateurs, qui constituent une alternative sérieuse aux très classiquesoscillateurs en anneau à base d’inverseurs. / Oscillators are essential building blocks in many applications. For instance, they arebasic blocks in almost all designs: they are part of PLLs, clock recovery systems andfrequency synthesizers. The design of a low phase-noise multi-phase clock circuitry isespecially crucial when a large number of phases is required. There are plenty of workscovering the design of multiphase clocks. High frequency oscillators can be implementedusing ring structures, relaxation circuits or LC circuits. Ring architectures can easily providemultiple clocks with a small die size. With the advanced nanometric technologies, it is alsorequired to deal with the process variability, stability and phase noise. Today many studiesare oriented to Self-Timed Ring (STR) oscillators which present well-suited characteristicsfor managing process variability and offering an appropriate structure to limit the phasenoise. Therefore, self-timed rings are considered as promising solution for generatingclocks.This thesis studies the benefits and potential offered by Self-Timed Ring oscillators.Two main applications have been identified. On the one hand, these oscillators are apromising solution for the generation of high-frequency multi-phase low phase noise clocks.On the other hand, they are a simple alternative to some extent to the conventionaloscillators and DLLs, because they are digitally programmable. Several oscillators havebeen designed, implemented, manufactured in 65 nm CMOS technology fromSTMicroelectronics, and characterized. This work has demonstrated the relevance of theseoscillators, which are a serious alternative to the conventional ring oscillators based oninverters.

Cette thèse se concentre sur la conception de circuits intégrés radio fréquence en technologie CMOS. En particulier, l’effort est axé sur les circuits pour la synthèse de fréquence (boucles à verrouillage de phase) pour les émetteurs/récepteurs. L’attention se concentre sur la conception des blocs critiques comme les oscillateurs contrôlé en tension(VCO) et les diviseurs de fréquence. La première partie de la thèse présente des directives pour la conception de VCO à résonateur LC à résistance négative et la conception d’un oscillateur en quadrature contrôlé en tension (QVCO) à 15GHz. Ce dernier représente la contribution à la réalisation d’un synthétiseur de fréquence à 15GHz en technologie CMOS 130 nm pour des applications satellites réalisé en collaboration avec Polytech’Nice (Sophia Antipolis, France). La deuxième partie de la thèse montre la contribution à la réalisation d’un synthétiseur de fréquence 60GHz en technologie CMOS 65 nm, en collaboration avec le laboratoire LAAS (Toulouse, France) pour les réseaux haut débit sans fil et à courte distance WPAN. Une attention particulière a été portée sur la conception des blocs fonctionnant des les bandes millimétriques tel que l’oscillateur et les deux premiers blocs de la chaine de division.En ce qui concerne les diviseurs de fréquence, deux topologies à injection ont été utilisées pour leur efficacité et leur basse consommation. Le prédiviseur a été conçu avec une topologie oscillateur à résonateur LC synchronisé suivi d’un oscillateur en anneau synchronisé. Le VCO a une topologie à résistance négative. Tous les circuits ci-dessus ont été réalisés et testée avec succès. / The research activities presented in this thesis are related to the design of analog CMOS Radio Frequency Integrated Circuits. In particular the effort was focused on frequency synthesizers (Phase-Locked Loop) for transceiver. This work especially deals with critical blocks such as Voltage Controlled Oscillator (VCO) and Frequency Dividers.The first part of the thesis reports the design guidelines of a negative resistance LC-tank VCO and the design of a 15GHz Quadrature Voltage Controlled Oscillator. This represents the contributions to the realizations of a Phase-Locked Loop (PLL) realization in CMOS 130 nm technology for satellite applications in collaborations with the Polytech’Nice Sophia laboratory in France. The second part of this work reports the design contribution of a 60GHz Phase-Locked Loop in 65 nm CMOS technology for Wireless Personal Area Network (WPAN) applications in collaboration with the LAAS laboratory (Toulouse, France). In particular the design efforts were devote to the blocks working at millimeter Wave (mmW) frequency such as VCO and Frequency Divider (FD). Concerning the Frequency Dividers the Injection-Locked topology was selected for the sake of its high frequency and low power characteristics. In particular the prescaler is an Injection-Locked LC-tank Frequency Divider (ILLCFD) followed by an Injection-Locked Ring Oscillator Frequency Divider (ILROFD). For the VCO the negative resistance design approach has been employed.All cited circuits have been implemented and succesfully tested.

The competitive market of wireless communication devices demands low power and low cost RF solutions. A quadrature local oscillator (LO) is an essential building block for most transceivers. As the CMOS technology scales deeper into the nanometer regime, design of a low-power low-voltage quadrature LO still poses a challenge for RF designers. This dissertation investigates a new quadrature LO topology featuring a transformer-based voltage controlled oscillator (VCO) stacked with a divide-by-two for low-power low-voltage wireless applications. The transformer-based VCO core adopts the Armstrong VCO configuration to mitigate the small voltage headroom and the noise coupling. The LO operating conditions, including the start-up condition, the oscillation frequency, the voltage swing and the current consumption are derived based upon a linearized small-signal model. Both linear time-invariant (LTI) and linear time-variant (LTV) models are utilized to analyze the phase noise of the proposed LO. The results indicate that the quality factor of the primary coil and the mutual inductance between the primary and the secondary coils play an important role in the trade-off between power and noise. The guidelines for determining the parameters of a transformer are developed. The proposed LO was fabricated in 65 nm CMOS technology and its die size is about 0.28 mm2. The measurement results show that the LO can work at 1 V supply voltage, and its operation is robust to process and temperature variations. In high linearity mode, the LO consumes about 2.6 mW of power typically, and the measured phase noise is -140.3 dBc/Hz at 10 MHz offset frequency. The LO frequency is tunable from 1.35 GHz to 1.75 GHz through a combination of a varactor and an 8-bit switched capacitor bank. The proposed LO compares favorably to the existing reported LOs in terms of the figure of merit (FoM). More importantly, high start-up gain, low power consumption and low voltage operation are achieved simultaneously in the proposed topology. However, it also leads to higher design complexity. The contributions of this work can be summarized as 1) proposal of a new quadrature LO topology that is suitable for low-power low-voltage wireless applications, 2) an in-depth circuit analysis as well as design method development, 3) implementation of a fully integrated LO in 65 nm CMOS technology for GPS applications, 4) demonstration of high performance for the design through measurement results. The possible future improvements include the transformer optimization and the method of circuit analysis. / Ph. D.

A Voltage Controlled Oscillator (VCO) is used to generate a signal with a frequency that is a function of an input voltage amplitude, and is an integral part of circuits such as phase locked loops, frequency synthesizers, down conversion receivers, and clock generators. A typical design flow for a VCO involves architecture selection based on specification, calculation of circuit parameters, simulation, and iterations of circuit parameters based on the simulation result. In such a design flow, changes in specification or process can lead to significant redesign. This report focuses on a C++ based LC VCO generation software that seeks to automate the design process and that includes calculation of circuit parameters, creation of Spectre netlist, invocation of simulation, automated checking of the result, and a feedback mechanism to modify circuit parameters until the design can converge to the desired specification. Object Oriented Programming principles such as inheritance, polymorphism, encapsulation, class abstraction are exercised to maximize reusability and portability to other projects which may require different foundry device models and supply voltages. / text

No description available.

Le coût et le temps de test élevés des testeurs RadioFréquences (RF) poussent à l'optimisation de test, voir même à des méthodes alternatives de test pour les circuits analogiques-mixtes RF. Jusqu'à présent, le test des circuits RF était effectué par la validation des spécifications fonctionnelles du circuit. Cependant, à cause des contraintes imposées par les fréquences en jeu de plus en plus élevées et par des temps de test les plus réduits possible, la mesure de certaines spécifications fonctionnelles, même sur testeurs dédiés, n'est plus faisable. Il est ainsi nécessaire de développer de nouvelles méthodes de test permettant de répondre à ces besoins. Cette thèse a pour objectif de commencer le développement d'un bouquet des circuits de test sur puce de type BIST (Built-In Self Test) le plus général possible pour les circuits RF afin de supporter l'étape de conception et d'optimiser le test de production. La validation de ces circuits de BIST est orientée défaut. Le développement de la stratégie de validation d'un circuit de BIST se base sur les points suivants : choix des mesures de test avec simulation du circuit sous test ; modélisation des mesures de test et de spécifications du circuit sous test a travers simulations Monte-Carlo ; génération d'une population statistiquement plus représentative a travers la théorie des Copules ; génération d'une liste de fautes qui peuvent se produire dans le circuits sous test ; simulations d'injection de fautes ; analyse des métriques de test telles que le taux de couverture, le taux de circuits défaillants qui passent le test (defect level) et le rejet de circuits fonctionnels par le test (yield loss). Ces travaux ont été menés sur un cas d'étude industriel de type synthétiseur de fréquence, PLL (Phase-Locked Loop), conçu à STMicroelectronics.

This thesis presents a wide tuning, low phase noise CMOS integer-N frequency synthesizer with 1.8V power supply. The frequency synthesizer is designed using the TSMC 0.18£gm CMOS 1P6M technology. The proposed frequency synthesizer consists of a phase-frequency detector, a charge pump, a low-pass loop filter, a voltage control oscillator, an auto-band selection (ABS), an optimum-band selection (OBS), and a pulse-swallow divider. In system design, we present the new architecture for voltage-controlled oscillator with switched capacitors technique with a lowered VCO gain (KVCO) to achieve wide tuning range and low phase noise in order to cover the desired operating frequency bands and to accommodate process, voltage, and temperature (PVT) variations. The ABS accomplishes the efficient search for a VCO discrete tuning curve among a group of frequency sub-bands. It is apparent to reduce the calibration time by adopting the binary search algorithm to select the calibration word. However, the variation of Kvco across different channels can still be large after the execution of ABS. There might be many sub-bands covering the desired frequency. Hence the sub-band which is selected by ABS could not be an optimum choice for the minimum Kvco variation. The OBS is proposed to implement an algorithm in order to find the optimum solution which has the minimum Kvco variation and covers the desired frequency. The Kvco variation is quantified by OBS and using this value to adjust the charge pump current. Therefore, Loop bandwidth and stability were maintained across the operating range by using optimum-band selection(OBS) and a programmable charge pump.

The permeation of CMOS technology to radio frequencies and beyond has fuelled an urgent need for a diverse array of passive and active circuits that address the challenges of rapidly emerging wireless applications. While traditional analog based design approaches satisfy some applications, the stringent requirements of newly emerging applications cannot necessarily be addressed by existing design ideas and compel designers to pursue alternatives. One such alternative, an amalgamation of microwave and analog design techniques, is pursued in this work. A number of passive and active circuits have been designed using a combination of microwave and analog design techniques. For passives, the most crucial challenge to their CMOS implementation is identified as their large dimensions that are not compatible with CMOS technology. To address this issue, several design techniques – including multi-layered design and slow wave structures – are proposed and demonstrated through experimental results after being suitably tailored for CMOS technology. A number of novel passive structures - including a compact 10 GHz hairpin resonator, a broadband, low loss 25-35 GHz Lange coupler, a 25-35 GHz thin film microstrip (TFMS) ring hybrid, an array of 0.8 nH and 0.4 nH multi-layered high self resonant frequency (SRF) inductors are proposed, designed and experimentally verified. A number of active circuits are also designed and notable experimental results are presented. These include 3-10 GHz and DC-20 GHz distributed low noise amplifiers (LNA), a dual wideband Low noise amplifier and 15 GHz distributed voltage controlled oscillators (DVCO). Distributed amplifiers are identified as particularly effective in the development of wideband receiver front end sub-systems due to their gain flatness, excellent matching and high linearity. The most important challenge to the implementation of distributed amplifiers in CMOS RFICs is identified as the issue of their miniaturization. This problem is solved by using integrated multi-layered inductors instead of transmission lines to achieve over 90% size compression compared to earlier CMOS implementations. Finally, a dual wideband receiver front end sub-system is designed employing the miniaturized distributed amplifier with resonant loads and integrated with a double balanced Gilbert cell mixer to perform dual band operation. The receiver front end measured results show 15 dB conversion gain, and a 1-dB compression point of -4.1 dBm in the centre of band 1 (from 3.1 to 5.0 GHz) and -5.2 dBm in the centre of band 2 (from 5.8 to 8 GHz) with input return loss less than 10 dB throughout the two bands of operation.

The frequency synthesizer, which performs the main role of carrier generation for the down-conversion/up-conversion operations, is a key building block in radio transceiver front-ends. The design of a synthesizer for a 2.4 GHz IEEE 802.15.4/Zigbee transceiver forms the core of this work. This thesis provides a step-by-step procedure for the design of a frequency synthesizer in a transceiver environment, from the mapping of standard-specifications to its integrated circuit implementation in a CMOS technology. The results show that careful system level planning leads to high-performance realizations of the synthesizer. A strategy of using different supply voltages to enhance the performance of each building block is discussed. A section is presented on layout and board level issues, especially for radio-frequency systems, and their effect on synthesizer performance. The synthesizer consumes 15.5 mW and meets the specifications of the 2.4 GHz IEEE 802.15.4/Zigbee standard. It is capable of 5 GHz operation with a VCO sensitivity of 135 MHz/V and a tuning range of 700 MHz. It can be seen that the adopted methodology can be used for the design of high-performance frequency synthesizers for any narrow-band wireless standard.