Master of Science / Department of Electrical and Computer Engineering / William B. Kuhn / RF frequency synthesizer systems are prevalent in today’s electronics. In a synthesizer there is a sensitive analog oscillator that may be affected by two different types of noise. The first is random noise injection from active devices. This results in phase noise in the synthesizer’s spectrum. The second noise source is deterministic. A digital frequency divider with high-amplitude switching is an example of such a deterministic source. This noise enters the system through various forms of electric or magnetic field coupling and manifests itself as spurs or pulling. Both forms of noise can adversely affect system performance. We will first summarize methods for reducing noise. These already known steps have to do with layout techniques, device geometry, and general synthesizer topologies. Then we will show ways to isolate noisy interfering circuits from the sensitive analog systems. Finally, we present some considerations for reducing the effects of random noise. A power supply filter can improve the effects of deterministic noise such as undesired signals on the supply line. We show several ways to improve the rejection of high frequency supply noise (characterized by the power supply rejection ratio or PSRR) through the design of a voltage regulator. The emphasis is on new techniques for obtaining good PSRR at S-band frequencies and above. To validate the techniques, we designed a regulator in Peregrine Semiconductor’s .25µm ULTRA CMOS Silicon on Sapphire process. It produces a 2.5V output with an input ranging from 2.6V to 5V and has a maximum current sourcing of 70mA. The regulator’s low drop out performance is 60mV with no load and it achieves a power supply ripple reduction of 29.8 dB at 500 MHz. To address random noise in synthesizers, the thesis provides preliminary investigation of an oscillator topology change that has been proposed in the literature. This proposed change reduces the phase noise of the oscillator within the overall system. A differential cross-coupled design is the usual topology of choice, but it is not optimal for noise performance. We investigate current noise injection in the traditional design and present an updated design that uses a differential Colpitts oscillator as an alternative to classic cross-coupled designs.

Ericsson har haft ett problem som påverkar deras mikrovågsradio. Detta problem handlar i grunden om mekaniska störningar som påverkar dataöverföringen mellan två radioenheter. Dessa störningar resulterar i bitfel på grund av olika orsaker. Dessa orsaker undersöks i projektet, för att i senare skede kunna förbättra precisionen av dataöverföringen. Genom att skicka signalerna med olika frekvenser på ett automatiserat och mer noggrant sätt, ökar möjligheten att testa radion i fler miljöer samtidigt möjligheten av att täcka ett så stort frekvensområde som möjligt ges. Arbetet är en blandning av elektronik, mekanik, akustik och programmering. Tanken är att den nya mätmetoden som presenteras skall vara automatisk och mjukvarustyrd. Även manuell styrning skall vara möjlig. Arbetet har bestått av forskning, marknadsskanning och kontakt med personer som är involverade inom området, detta för att hitta det bästa sättet att utveckla en ny felsökningsmetod.Med hjälp av olika testkörningar som studeras noggrant kommer förståelsen för ovan nämnda störningar att öka, vilket förhoppningsvis hjälper oss att hitta olika sätt att hantera dessa störningar i enskilda komponenter samt konstruktionen i sin helhet. Det finns flera förslag på alternativ, men genom ökad förståelse och kunskap inom området har det visat sig att det lämpligaste alternativet är att använda en shaker och en speaker som sändare och ett piezoelement som givare. Detta piezoelement tillsammans med en förstärkare mäter signalerna och övervakas med ett oscilloskop. Shakern och speakern drivs av en signalgenerator via en förstärkare. Alla dessa instrument styrs via ett styrprogram som är programmerad i LabVIEW. Styrprogrammets uppgift är att skanna över ett bestämt frekvensintervall med en konstant amplitud. Givaren mäter dessa signaler och sparar till en textfil. Denna information är viktig för att finna resonansfrekvenser och även övervaka den verkliga utsignalen som kommer fram till testobjektet.Detta arbete kommer förhoppningsvis att vara av stor betydelse för utvecklingen av nya produkter och kan bli ett användbart verktyg för andra ingenjörer inom Ericsson i framtiden. / Program: Utvecklingsingenjör

<p>Automotive Radars have introduced various functions on automobiles for driver’s safety and comfort, as part of the Intelligent Transportation System (ITS) including Adaptive Cruise Control (ACC), collision warning or avoidance, blind spot surveillance and parking assistance. Although such radar systems with 24 GHz carrier frequency are already in use but due to some regulatory issues, recently a permanent band has been allocated at 77-81 GHz, allowing for long-term development of the radar service. In fact, switchover to the new band is mandatory by 2014.</p><p>A frequency multiplier will be one of the key components for such a millimeter wave automotive radar system because there are limitations in direct implementation of low phase noise oscillators at high frequencies. A practical way to build a cost-effective and stable source at higher frequency is to use an active multiplier preceded by a high spectral purity VCO operating at a lower frequency. Recent improvements in the performance of SiGe technology allow the silicon microelectronics to advance into areas previously restricted to compound semiconductor devices and make it a strong competitor for automotive radar applications at 79 GHz.</p><p>This thesis presents the design of active frequency doubler circuits at 20 GHz in a commercially available SiGe BiCMOS technology and at 40GHz in SiGe bipolar technology (Infineon-B7h200 design). Buffer/amplifier circuits are included at output stages to drive 50 Ω load. The frequency doubler at 20 GHz is based on an emitter-coupled pair operating in class-B configuration at 1.8 V supply voltage. Pre-layout simulations show its conversion gain of 10 dB at -5 dBm input, fundamental suppression of 25dB and NF of 12dB. Input and output impedance matching networks are designed to match 50 Ω at both sides.</p><p>The millimeter wave frequency doubler is designed for 5 V supply voltage and has the Gilbert cell-based differential architecture where both RF and LO ports are tied together to act as a frequency doubler. Both pre-layout and post-layout simulation results are presented and compared together. The extracted circuit has a conversion gain of 8 dB at -8 dB input, fundamental suppression of 20 dB, NF of 12 dB and it consumes 42 mA current from supply. The layout occupies an area of 0.12 mm2 without pads and baluns at both input and output ports. The frequency multiplier circuits have been designed using Cadence Design Tool.</p>

In a conventional charge-pump based PLL design, the loop parameters such as the band-width, jitter performance, charge-pump current, pull-in range among others govern the ar-chitecture and implementation details of the PLL. Different loop parameter specificationschange with a change in the reference frequency and inmost cases, requires careful re-designof some of the PLL blocks. This thesis describes the implementation of a semi-digital PLLfor high bandwidth applications, which is self-compensated, low-power and exhibits band-width tracking for all reference frequencies between 40 MHz and 1.6 GHz in 65nm CMOStechnology.This design can be used for a wide range of reference frequencies without redesigning anyblock. The bandwidth can be fixed to some fraction of the reference frequency during designtime. In this thesis, the PLL is designed to make the bandwidth track 5% of the referencefrequency. Since this PLL is self-compensated, the PLL performance and the bandwidthremains same over PVT corners.

Automotive Radars have introduced various functions on automobiles for driver’s safety and comfort, as part of the Intelligent Transportation System (ITS) including Adaptive Cruise Control (ACC), collision warning or avoidance, blind spot surveillance and parking assistance. Although such radar systems with 24 GHz carrier frequency are already in use but due to some regulatory issues, recently a permanent band has been allocated at 77-81 GHz, allowing for long-term development of the radar service. In fact, switchover to the new band is mandatory by 2014. A frequency multiplier will be one of the key components for such a millimeter wave automotive radar system because there are limitations in direct implementation of low phase noise oscillators at high frequencies. A practical way to build a cost-effective and stable source at higher frequency is to use an active multiplier preceded by a high spectral purity VCO operating at a lower frequency. Recent improvements in the performance of SiGe technology allow the silicon microelectronics to advance into areas previously restricted to compound semiconductor devices and make it a strong competitor for automotive radar applications at 79 GHz. This thesis presents the design of active frequency doubler circuits at 20 GHz in a commercially available SiGe BiCMOS technology and at 40GHz in SiGe bipolar technology (Infineon-B7h200 design). Buffer/amplifier circuits are included at output stages to drive 50 Ω load. The frequency doubler at 20 GHz is based on an emitter-coupled pair operating in class-B configuration at 1.8 V supply voltage. Pre-layout simulations show its conversion gain of 10 dB at -5 dBm input, fundamental suppression of 25dB and NF of 12dB. Input and output impedance matching networks are designed to match 50 Ω at both sides. The millimeter wave frequency doubler is designed for 5 V supply voltage and has the Gilbert cell-based differential architecture where both RF and LO ports are tied together to act as a frequency doubler. Both pre-layout and post-layout simulation results are presented and compared together. The extracted circuit has a conversion gain of 8 dB at -8 dB input, fundamental suppression of 20 dB, NF of 12 dB and it consumes 42 mA current from supply. The layout occupies an area of 0.12 mm2 without pads and baluns at both input and output ports. The frequency multiplier circuits have been designed using Cadence Design Tool.

With decreasing feature sizes, lowered supply voltages and increasing operating frequencies, the radiation tolerance of digital circuits is becoming an increasingly important problem. Many radiation hardening techniques have been presented in the literature for combinational as well as sequential logic. However, the radiation tolerance of clock generation circuitry has received scant attention to date. Recently, it has been shown that in the deep submicron regime, the clock network contributes significantly to the chip level Soft Error Rate (SER). The on-chip Phase Locked Loop (PLL) is particularly vulnerable to radiation strikes. In this thesis, we present a radiation hardened PLL design. Each of the components of this design-the voltage controlled oscillator (VCO), the phase frequency detector (PFD) and the charge pump/loop filter-are designed in a radiation tolerant manner. Whenever possible, the circuit elements used in our PLL exploit the fact that if a gate is implemented using only PMOS (NMOS) transistors then a radiation particle strike can result only in a logic 0 to 1 (1 to 0) flip. By separating the PMOS and NMOS devices, and splitting the gate output into two signals, extreme high levels of radiation tolerance are obtained. Our design uses two VCOs (with cross-coupled inverters) and charge pumps, so that a strike on any one is compensated by the other. Our PLL is tested for radiation immunity for critical charge values up to 250fC. Our SPICE-based results demonstrate that after exhaustively striking all circuit nodes, the worst case jitter of our hardened PLL is just 37.4 percent. In the worst case, our PLL returns to the locked state in 2 cycles of the VCO clock, after a radiation strike. These numbers are significant improvements over those of the best previously reported approaches.

Because of IC technology evolution and the increase of market demand, the communication industry grows vigorously in recent years. The voltage-controlled oscillator plays a key role in the RF transceiver and provides oscillation signals needed for upconversin and downconvertion. Usually, we separate the signals into I/Q channels for modulation and demodulation in upconversin and downconvertion. Because the quality of the local oscillator influences the performance of communication system, designing a voltage-controlled oscillator that can provide two identical signals in accurate quadrature is necessary. In this thesis, a new quadrature voltage-controlled oscillator is presented. We use two identical relaxation oscillators with adjustable Schmitt triggers to construct the cross-coupled architecture. This oscillator has accurate ( <1¢X) and stable quadrature outputs which are independent of operating frequency and process variations. This oscillator circuit is fabricated in TSMC 0.35£gm CMOS Mixed-Signal process provided by National Chip Implementation Center (CIC). Our design is verified by simulation and measurement results.

This thesis presents a low power consumption, low phase noise, and fast locking CMOS fractional-N frequency synthesizer with optimalied voltage-controlled oscillator. The frequency synthesizer is designed in a TSMC 0.18£gm CMOS 1P6M technology process. It can be used for IEEE 802.16e mobile Wimax¡¦s devices and outputing frequency is ranged from 2.3GHz to 2.45GHz for the local oscillator in RF front-end circuits. The proposed frequency synthesizer consists of a phase-frequency detector (PFD), a charge pump (CP), a low-pass loop filter (LPF), a voltage-controlled oscillator (VCO), a multi-modulus divider, and a delta-sigma modulator (DSM). In system design, two voltage-controlled oscillators we presented to achieve low power consumption, low phase noise, and stable output swing. Delta-sigma modulator (DSM) is adopted to produce high frequency resolution, switching over frequency fast and very low phase noise. This thesis proposes a switch circuit which can reduce the lock of time of synthesizer. In the mean time it also reduces the emergence of lose lock.

With the advancement in wireless communication, there has been a lot of overlap in the frequency spectrum used by different applications in the lower frequency band. Also there is an ever-increasing demand for high-speed wireless data transfer. Due to the aforementioned reasons, a lot of work is being done recently in the unlicensed 60GHz bandwidth due to the high data rates it can support. But it is tough to achieve long-range point-to-point transmission at this frequency due to the limited output power and high path losses. A phased array system is a viable solution at these mmWave frequencies to achieve highly directive long-range point-to-point communication. The objective of this research is the design and implementation of phase shifters, VCO and LNA for mmWave phased array system. In this work, active and passive quadrature generation schemes integrated with a vector modulator have been proposed that can be used to produce arbitrary phase shift with a deterministic resolution at the LO signal. Also, alternate IF and PLL based phase shifting schemes for a mmWave phased array system have been proposed. A complete design procedure from parasitic modeling of devices to verification of the design using EM simulations has been discussed in this work. The simulation results are compared with actual measurement results from the fabricated chip and the performance of the various circuits has been analyzed. Furthermore, the designs of VCO and low noise amplifier to be used in the mmWave phased array system are discussed here.

This thesis focuses on the design and analysis of a novel variable inductor (VID) based VCO solution to the frequency tuning range (TR) limitation of the IEEE 802.11ad compliant radio systems. The IEEE 802.11ad standard has drawn strong attention from the industry as the next generation affordable multi-gigabit speed wireless communication standard. Prepared for the global market, IEEE 802.11ad compliant systems are required to cover a broad 8 GHz TR centered on 60 GHz. This wide TR at V band imposes significant challenge to the VCO design in radio transceivers, and makes the TR of the integrated VCO a major bottleneck to the successful commercialization of many IEEE 802.11ad compliant radio systems today. As an effort to solve the current TR problem for the IEEE 802.11ad compliant radio systems, 2 VCOs designs based on this novel VID-based solution and a conventional Colpitts-Clapp VCO design are presented in this thesis report. The novel VCOs integrate a VID into the differential Colpitts configuration to create a feasible solution to the aforementioned TR problem. The VID in the VCO tank eliminates the base node varactors and their fixed parasitic capacitance that degrades TR in conventional VCO designs, while the differential Colpitts configuration provides advantageous performance at mm-wave frequencies and high output power for real-world applications. Also, a fundamental 30 GHz Colpitts-Clapp VCO was developed in conjunction with the other 2 VCOs for comparison purposes. One of the 2 VID-based VCO designs is a fundamental 30 GHz VID-based Colpitts VCO that covers 17% TR for proof of concept to the novel topology. Another is an IEEE 802.11ad compliant 60 GHz VCO chain consists of the 30 GHz VID-based Colpitts VCO and a frequency doubler covering 17% TR with 3 dBm output power and -115.7 dBc/Hz phase noise at 10 MHz offset. The conventional Colpitts-Clapp VCO is used to compare with the other 2 VID-based VCOs. As the measurement results indicate, this VID-based VCO topology provides a viable solution to overcome the TR bottleneck in the current IEEE 802.11ad compliant VCO development. All 3 VCOs are fabricated using a 130 nm SiGe BiCMOS process. / Thesis (Master, Electrical & Computer Engineering) -- Queen's University, 2014-01-23 13:40:31.258