Le travail présenté dans ce mémoire traite de l’étude comportementale, de la conception et de la validation d’une nouvelle architecture, basée sur le couplage d’O.C.T différentiels, appliquée à la commande électronique de l’orientation du diagramme de rayonnement d’un réseau d’antennes linéaire. Après avoir optimisé la structure de l’O.C.T différentiel, qui constitue le corps du circuit de commande, selon une méthode graphique qui visualise les différentes contraintes imposées par le système afin de minimiser son bruit de phase et sa consommation, l’O.C.T à sorties différentielles a été réalisé en technologie NXP BiCMOS SiGe 0,25 μm puis mesuré en boîtier. Etant donné que la direction de rayonnement d’une antenne réseau dépend de la valeur du déphasage imposé entre les signaux envoyés sur deux antennes adjacentes, les équations théoriques modélisant deux O.C.T couplés et permettant d’extraire les amplitudes et le déphasage entre les différents signaux ont été décrites. La dernière étape a alors consisté en la réalisation de deux réseaux constitués respectivement de deux et de quatre O.C.T couplés au moyen d’une résistance puis d’un transistor MOS fonctionnant en zone ohmique. L’approche de couplage proposée a été validée en se basant sur les résultats de mesures effectués. De plus, l’impact de l’utilisation de structures différentielles sur la plage de déphasage obtenue et donc sur le dépointage réalisé a également été présenté ce qui nous a permis de conclure sur l’efficacité du circuit de commande proposé. / The work presented in this thesis deals with the study, design, and validation of a new architecture based on the coupling of differential voltage controlled oscillators (VCO) applied to the beamsteering of a linear antenna array. After optimizing the differential VCO structure, with a graphical optimization approach while satisfying design constraints imposed, in order to minimize the phase noise and power consumption, the differential VCO was realized in NXP BiCMOS SiGe 0.25 µm process and then measured. Since the radiation direction of an antenna array depends on the phase difference imposed between the two signals on adjacent antennas, the theoretical equations modeling two coupled VCOs, and allowing the extraction of the amplitude and phase difference between the outputs signals have been presented. The last step was the realization of two arrays consisting respectively of two and four VCOs coupled through a resistor and a MOS transistor operating in the triode region. The proposed coupling approach is validated based on the obtained measurement results. Furthermore, the impact of the use of differential structures on the phase shift range obtained and thus on the beam-scanning range achieved was also presented allowing to conclude on the efficiency of the proposed architecture.

This thesis introduces, for the first time, a novel 4-bit, metal-oxide-metal (MOM) digital capacitor switching array (MOMDCSA) which has been implemented into a wideband CMOS voltage controlled oscillator (VCO) for 5 GHz WiMAX/WLAN applications. The proposed MOMDCSA is added both in series and parallel to nMOS varactors. For further gain linearity, a wider tuning range and minor phase noise variations, this varactor bank is connected in parallel to four nMOS varactor pairs, each of which is biased at a different voltage. Thus, VCO tuning gain reduces and optimal phase noise variation is obtained across a wide range of frequencies. Based on this premise, a wideband VCO is achieved with low phase noise variation of less than 4.7 dBc/Hz. The proposed VCO has been designed using UMC 130 nm CMOS technology. It operates from 3.45 GHz to 6.23 GHz, with a phase noise of -133.80 dBc/Hz at a 1 MHz offset, a figure of merit (FoM) of -203.5 dBc/Hz. A novel microstrip low-phase noise oscillator is based on a left-handed (LH) metamaterial bandpass filter which is embedded in the feedback loop of the oscillator. The oscillator is designed at a complex quality factor Qsc peak frequency, to achieve excellent phase noise performance. At a centre frequency of 2.05 GHz, the reported oscillator demonstrates, experimentally, a phase noise of -126.7 dBc/Hz at a 100 kHz frequency offset and a FoM of -207.2 dBc/Hz at a 1 MHz frequency offset. The increasing demands have been placed on the electromagnetic compatibility performance of VCO devices is crucial. Therefore, this thesis extends the potential of highly flexible and conductive graphene laminate to the application of electromagnetic interference (EMI) shielding. Graphene nanoflake-based conductive ink is printed on paper, and then it is compressed to form graphene laminate with a conductivity of 0.43×105 S/m. Shielding effectiveness is experimentally measured at above 32 dB as being between 12GHz and 18GHz, even though the thickness of the graphene laminate is only 7.7µm. This result demonstrates that graphene has great potential for offering lightweight, low-cost, flexible and environmentally friendly shielding materials which can be extended to offering required shielding from electromagnetic interference (EMI), not only for VCO phase noise optimisation, but also for sensitive electronic devices.

This thesis describes GSM communication, the method of its jamming and design of a jammer for this band. This document is mainly focused on design of the jammer with the variable bandwidth of jamming and the variable level of output power. Requested parameters of jamming are set by a control panel with a LCD display. In this document there is a detailed description of each function block and connection between them. At the end of this thesis there are released measured results of designed jammer.

Since the heyday of analogue synthesizers in the 70's, they have largely been replaced by digital hardware and software synthesizers. However, in recent years, there has been a revival in analogue designs, possibly due to its ``warmer" sound. This projects aims to take part of this renewal by building a simple analogue synth design with the most basic modules (e.g. oscillators, filters, mixers, amplifier), accompanied by a step sequencer for programming melodies. This will be done by designing circuits and implementing them on breadboards. The circuits were designed with inspiration from various online resources, along with theoretical analysis and simulation software for complex circuitry. The result is a fully functional synthesizer with four sawtooth oscillators. The only modules missing from the initial design are battery support and a line out output for recording the output of the synthesizer. The pitch specification was met as the oscillator did not differ from the expected frequency by more than $\pm$15 cents (hundredths of a semitone), for a range of five octaves. Some possible improvements include better step sequencer user friendliness by installing a display to indicate the notes, more robustness by implementing the synth on a circuit board instead of breadboard. Some improvements can be made for the synth. For example, a display for the step sequencer would facilitate melody programming. Moreover, implementing the synth on a circuit board instead of breadboards would greatly improve robustness and reduce the risk of sound disruptions.

No description available.

No description available.

The advent of high-fT silicon CMOS/BiCMOS technologies has led to a dramatic upsurge in the research and development of radio and microwave frequency integrated circuits (ICs) in silicon. The integration of silicon-germanium heterojunction bipolar transistors (SiGe HBTs) into established "digital" CMOS processes has provided analog performance in silicon that is not only competitive with III-V compound-semiconductor technologies, but is also potentially lower in cost. Combined with improvements in silicon on-chip passives, such as high-Q metal-insulator-metal (MIM) capacitors and monolithic spiral inductors, these advanced RF CMOS and SiGe BiCMOS technologies have enabled complete silicon-based RF integrated circuit (RFIC) solutions for emerging wireless communication standards; indeed, both the analog and digital functionalities of an entire wireless system can now be combined in a single IC, also known as a wireless "system-on-a-chip" (SoC). This approach offers a number of potential benefits over multi-chip solutions, such as reductions of parasitics, size, power consumption, and bill-of-materials; however, a number of critical challenges must be considered in the integration of such SoC solutions. The focus of this research is the application of SiGe BiCMOS technology to on-going challenges in the development of receiver components for high speed wireless data networks. The research seeks to drive SoC integration by investigating circuit topologies that eliminate the need for off-chip components and are amenable to complete on-chip integration. The first part of this dissertation presents the design, fabrication, and measurement of a 5--6GHz sub-harmonic direct-conversion-receiver (DCR) front-end, implemented in the IBM 0.5um 5HP SiGe BiCMOS process. The design consists of a fully-differential low-noise amplifier (LNA), a set of quadrature (I and Q)x~2 sub-harmonic mixers, and an LO conditioning chain. The front-end design provides a means to address performance limitations of the DCR architecture (such as DC-offsets, second-order distortion, and quadrature phase and amplitude imbalances) while enabling the investigation of high-frequency IC design complications, such as package parasitics and limited on-chip isolation. The receiver front-end has a measured conversion gain of ~18dB, an input second-order intercept point of +17.5dBm, and a noise figure of 7.2dB. The quadrature phase balance at the sub-harmonic mixer IF outputs was measured in the presence of digital switching noise; 90<degree> balance was achieved, over a specific range of LO power levels, with a square wave noise signal injected onto the mixer DC supply rails. The susceptibility of receiver I/Q balance to mixed-signal effects in a SoC environment motivates the second part of this dissertation --- the design of a phase and amplitude tunable, quadrature voltage-controlled oscillator (QVCO) for the on-chip synthesis of quadrature signals. The QVCO design, implemented in the Freescale (formerly Motorola) 0.18um SiGe:C RFBiCMOS process, uses two identical, differential LC-tank VCOs connected such that the two oscillator outputs lock in quadrature to the same frequency. The QVCO designs proposed in this work provide the additional feature of phase-tunability, i.e. the relative phase balance between the quadrature outputs can be adjusted dynamically, offering a simulated tuning range of ~90<degree>+/-10â ¹degree> in addition, a variable-gain buffer/amplifier circuit that provides amplitude tunability is introduced. One potential application of the QVCO is in a self-correcting RF receiver architecture, which, using the phase and amplitude tunability of the QVCO, could dynamically adjust the IF output quadrature phase and amplitude balance, in near real-time, in the analog-domain. The need for high-quality inductors in both the DCR and QVCO designs motivates the third aspect of this dissertation --- the characterization and modeling of on-chip spiral inductors with patterned ground shields, which are placed between the inductor coil and the underlying substrate in order to improve the inductor quality factor (Q). The shield prevents the coupling of energy away from the inductor spiral to the typically lossy Si substrate, while the patterning disrupts the flow of induced image currents within the shield. The experimental effort includes the fabrication and testing of a range of inductors with different values, and different types of patterned ground shields in different materials. Two-port measurements show a ~50% improvement in peak-Q and a ~20% degradation in self-resonant frequency for inductors with shields. From the measured results, a scalable lumped element model is developed for the rapid simulation of spiral inductors with and without patterned ground shields. The knowledge gained from this work can be combined and applied to a range of future RF/wireless SoC applications. The designs developed in this dissertation can be ported to other technologies (e.g. RF CMOS) and scaled to other frequency ranges (e.g. 24GHz ISM band) to provide solutions for emerging applications that require low-cost, low-power RF/microwave circuit implementations. / Ph. D.

Advances in wireless technology have recently led to the potential for higher data rates and greater functionality. Wireless home and business networks and 3G and 4G cellular phone systems are promising technologies striving for market acceptance, requiring low-cost, low-power, and compact solutions. One approach to meet these demands is system-on-a-chip (SoC) integration, where RF/analog and digital circuitry reside on the same chip, creating a mixed-signal environment. Concurrently, there is tremendous incentive to utilize Si-based technologies to leverage existing fabrication and design infrastructure and the corresponding economies of scale. While the SoC approach is attractive, it presents major challenges for circuit designers, particularly in the design of monolithic voltage controlled oscillators (VCOs). VCOs are important components in the up or downconversion of RF signals in wireless transceivers. VCOs must have very low phase noise and spurious emissions, and be extremely power efficient to meet system requirements. To meet these specifications, VCOs require high-quality factor (Q) tank circuits and reduction of noise from active devices; however, the lack of high-quality monolithic inductors, along with low noise transistors in traditional Si technologies, has been a limiting factor. This thesis presents the design, characterization, and comparison of three monolithic 3-4 GHz VCOs and an integrated 5-6 GHz VCO with tunable polyphase outputs. Each VCO is designed around a differential -G_{M} core with an LC tank circuit. The circuits exploit two Si-based device technologies: Silicon Germanium (SiGe) Heterojunction Bipolar Transistors (HBTs) for a cross-coupled collectors circuit and Graded-Channel MOS (GC-MOS) transistors for a complementary (CMOS) implementation. The circuits were fabricated using the Motorola 0.4 μm CDR1 SiGe BiCMOS process, which consists of four interconnected metal layers and a thick copper (10 μm) metal bump layer for improved inductive components. The VCO implementations are targeted to meet the stringent phase noise specifications for the GSM/EGSM 3G cellular standard. The specifications state that the VCO output cannot exceed -162 dBc/Hz sideband noise at 20 MHz offset from the carrier. Simultaneously, oscillators must be designed to address other system level effects, such as feed-through of the local oscillator (LO). LO feed-through directly results in self-mixing in direct conversion receivers, which gives rise to unwanted corrupting DC offsets. Therefore, a system-level strategy is employed to avoid such issues. For example, multiplying the oscillator frequency by two or four times can help avoid self-mixing during downconversion by moving the LO out of the bandwidth of the RF front-end. Meanwhile, direct conversion or low-IF (intermediate frequency) receiver architectures utilize in-phase and quadrature (I/Q) downconversion signal recovery and image rejection. Any imbalance between the I and Q channels can result in an increase in bit-error-rate (BER) and/or decrease in the image rejection ratio (IRR). To compensate for such an imbalance, an integrated tunable polyphase filter is implemented with a VCO. Control voltages between the differential I and Q channels can be individually controlled to help compensate for I/Q mismatches. This thesis includes an introduction to design flow and layout strategies for oscillator implementations. A detailed comparison of the advantages and disadvantages of the SiGe HBTs and GC-MOS device in 3-4 GHz VCOs is presented. In addition, an overview of full-wave electromagnetic characterization of differential dual inductors is given. The oscillators are characterized for tuning range, output power, and phase noise. Finally, new measurement techniques for the 5-6 GHz VCO with a tunable polyphase filter are explored. A comparison between the time and frequency approaches is also offered. / Master of Science

Made available in DSpace on 2014-12-17T14:55:40Z (GMT). No. of bitstreams: 1 FranciscoAB.pdf: 846082 bytes, checksum: d9718796dd9ac807f8f053e7d371d2bb (MD5) Previous issue date: 2009-09-03 / Conselho Nacional de Desenvolvimento Cient?fico e Tecnol?gico / This work presents an wideband ring VCO for cognitive radio five-port based receivers. A three-stage differential topology using transmission gate was adopted in order to maintain wide and linear tuning range and a low phase-noise. Monte-Carlo analysis were performed for phase-shift response of individual stages, which is an important figure of merit in five-port works. It was observed a fairly linear correlation between control voltage and oscillation frequency in the range between 200 MHz and 1800 MHz. The VCO was preliminarily designed for IBM 130nm CMOS technology / Este trabalho apresenta um VCO anel banda-larga para ser utilizado em receptores para R?dio Cognitivo baseados no correlator a cinco portas. Uma arquitetura diferencial de tr?s est?gios com porta de transmiss?o ? utilizada como forma de manter uma sintonia linear em larga faixa de frequ?ncias, bem como, um baixo ru?do de fase. An?lises de Monte-Carlo foram feita para avaliar as varia??es de fase em cada est?gio, o que constitui uma figura de m?rito importante em receptores baseados no correlator de cinco portas. Observou-se correspond?ncia razoavelmente linear entre tens?o de controle e freq??ncia de oscila??o na faixa compreendida entre 200 MHz e 1800 MHz. O VCO foi preliminarmente projetado para tecnologia CMOS IBM de 130 nan?metros

This thesis discusses about using the worldwide satellite system GPS for time and frequency synchronization. This thesis presents study about basic principles of the GPS system, its segments and ways of using this system. Some GPS receivers suitable for receiving the time marks (pulses) used for time synchronization are described. Thesis contents designing of the circuit that will receive time marks and it will digitalize and record external signal and send it with precision time information to PC for displaying and post processing. Thesis also discusses about both hardware and software development of the synchronization module and software used in PC.