No description available.

This dissertation presents the design and implementation of circuits and transceivers in CMOS technology to enable many new millimeter-wave applications. A simple approach is presented for accurately modeling the millimeter-wave characteristics of transistors that are not fully captured by contemporary parasitic extraction techniques. Next, the integration of a low-power 60-GHz CMOS on-off keying (OOK) receiver in 90-nm CMOS for use in multi-gigabit per second wireless communications is demonstrated. The use of non-coherent OOK demodulation by a novel demodulator enabled a data throughput of 3.5 Gbps and resulted in the lowest power budget (31pJ/bit) for integrated 60-GHz CMOS OOK receivers at the time of publication. Also presented is the design of a high-power, high-efficiency 45-GHz VCO in 45-nm SOI CMOS. The design is a class-E power amplifier placed in a positive feedback configuration. This circuit achieves the highest reported output power (8.2 dBm) and efficiency (15.64%) to date for monolithic silicon-based millimeter-wave VCOs. Results are provided for the standalone VCO as well as after packaging in a liquid crystal polymer (LCP) substrate. In addition, a high-power high-efficiency (5.2 dBm/6.1%) injection locked oscillator is presented. Finally, the design of a 2-channel 45-GHz vector modulator in 45-nm SOI CMOS for LINC transmitters is presented. A zero-power passive IQ generation network and a low-power Gilbert cell modulator are used to enable continuous 360° vector generation. The IC is packaged with a Wilkinson power combiner on LCP and driven by external DACs to demonstrate the first ever 16-QAM generated by outphasing modulation in CMOS in the Q-band.

Wireless communication is witnessing tremendous growth with the proliferation of various standards covering wide, local, and personal area networks, which operate at different frequency bands. Future wireless terminals will not only need to support multiple standards, but also need to be multi-functional to keep pace with the demands of the consumers. For such an implementation, the local oscillator (LO) turns out to be the bottleneck, which must exhibit frequency agility by generating a very wide range of carrier frequencies in order to access all the specified communication standards. This dissertation presents various design techniques to realize compact low-cost low-power and broadband oscillators in silicon-based technologies. The two most suitable techniques for broadband signal generation: (1) Use of widely tunable active inductor, and (2) Use of switched resonator have been thoroughly evaluated. A fully reconfigurable active inductor with a widely tunable feedback resistor has been proposed. Using the proposed tunable active inductor in a VCO generates frequency tuning ranges higher than 100%, and helps achieve the highest PFTN Figure-of-Merit among Si-based active inductor VCOs reported in literature till date. The large-signal non-linearity of the active inductor has been utilized to develop the first reported broadband harmonic active inductor-based VCO. The degradation of phase noise due to active inductors is partially solved by a noise optimization guideline for active inductors. Utilizing the low saturation voltage of HBT technologies and high-Q short line inductors seems to be very useful to reduce power consumption of cross-coupled VCOs while achieving low phase noise performance simultaneously.

In this thesis, we present a new continuously variable high frequency standing wave oscillator and demonstrate its use in generating the phase locked clock signal of a digital IC. The ring based standing wave resonant oscillator is implemented with a plurality of wires connected in a mobius configuration, with a cross coupled inverter pair connected across the wires. The oscillation frequency can be modulated by coarse and fine tuning. Coarse modification is achieved by altering the number of wires in the ring that participate in the oscillation, by driving a digital word to a set of passgates which are connected to each wire in the ring. Fine tuning of the oscillation frequency is achieved by varying the body bias voltage of both the PMOS transistors in the cross coupled inverter pair which sustains the oscillations in the resonant ring. We validated our PLL design in a 90nm process technology. 3D parasitic RLCs for our oscillator ring were extracted with skin effect accounted for. Our PLL provides a frequency locking range from 6 GHz to 9 GHz, with a center frequency of 7.5 GHz. The oscillator alone consumes about 25 mW of power, and the complete PLL consumes a power of 28.5 mW. The observed jitter of the PLL is 2.56 percent. These numbers are significant improvements over the prior art in standing wave based PLLs.

This work consists of two main parts: i) Design and implementation of a compact current-reusing 2.4GHz direct-modulation transmitter with on-chip automatic tuning; ii) Design and implementation of a novel highly-reconfigurable, continuously tunable, power-adjustable Active-RC filter for multiple standards. The design, analysis, and experimental verification of a proposed self-calibrating, current reused 2.4GHz, direct-modulation transmitter are introduced. A stacked arrangement of the power amplifier/voltage-controlled oscillator is presented along with a novel LC-tank-tuning algorithm with a simple, low-cost, on-chip implementation. To transmit maximum power, the tuning loop ensures the PA's resonant tank is centered around the operating frequency, and the loop requires no ADC, DSP, or external signal generator. This work also details the proposed tuning-loop algorithm and examines the frequency-dependent nonlinear power-detector. The system was implemented in TSMC 0.18[mu]m CMOS, occupies 0.7 mm² (TX) + 0.1 mm² (self tuning), and was measured in a QFN48 package on FR4 PCB. Automatically adjusting the tank-tuning bits within their tuning range results in >4dB increase in output power. With the self-tuning circuit active, the transmitter delivers a measured output power of > 0dBm to a 100-[omega] differential load, and the system consumes 22.9 mA from a 2.2-V supply. A biquad design methodology and a baseband low-pass filter is presented for wireless and wireline applications with reconfigurable frequency response, selectable order (1st/3rd/5th), continuously tunable cutoff frequency (1MHz-20MHz) and adjustable power consumption (3mW-7.5mW). A discrete capacitor array coarsely tunes the low-pass filter, and a novel Continuous Impedance Multiplier (CIM) then finely tunes the filter. Resistive/capacitive networks select between the Chebyshev and Inverse Chebyshev approximation types. Also, a new stability metric for biquads, Minimum Acceptable Phase Margin (MAPM), is presented and discussed in the context of filter compensation and passband ripple considerations. Experimental results yield an IIP3 of 31.3dBm, a THD of -40dB at 447mV[subscript pk, diff] input signal amplitude, and a DR of 71.4dB. The filters tunable range covers frequencies from 1MHz to 20MHz. In Inverse Chebyshev mode, the filter achieves a passband group delay variation less than ±2:5%. The design is fabricated in 0.13[mu]m CMOS, occupies 1.53mm², and operates from a 1-V supply.

High-speed serial data links are quickly gaining in popularity and replacing the conventional parallel data links in recent years when the data rate of communication exceeds one gigabits per second. Compared with parallel data links, serial data links are able to achieve higher data rate and longer transfer distance. This dissertation is focused on the design of CMOS integrated phase-locked loops (PLLs) and relevant building blocks used in multi-gigabits serial data link transceivers. Firstly, binary phase-locked loops (BPLLs, i.e., PLLs based on binary phase detectors) are modeled and analyzed. The steady-state behavior of BPLLs is derived with combined discrete-time and continuous-time analysis. The jitter performance characteristics of BPLLs are analyzed. Secondly, a 10 Gbps clock and data recovery (CDR) chip for SONET OC- 192, the mainstream standard for optical serial data links, is presented. The CDR is based on a novel referenceless dual-loop half-rate architecture. It includes a binary phase-locked loop based on a quad-level phase detector and a linear frequency-locked loop based on a linear frequency detector. The proposed architecture enables the CDR to achieve large locking range and small jitter generation at the same time. The prototype is implemented in 0.18 μm CMOS technology and consumes 250 mW under 1.8 V supply. The jitter generation is 0.5 ps-rms and 4.8 ps-pp. The jitter peaking and jitter tolerance performance exceeds the specifications defined by SONET OC-192 standard. Thirdly, a fully-differential divide-by-eight injection-locked frequency divider with low power dissipation is presented. The frequency divider consists of a four-stage ring of CML (current mode logic) latches. It has a maximum operating frequency of 18 GHz. The ratio of locking range over center frequency is up to 50%. The prototype chip is implemented in 0.18 μm CMOS technology and consumes 3.6 mW under 1.8 V supply. Lastly, the design and optimization techniques of fully differential charge pumps are discussed. Techniques are proposed to minimize the nonidealities associated with a fully differential charge pump, including differential mismatch, output current variation, low-speed glitches and high-speed glitches. The performance improvement brought by the techniques is verified with simulations of schematics designed in 0.35 μm CMOS technology.

In this dissertation, the development of the first 60 GHz-standard compatible fully integrated 4-channel phase-locked loop (PLL) frequency synthesizer has been presented. The frequency synthesizer features third-order single loop architecture with completely integrated passive loop filter that does not require any additional external passive component. Two possible realizations of fully integrated clock and data recovery (CDR) circuits suitable for 60 GHz-standard compliant base band signal processing have been presented for the first time as well. The two CDRs have been optimized for either high data rate (3.456 Gb/s) or very low power consumption (5 mW) and they both work with a single 1 V supply. The frequency synthesizer is intended to generate a variable LO frequency in a fixed-IF heterodyne transceiver architecture. In such configuration the channel selection is implemented by changing the LO frequency by the required frequency step. This method avoids quadrature 50 GHz up/down-conversion thereby lowering the LO mixer design complexity and simplifying the LO distribution network. The measurement results show the PLL locking correctly on each of the four channels while consuming 60 mW from a 1 V power supply. The worst case phase noise is measured to be -80.1 dBc/Hz at 1 MHz offset from the highest frequency carrier (56.16 GHz). The output spectrum shows a reference spur attenuation of -32 dBc. The high data rate CDR features a maximum operating data rate in excess of 3.456 Gb/s while consuming 30 mW of power. The low power CDR consumes only 5 mW and operates at a maximum data rate of 1.728 Gb/s. Over a 1.5 m 60 GHz wireless link, both CDRs allow 95% reduction of the pulse shaping generated input peak-to-peak jitter from 450 ps down to 50 ps.

No description available.

Cette habilitation à diriger des recherches résume la majeure partie des activités que nous avons menées dans le domaine des systèmes communicants hautes fréquences, et qui nous ont permis d'en explorer l'élément central "synthèse de fréquences", dans ses déclinaisons intégrées sur silicium, véritables lignes directrices de nos travaux. Si la synthèse de fréquences est essentielle, c'est qu'elle permet aux différents standards de communication actuels (WiFi, Bluetooth, ZigBee, ...) et futurs (Wireless-HD, ...) d'exister et de cohabiter, de commuter entre les canaux des différents utilisateurs, et dans certaines techniques d'étalement de spectre, d'assurer des sauts de fréquences ultra rapides. De multiples aspects ont été abordés, dont l'originalité réside dans le croisement des approches analogiques, numériques, mixtes, basses et hautes fréquences, impliquant les niveaux composants, circuits et systèmes, depuis l'optimisation très ciblée de fonctions élémentaires jusqu'à une application de métrologie de bruit de phase totalement atypique car entièrement intégrée et reconfigurable, en passant par la remise en question d'architectures habituelles de synthèse visant à en résoudre certains défauts récurrents. En tout premier lieu, nous avons mené une activité de conception analogique " classique " d'oscillateurs intégrés, que notre participation à un projet européen nous a permis de coupler pour la première fois à des résonateurs à ondes acoustiques de volume (BAW) très sélectifs dans une approche SoC "above-IC" à 5 GHz. Ils ont affiché des performances en bruit de phase à l'état de l'art au moment de leur publication. À côté de cela, nous avons développé des activités autour de la boucle à verrouillage de phase (PLL), fonction complexe standard des synthèses de fréquences. Avec elles, nous avons pu mettre en oeuvre des techniques de conception originales dans la numérisation haute fréquence des fonctions de la boucle, diviseurs, comparateurs phase/fréquence et filt res, ce qui nous a permis de dépasser certaines limitations au regard des technologies standards utilisées, en termes de chemins critiques, de parasites et de fréquences de fonctionnement notamment. En nous intéressant à la numérisation du dernier bloc de la PLL, l'oscillateur contrôlé en tension (VCO), nous nous sommes tournés vers le synthétiseur de fréquences digital direct (DDS). C'est avec cette fonction, dont le domaine d'application se révéla bien plus large que le seul oscillateur numérique (NCO), que nous avons pu apporter les solutions les plus singulières, voire les plus osées, en totale rupture avec les habitudes du domaine basse fréquence dont elle est issue. Nous avons ainsi été les premiers à proposer une architecture basse consommation de plusieurs milliers de transistors et fonctionnant au-delà de la gamme RF (6 GHz) sur une technologie pourtant grand public. Un brevet nous a également permis de mettre en valeur un fonctionnement spécial du DDS, capable de lui faire générer facilement des impulsions ultra-large bande (UWB). Dans une dernière partie, nous avons abordé les systèmes de mesure sur puce, et en particulier la mesure intégrée de bruit de phase, paramètre dont la minimisation est essentielle à la qualité des systèmes communicants. Nous avons montré qu'il était possible de concevoir sur une technologie courante des fonctions analogiques d'instrumentation dont la contribution minime en bruit a pu permettre la création d'un banc de mesure de bruit de phase reconfigurable totalement intégré. Les déclinaisons de ce banc, décrites dans un brevet, le rendent capable aussi bien de mesurer le bruit de phase de sources de fréquences que celui résiduel de quadripôles. Nul doute que les micro et nano systèmes hétérogènes multiphysiques du futur sauront tirer bénéfice de tels bancs de mesure miniatures intégrés, autorisant un traitement du signal des plus fidèle car effectué "au plus proche" des différents capteurs à interroger. Notre contribution s' est toujours voulue volontairement appliquée, en gardant à l'esprit certaines notions élémentaires telles que le coût et la consommation raisonnés des techniques et technologies mises en oeuvre, que la quête de l'innovation et de l'excellence doit malgré tout motiver, mais que le Graal de la performance ultime peut facilement faire oublier.

Les travaux de thèse présentés se situent dans le contexte de la conception de circuits intégrés en technologie CMOS avancée pour des applications radiofréquence à très faible consommation de puissance. Les circuits sont conçus à travers deux concepts. Le premier est l'utilisation du coefficient d'inversion qui permet de normaliser le transistor en fonction de sa taille et de sa technologie, ceci permet une analyse rapide pour différentes performances visées ou différentes technologies. La deuxième approche est d'utiliser un facteur de mérite pour trouver la polarisation la plus adéquate d'un circuit en fonction de ses performances. Ces deux principes ont été utilisés pour définir des méthodes de conception efficaces pour deux blocs radiofréquence : l'amplificateur faible bruit et l'oscillateur. / Thesis work are presented in the context of the integrated circuits design in advanced CMOS technology for ultra low power RF applications. The circuits are designed around two concepts. The first is the use of the inversion coefficient to normalize the transistor as a function of its size and its technology, this allows a quick analysis for different performances or different technologies. The second approach is to use a figure of merit to find the most appropriate polarization of a circuit based on its performance. These two principles were used to define effective design methods for two RF blocks: low noise amplifier and oscillator.