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Målet med examensarbetet har varit att ta fram teoretiskt underlag och en beräkningsmodell. Detta ska beskriva hur kabeltyp, kabellängd, kabelarea samt effektfaktor påverkar spänningsfallet över ett 400 Hz ledningssystem. Mätningar har utförts på två olika kablar som används i det aktuella systemet. En av kablarna var symm­et­riskt uppbyggd med 7 ledare, där respektive fas bestod av två ledare förskjutna 180° från varandra runt nolledaren. För att åstadkomma 115/200V 400 Hz, användes en 90 kVA frekvensomformare. Belastningen som användes var en resistiv, induktiv samt en kapacitiv belastning. Med den resistiva belastningen justerades effekten för att ställa in den effektfaktor som önskades under mätningarna. Detta var inte möjligt med den induktiva eller den kapacitiva belastningen, då de inte kunde regleras steglöst.   Beräkningsmodellen jämfördes sedan med mätningarna av spänningsfallet. Den visade sig ge en bra uppskattning av de uppmätta värdena för att kunna användas i Saabs fortsatta arbete. Vidare ges förslag på hur de distorsioner som uppstår, i samband med komplexa laster, kan minskas. Detta för att klara de standardiserade mått på elkvaliteten som ställs i de gällande standarderna MIL-STD-704E och ISO 6858-1982 (E). Beräkningsmodellen och dess beräkningar presenteras dock inte i denna rapport, då det av Saab AB är sekretessbelagda. / The goal with this bachelor thesis has been to present theoretical material and a calculation model. This is to be used to explain how cable type, cable length, cable area affects the voltage drop in a 400 Hz power system. Measurements have been made on two different cables that are being used in the current system. One of the cables was built symmetrically built with 7-conduktors, where each phase consisted of two conductors shifted 180° from each other around the neutral conductor. To establish the system voltage 115/200 V 400 Hz, a 90 kVA frequency converter was used. The load that was used under the measurements was a resistive, inductive and a capacitive load-equipment. With the resistive load active power is adjusted to obtain the proper power factor for different measurements. This was not an option with the inductive or the capacitive load-equipment since they could not be regulated with a rheostat as the resistive load. The calculation model was compared with the measured results of the voltage drop. It was proven that it approximated the voltage drop good enough to be used in Saabs future work. Furthermore, suggestions are made of how to minimize the distortions that are developed by complex loads, to clear the demands on power quality presented by the standards MIL-STD-704E and ISO 6858-1982 (E).

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Kraven på ett driftsäkert elnät ökar hela tiden i takt med att elanvändning blir allt viktigare i dagens samhälle. Luftledningar byts ut med markkabel och möjlighet till reservmatningar samt bra elkvalitet är av hög prioritering. Skicket på elnätets utrustning försämras med åren och kommer med tiden behöva bytas ut. Med uppdrag från Uddevalla Energi AB har siffror tagits fram berörande spänningsfall, kapacitiv jordfelsström och belastningar vid normaldrift och reservmatning, samt ålder och typ på kablar i Uddevalla citys mellanspänningsnät. Den här rapporten presenterar dessa resultat och ger några förslag på ändringar om så krävs. Även en del om planerade framtida utbyggnationer tas upp och hur dessa påverkar nätet. För att få fram resultaten används Uddevalla Energis program för nätberäkning, "DpPower". Beräkningarna visade att vid normaldrift var alla värden godkända enligt tumregler som Uddevalla Energi följer. Vid reservmatning däremot var vissa linjer överbelastade, analysen visar dock tillgängliga lösningar. Ålder och status på kablar i nätet varierar stort vilket gör det svårt att specificera hur ombyggnationer ska ske. Hänsyn bör istället tas till överbelastningar. / The demand of reliable power distribution is increasing as the usage of power is increasing in the society of today. Overhead lines are replaced by underground cables, availability to reserve power supply and power quality is of high priority. The condition of the equipment deteriorates over the years and will eventually have to be replaced. By request from Uddevalla Energi, values have been provided concerning voltage drop, capacitive ground fault current and loads during normal operation and standby power supply. The types and ages of cables in Uddevalla City’s high-voltage network has also been looked at. This report presents these results and gives some suggestions for modifications if required. Planned future deployments are looked over and how these may affect the network. To obtain these results the network calculating program "DpPower" was used. The calculations presented shows that in normal operation all values are approved within the company standards that Uddevalla Energi follows. For the reserve supply however, some lines are overloaded. The analysis shows possible solutions for these issues. Age and status of cables in the network varies widely, making it difficult to specify how redevelopments should take place. Instead the overloads should be given more consideration.

The superior characteristics of silicon carbide, compared with silicon, have suggested considering this material for the next generation of power semiconductor devices. Among the different power switches, the bipolar junction transistor (BJT) can provide a very low forward voltage drop, a high current capability and a fast switching speed. However, in order to compete on the market, it is crucial to a have high current gain and a breakdown voltage close to ideal. Moreover, the absence of conductivity modulation and long-term stability has to be solved. In this thesis, these topics are investigated comparing simulations and measurements. Initially, an efficient etched JTE has been simulated and fabricated. In agreement with the simulations, the fabricated diodes exhibit the highest BV of around 4.3 kV when a two-zone JTE is implemented. Furthermore, the simulations and measurements demonstrate a good agreement between the electric field distribution inside the device and the optical luminescence measured at breakdown. Additionally, an accurate model to simulate the forward characteristics of 4H-SiC BJTs is presented. In order to validate the model, the simulated current gains are compared with measurements at different temperatures and different base-emitter geometries. Moreover, the simulations and measurements of the on-resistance are compared at different base currents and different temperatures. This comparison, coupled with a detailed analysis of the carrier concentration inside the BJT, indicates that internal forward biasing of the base-collector junction limits the BJT to operate at high current density and low forward voltage drop simultaneously. In agreement with the measurements, a design with a highly-doped extrinsic base is proposed to alleviate this problem. In addition to the static characteristics, the comparison of measured and simulated switching waveforms demonstrates that the SiC BJT can provide fast switching speed when it acts as a unipolar device. This is crucial to have low power losses during transient. Finally, the long-term stability is investigated. It is observed that the electrical stress of the base-emitter diode produces current gain degradation; however, the degradation mechanisms are still unclear. In fact, the analysis of the measured Gummel plot suggests that the reduction of the carrier lifetime in the base-emitter region might be only one of the causes of this degradation. In addition, the current gain degradation due to ionizing radiation is investigated comparing the simulations and measurements. The simulations suggest that the creation of positive charge in the passivation layer can increase the base current; this increase is also observed in the electrical measurements. / QC 20120522

Power supply noise has become a critical issue for low power and high performance circuit design in recent years. The rapid scaling of the CMOS process has pushed the limit further and further in building low-cost and increasingly complex digital VLSI systems. Continued technology scaling has contributed to significant improvements in performance, increases in transistor density, and reductions in power consumption. However, smaller feature sizes, higher operation frequencies, and supply voltage reduction make current and future VLSI systems more vulnerable to power supply noise. Therefore, there is a strong demand for strategies to prevent problems caused by power supply noise. Design challenges exist in different design phases to reduce power supply noise. In terms of physical design, careful power distribution design is required, since it directly determines the quality of power stability and the timing integrity. In addition, power management, such as switching mode of the power gating technique, is another major challenge during the circuit design phase. A bad power gating switching strategy may draw an excessive rush current and slow down other active circuitry. After the circuit is implemented, another critical design challenge is to estimate power supply noise. Designers need to be aware of the voltage drop in order to enhance the power distribution network without wasting unnecessary design resources. However, estimating power supply noise is usually difficult, especially finding the circuit activity which induces the maximum supply noise. Blind search may be very time consuming and not effective. At post-silicon test, detecting power supply noise within a chip is also challenging. The visibility of supply noise is low since there is no trivial method to measure it. However, the supply noise measurement result on silicon is critical to debug and to characterize the chip. This dissertation focuses on novel circuit designs and design methodologies to prevent problems resulted from power supply noise in different design phases. First, a supply noise estimation methodology is developed. This methodology systematically searches the circuit activity inducing the maximum voltage drop. Meanwhile, once the circuit activity is found, it is validated through instruction execution. Therefore, the estimated voltage drop is a realistic estimation close to the real phenomenon. Simulation results show that this technique is able to find the circuit activity more efficiently and effectively compared to random simulation. Second, two on-chip power supply noise detectors are designed to improve the visibility of voltage drop during test phase. The first detector facilitates insertion of numerous detectors when there is a need for additional test points, such as a fine-grained power gating design or a circuit with multiple power domains. It focuses on minimizing the area consumption of the existing detector. This detector significantly reduces the area consumption compared to the conventional approach without losing accuracy due to the area minimization. The major goal of designing the second on-chip detector is to achieve self-calibration under process and temperature variations. Simulation and silicon measurement results demonstrate the capability of self-calibration regardless these variations. Lastly, a robust power gating reactivation technique is designed. This reactivation scheme utilizes the on-chip detector presented in this dissertation to monitor power supply noise in real time. It takes a dynamic approach to control the wakeup sequence according to the ambient voltage level. Simulation results demonstrate the ability to prevent the excessive voltage drop while the ambient active circuitry induces a high voltage drop during the wakeup phase. As a result, the fixed design resource, which is used to prevent the voltage emergency, can potentially be reduced by utilizing the dynamic reactivation scheme. / text

Made available in DSpace on 2014-06-11T19:30:51Z (GMT). No. of bitstreams: 0 Previous issue date: 2006-11-23Bitstream added on 2014-06-13T21:01:26Z : No. of bitstreams: 1 ochoapizzali_lf_dr_ilha.pdf: 1694440 bytes, checksum: e159d13557d3d0a89139b7565f849244 (MD5) / Conselho Nacional de Desenvolvimento Científico e Tecnológico (CNPq) / Coordenação de Aperfeiçoamento de Pessoal de Nível Superior (CAPES) / Alban / Fundação de Ensino Pesquisa e Extensão de Ilha Solteira (FEPISA) / Neste trabalho, é apresentada uma análise em regime permanente que considera a avaliação de impactos técnicos tais como perdas elétricas, queda de tensão e níveis de curto-circuito, entre outros; utilizando dados de demanda e geração variáveis no tempo ao longo de um horizonte determinado. O objetivo é encontrar um conjunto de arranjos da GD (configurações) que levem ao melhor desempenho da rede de distribuição analisada, minimizando ou maximizando cada aspecto técnico segundo o interesse da empresa de distribuição. Dada a natureza combinatória deste problema, que requer uma ferramenta de otimização capaz de manipular múltiplos objetivos, os impactos técnicos serão avaliados simultaneamente utilizando uma metodologia baseada no conceito do Non-dominated Sorting Genetic Algorithm (NSGA), conduzindo a soluções mais reais e diversificadas para a tomada de decisões, conhecidas como soluções ótimas de Pareto. / In this work a steady-state analysis considering the assessment of technical impacts such as losses, voltage drop and short-circuit levels, among others; utilizing time-variant loads and generation within a specified horizon. The objective is to find a set of configurations that lead to the best performance of the distribution network under analysis, minimizing or maximizing each technical aspect according to the utility's concerns. Given the combinatorial nature of this problem, which requires an optimization tool able to handle multiple objectives, technical impacts will be assessed simultaneously through a methodology based on the non-dominated sorting genetic algorithm (NSGA). This approach leads to a more realistic and diversified set of solutions for taking decisions, known as Pareto-optimal solutions.

Orientador: Antonio Padilha Feltrin / Banca: Rubén Augusto Romero Lázaro / Banca: Dionízio Paschoareli Júnior / Banca: Gareth Harrison / Banca: Carmen Lucia Tancredo Borges / Resumo: Neste trabalho, é apresentada uma análise em regime permanente que considera a avaliação de impactos técnicos tais como perdas elétricas, queda de tensão e níveis de curto-circuito, entre outros; utilizando dados de demanda e geração variáveis no tempo ao longo de um horizonte determinado. O objetivo é encontrar um conjunto de arranjos da GD (configurações) que levem ao melhor desempenho da rede de distribuição analisada, minimizando ou maximizando cada aspecto técnico segundo o interesse da empresa de distribuição. Dada a natureza combinatória deste problema, que requer uma ferramenta de otimização capaz de manipular múltiplos objetivos, os impactos técnicos serão avaliados simultaneamente utilizando uma metodologia baseada no conceito do Non-dominated Sorting Genetic Algorithm (NSGA), conduzindo a soluções mais reais e diversificadas para a tomada de decisões, conhecidas como soluções ótimas de Pareto. / Abstract: In this work a steady-state analysis considering the assessment of technical impacts such as losses, voltage drop and short-circuit levels, among others; utilizing time-variant loads and generation within a specified horizon. The objective is to find a set of configurations that lead to the best performance of the distribution network under analysis, minimizing or maximizing each technical aspect according to the utility's concerns. Given the combinatorial nature of this problem, which requires an optimization tool able to handle multiple objectives, technical impacts will be assessed simultaneously through a methodology based on the non-dominated sorting genetic algorithm (NSGA). This approach leads to a more realistic and diversified set of solutions for taking decisions, known as Pareto-optimal solutions. / Doutor

Silicon carbide bipolar junction transistors (BJTs) are attractive power switching devices because of the unique material properties of SiC with high breakdown electric field, high thermal conductivity and high saturated drift velocity of electrons. The SiC BJT has potential for very low specific on-resistances and this together with high temperature operation makes it very suitable for applications with high power densities. For SiC BJTs the common emitter current gain (β), the specific on-resistance (RSP_ON), and the breakdown voltage are important to optimize for competition with silicon based power devices. In this thesis, power SiC BJTs with high current gain β ≈ 60 , low on-resistance RSP_ON ≈ 5 mΩcm2, and high breakdown voltage BVCEO ≈ 1200 V have been demonstrated. The 1200 V SiC BJT that has been demonstrated has about 80 % lower on-state power losses compared to a typical 1200 V Si IGBT chip. A continuous epitaxial growth of the base-emitter layers has been used to reduce interface defects and thus improve the current gain. A significant influence of surface recombination on the current gain was identified by comparing the experiments with device simulations. In order to reduce the surface recombination, different passivation layers were investigated in SiC BJTs, and thermal oxidation in N2O ambient was identified as an efficient passivation method to increase the current gain. To obtain a low contact resistance, especially to the p-type base contact, is one critical issue to fabricate SiC power BJTs with low on-resistance. Low temperature anneal (~ 800 oC) of a p-type Ni/Ti/Al contact on 4H-SiC has been demonstrated. The contact resistivity on the ion implanted base region of the BJT was 1.3 × 10-4 Ωcm2 after annealing. The Ni/Ti/Al p-type ohmic contact was adapted to 4H-SiC BJTs fabrication indicating that the base contact plays a role for achieving a low on-resistance of SiC BJTs. To achieve a high breakdown voltage, optimized junction termination is important in a power device. A guard ring assisted Junction Termination Extension (JTE) structure was used to improve the breakdown voltage of the SiC BJTs. The highest breakdown voltage of the fabricated SiC BJTs was obtained for devices with guard ring assisted JTE using the base contact implant step for a simultaneous formation of guard rings. As a new approach to fabricate SiC BJTs, epitaxial regrowth of an extrinsic base layer was demonstrated. SiC BJTs without any ion implantation were successfully demonstrated using epitaxial regrowth of a highly doped p-type region and an etched JTE using the epitaxial base. A maximum current gain of 42 was measured for a 1.8 mm × 1.8 mm BJT with a stable and reproducible open base breakdown voltage of 1800 V. / QC 20100819