Esta dissertação de mestrado apresenta uma metodologia de projeto de filtros de microondas planares passa-faixa tipo patch dual-mode, que associam baixas perdas nos condutores, boa capacidade de potência, rejeição da banda de segunda harmônica e miniaturização. Utilizou-se a ferramenta computacional MATLAB para desenvolver programas de cálculo de dimensões de ressoadores patch single-mode em função da freqüência fundamental e do substrato escolhido, bem como para cálculo da distribuição de campos eletromagnéticos (EM) ao longo destes ressoadores. O simulador EM 3D Momentum/ADS foi utilizado na análise, otimização e simulação do desempenho dos filtros. A metodologia desenvolvida consiste no projeto do ressoador patch single-mode nas geometrias quadrada, triangular e circular, com perturbações tais que resultem na freqüência central e banda de passagem desejadas para o filtro, bem como na miniaturização do mesmo. A metodologia engloba a análise do posicionamento das linhas de entrada e de saída para excitação dos modos desejados e seu acoplamento ao ressoador projetado. Foram propostos três ressoadores patch com topologias originais, modificados pela inserção de fendas, os quais foram aplicados ao projeto, construção e caracterização de cinco filtros. Desses, dois filtros passa-faixa dual-mode de banda mediana utilizam a nova topologia proposta de ressoador patch quadrado. Esses filtros, com dois e com quatro pólos, operam em 2,4 GHz e 2,35 GHz, com banda de passagem fracional de 14% e 9,8%, respectivamente. Outros dois filtros passa-faixa dual-mode de banda estreita, um com dois pólos e outro com quatro pólos, utilizam a topologia original proposta de ressoador patch triangular, com fenda em forma de \"T\" invertido. O filtro com dois pólos opera em 7,8 GHz, com banda de passagem fracional de 4,3% e o filtro de quatro pólos, em 7,5 GHz, com banda de 3,5%. Por fim, o filtro passa-faixa circular banda larga utiliza o ressoador patch circular proposto, que foi modificado para operar como triple-mode, comportamento inédito na literatura internacional enfocando ressoadores patch. Esse filtro triple-mode com três pólos apresenta freqüência central de 2,4 GHz e banda fracional de 29%. Os resultados experimentais validam a aplicação da metodologia, que apresenta grande flexibilidade no projeto de filtros com bandas estreitas, medianas ou largas, com boa rejeição na faixa de segunda harmônica (resultados acima de 13 dB). Conseguem-se leiautes miniaturizados com redução em área maior que 50% e ao mesmo tempo sem dimensões críticas, o que resulta em facilidade de fabricação através de métodos tradicionais de fotogravação em placas de circuito impresso. / This dissertation presents a methodology for the design of microwave planar bandpass filters using dual-mode patch resonators, which have low conductor loss, high power handling, second harmonic band rejection and miniaturization. MatLab software was used to develop routines that can calculate the dimensions of the single-mode patch resonators as a function of their fundamental frequency and of the chosen substrate. Further, these routines are able to calculate the electromagnetic (EM) field patterns across these resonators. Momentum/ADS EM 3D software was used for the analysis, optimization and simulation of the performance of the filters. The developed methodology consists on the design of the single-mode patch resonator in either square, rounded or triangular shape with perturbations that result in the desired filter\'s central frequency and bandwidth, and also in its miniaturization. The methodology involves the positioning of the input and output transmission lines to excite the desired modes and their coupling to the developed resonator. Three patch resonators were proposed with novel topologies that were modified by the insertion of slots, and applied to the design, fabrication, and measurements of five filters. Out of these five filters, two are dualmode medium band filters that use the proposed new topology for the square patch resonator. These filters, with two and four poles, are centered at 2.4 GHz and 2.35 GHz, with fractional bandwidth of 14% and 9.8%, respectively. Other two filters are dual-mode narrowband filters, a two-pole and a four-pole, that use the original topology proposed for the triangular patch resonator with a \"T\"-shaped slot. The two-pole filter is centered at 7.8 GHz with fractional bandwidth of 4.3%, whereas the four-pole filter is centered at 7.5 GHz with 3.5% of bandwidth. The last filter is a broadband circular filter that uses the proposed circular triplemode patch resonator, which is a brand new behavior in the international literature that focus on patch resonators. This triple-mode filter with three poles is centered at 2.4 GHz with fractional bandwidth of 29%. Experimental results validate the methodology, which presents wide filter design flexibility with narrow, medium or broad bands, and good second harmonic rejection (results better than 13 dB). Layouts can be designed with more than 50% of area reduction, and without critical dimensions at the same time, resulting in a simple fabrication that utilizes conventional PCB photopatterning process.

In modern wireless communication and radar systems, filters play an important role in getting a high-quality signal while rejecting spurious and neighboring unwanted signals. The filters with reconfigurable features, such as tunable bandwidths or switchable dual bands, also play a key part both in realizing the compact size of the system and in supporting multi-communication services. The Chapters II-IV of this dissertation show the studies of the filters for microwave communication. Bandpass filters realized in ring resonators with stepped impedance stubs are introduced. The effective locations of resonant frequencies and transmission zeros are analyzed, and harmonic suppression by interdigital-coupled feed lines is discussed. To vary mid-upper and mid-lower passband bandwidths separately, the characteristic impedances of the open-circuited stubs are changed. Simultaneous change of each width of the open-circuited stub results in variable passband bandwidths. Asymmetric stepped-impedance resonators are also used to develop independently controllable dual-band (2.4 and 5.2 GHz) bandpass filters. By extending feed lines, a transmission zero is created, which results in the suppression of the second resonance of 2.4-GHz resonators. To determine the precise transmission zeros, an external quality factor at feeders is fixed while extracting coupling coefficients between the resonators. Two kinds of feed lines, such as hook-type and spiral-type, are developed, and PIN diodes are controlled to achieve four states of switchable dual-band filters. Beam-scanning features of the antennas are very important in the radar systems. Phase shifters using piezoelectric transducers and dielectric leaky-wave antennas using metal strips are studied in the Chapters V-VII of this dissertation. Meandered microstrip lines are used to reduce the size of the phase shifters working up to 10 GHz, and reflection-type phase shifters using piezoelectric transducers are developed. A dielectric film with metal strips fed by an image line with a high dielectric constant is developed to obtain wide and symmetrical beam-steering angle. In short, many techniques are presented for realizing reconfigurable filters and large beam-scan features in this dissertation. The result of this work should have many applications in various wireless communication and radar systems.

This dissertation reports, for the first time, on the electrical coupling of microelectromechanical (MEM) resonators for high order bandpass filter synthesis. Electrical coupling of MEM resonators has a strong potential for extension of the operating frequency of MEM bandpass filters into the ultra high frequency (UHF) range and provides higher tunability and design flexibility compared to the mechanical coupling approach. Various schemes of electrical coupling are presented in this dissertation. Electromechanical models of clamped-clamped beam resonators, and various types of electrically coupled filters are presented. Lower frequency prototypes of electrically coupled filters with operating frequencies in the hundreds of kHz are implemented using micromechanical single crystal silicon clamped-clamped beam resonators. Measurement results are in good agreement with the developed electrical equivalent models of the filters. It is demonstrated that the characteristics of electrically coupled filters can be widely tuned by changing the DC polarization voltages.

In wireless transceiver circuits some of the most prevalent required off-chip components are discrete filters. These components are generally implemented with surface acoustic wave (SAW) or ceramic components. These devices are used in the receiver section for discrimination of incoming radio frequency (RF) signals as well as downconverted intermediate frequency (IF) signals. Presently, with the growing demand for multi-functional wireless consumer devices, the need for full integration of RF and logic circuits in wireless communications systems is becoming increasingly evident. If integrated RF filters with acceptable electrical characteristics could be realized, this might reduce or eliminate the currently required off-chip filters, prospectively decreasing the complexity, size, and cost of future wireless transceiver circuits and systems. The objective of the present research effort is to implement an integrated Q-enhanced LC bandpass filter in a prospective receiver front-end RF amplifier using the passive and active components available in a standard digital complementary metal-oxide semiconductor (CMOS) process. CMOS is the standard design medium for digital circuitry, and with the increased unity gain or transit frequency (fT) values that accompany steadily shrinking CMOS device sizes, the implementation of gigahertz frequency communications circuits in this medium is increasingly feasible. The circuit design specifically investigated in this work introduces a loss-compensated second-order gigahertz range bandpass filter implemented in a 0.18 쭠digital CMOS process provided by National Semiconductor. This filter incorporates a unique design technique that provides improvements in filter linearity through an independently variable bias level shifting method, while also facilitating prospective single-to-differential signal conversion. One distinctive characteristic of the investigated circuit, in comparison to other RF integrated filter work, is the implementation of a novel integrated transformer feedback method that facilitates magnetically coupled loss-restoration and subsequent filter Q-enhancement. Additionally, this loss restoration method is achieved using a single transistor, in contrast to the multi-transistor cross-coupled transconductor Q-enhancement technique commonly implemented in other previous and current integrated RF filter research.

This research focuses on biologically inspired audio signal processing using programmable analog circuitry. This research is inspired by the biology of the human cochlea since biology far outperforms any engineered system at converting audio signals into meaningful electrical signals. The human cochlea efficiently decomposes any sound into the respective frequency components by harnessing the resonance nature of the basilar membrane, essentially forming a bank of bandpass filters. In a similar fashion, this work revolves around developing a filter bank composed of continuous-time, low-power, analog bandpass filters that serve as the core front end to this silicon audio-processing system. Like biology, the individual bandpass filters are tuned to have narrow bandwidths, moderate amounts of resonance, and exponentially spaced center frequencies. This audio front end serves to efficiently convert incoming sounds into information useful to subsequent signal-processing elements, and it does so by performing a frequency decomposition of the waveform with extremely low-power consumption and real-time operation. To overcome mismatch and offsets inherent in CMOS processes, floating-gate transistors are used to precisely tune the time constants in the filters and to allow programmability of analog components.

This dissertation aims to design and implement wireless passive components using domestic integrated passive device (IPD) technology. The research focuses on exploiting novel 3-D structures for various kinds of IPD-based wireless passive components including high-quality and high-efficiency planar transformers, baluns, filters, and combiners to achieve miniature size and high performance. A physical model has been developed for modeling the planar transformers. In this dissertation, a scalable transformer model in integrated passive device technology is further used to correlate with the coupled-line sections of a conventional Marchand balun. This improves the efficiency of the design of planar transformers with equivalent coupled-line parameters such as the coupling factor, and even- and odd-mode characteristic impedances and quality factors. Additionally, the proposed model-based design approach provides effective optimization techniques that incorporate geometrical and material parameters. In addition, a compact transformer-based coupled balun bandpass filter design is proposed based on integrated circuit technology and the equivalent circuit is established. Using a planar transformer with high-density fully symmetrical wiring not only greatly reduces the component size but also provides a superior stopband rejection and selectivity. Finally, by using the spiral-shaped resonators, the dual-band third-order bandpass filter has been implemented on organic substrates. The proposed BPF design is verified to overcome the elements¡¦ parasitic effects, and thus can be miniaturized and optimized with high degree of freedom. The simulation and measurement results have good agreement for the proposed design in this dissertation.

This dissertation studies and implements highly miniaturized bandpass filter designs for wireless System-in-Package (SiP) applications. Based on the coupling matrix synthesis method, the external quality factors and coupling coefficients can be extracted by selecting the proper tapped-line feeding position and coupling spacing in geometrical configuration. Despite their high performance, most conventional microstrip bandpass filter designs require a bulky area for achieving, making them difficult to implement SiP applications. This dissertation first develops a stacked LC resonator and a stacked spiral resonator (SSR) in an embedded passive substrate (EPS) for realizing miniature single- and multi-band bandpass filters. Moreover, multiple transmission zeros created on both sides of each passband provide high stopband roll-off rates. The designed performance and size are comparable to those of low-temperature co-fired ceramic (LTCC) bandpass filters. As another conventional means of implementing RF passive components, the integrated passive device (IPD) process can produce large-value inductors and high-density capacitors, simultaneously. This dissertation fully utilizes the advantages of IPD technology to implement very compact bandpass filter designs with multiple transmission-zero frequencies at stopband by using a high-density wiring planar transformer configuration. Furthermore, due to the fully symmetric geometry, the transformer-coupled bandpass filter can be easily converted into a balun bandpass filter, capable of providing a superior balance performance with a significantly higher common mode rejection ratio (CMRR) level. The electromagnetic (EM) simulation results, as obtained by using Ansys-Ansoft HFSS, agree with the measurement results for all of the proposed designs in this dissertation.

Due to the demand for high‐performance radio frequency (RF) integrated circuit design in the past years, a system‐on‐chip (SoC) that enables integration of analog and digital parts on the same die has become the trend of the microelectronics industry. As a result, a major requirement of the next generation of wireless devices is to support multiple standards in the same chip‐set. This would enable a single device to support multiple peripheral applications and services. Based on the aforementioned, the traditional superheterodyne front‐end architecture is not suitable for such applications as it would require a complete receiver for each standard to be supported. A more attractive alternative is the highintermediate frequency (IF) radio architecture. In this case the signal is digitalized at an intermediate frequency such as 200MHz. As a consequence, the baseband operations, such as down‐conversion and channel filtering, become more power and area efficient in the digital domain. Such architecture releases the specifications for most of the front‐end building blocks, but the linearity and dynamic range of the ADC become the bottlenecks in this system. The requirements of large bandwidth, high frequency and enough resolution make such ADC very difficult to realize. Many ADC architectures were analyzed and Continuous‐Time Bandpass Sigma‐Delta (CT‐BP‐ΣΔ) architecture was found to be the most suitable solution in the high‐IF receiver architecture since they combine oversampling and noise shaping to get fairly high resolution in a limited bandwidth. A major issue in continuous‐time networks is the lack of accuracy due to powervoltage‐ temperature (PVT) tolerances that lead to over 20% pole variations compared to their discrete‐time counterparts. An optimally tuned BP ΣΔ ADC requires correcting for center frequency deviations, excess loop delay, and DAC coefficients. Due to these undesirable effects, a calibration algorithm is necessary to compensate for these variations in order to achieve high SNR requirements as technology shrinks. In this work, a novel linearization technique for a Wideband Low‐Noise Amplifier (LNA) targeted for a frequency range of 3‐7GHz is presented. Post‐layout simulations show NF of 6.3dB, peak S21 of 6.1dB, and peak IIP3 of 21.3dBm, respectively. The power consumption of the LNA is 5.8mA from 2V. Secondly, the design of a CMOS 6th order CT BP‐ΣΔ modulator running at 800 MHz for High‐IF conversion of 10MHz bandwidth signals at 200 MHz is presented. A novel transconductance amplifier has been developed to achieve high linearity and high dynamic range at high frequencies. A 2‐bit quantizer with offset cancellation is alsopresented. The sixth‐order modulator is implemented using 0.18 um TSMC standard analog CMOS technology. Post‐layout simulations in cadence demonstrate that the modulator achieves a SNDR of 78 dB (~13 bit) performance over a 14MHz bandwidth. The modulator’s static power consumption is 107mW from a supply power of ± 0.9V. Finally, a calibration technique for the optimization of the Noise Transfer Function CT BP ΣΔ modulators is presented. The proposed technique employs two test tones applied at the input of the quantizer to evaluate the noise transfer function of the ADC, using the capabilities of the Digital Signal Processing (DSP) platform usually available in mixed‐mode systems. Once the ADC output bit stream is captured, necessary information to generate the control signals to tune the ADC parameters for best Signal‐to‐Quantization Noise Ratio (SQNR) performance is extracted via Least‐ Mean Squared (LMS) software‐based algorithm. Since the two tones are located outside the band of interest, the proposed global calibration approach can be used online with no significant effect on the in‐band content.

To provide more information mobility, many wireless communication systems such as WCDMA and EDGE in phone systems, bluetooth and WIMAX in communication networks have been recently developed. Recent efforts have been made to build the allin- one next generation device which integrates a large number of wireless services into a single receiving path in order to raise the competitiveness of the device. Among all the receiver architectures, the high-IF receiver presents several unique properties for the next generation receiver by digitalizing the signal at the intermediate frequency around a few hundred MHz. In this architecture, the modulation/demodulation schemes, protocols, equalization, etc., are all determined in a software platform that runs in the digital signal processor (DSP) or FPGA. The specifications for most of front-end building blocks are relaxed, except the analog-to-digital converter (ADC). The requirements of large bandwidth, high operational frequency and high resolution make the design of the ADC very challenging. Solving the bottleneck associated with the high-IF receiver architecture is a major focus of many ongoing research efforts. In this work, a 6th-order bandpass continuous time sigma-delta ADC with measured 68.4dB SNDR at 10MHz bandwidth to accommodate video applications is proposed. Tuned at 200 MHz, the fs/4 architecture employs an 800 MHz clock frequency. By making use of a unique software-based calibration scheme together with the tuning properties of the bandpass filters developed under the umbrella of this project, the ADC performance is optimized automatically to fulfill all requirements for the high-IF architecture. In a separate project, other critical design issues for continuous-time sigma-delta ADCs are addressed, especially the issues related to unit current source mismatches in multi-level DACs as well as excess loop delays that may cause loop instability. The reported solutions are revisited to find more efficient architectures. The aforementioned techniques are used for the design of a 25MHz bandwidth lowpass continuous-time sigma-delta modulator with time-domain two-step 3-bit quantizer and DAC for WiMAX applications. The prototype is designed by employing a level-to-pulse-width modulation (PWM) converter followed by a single-level DAC in the feedback path to translate the typical digital codes into PWM signals with the proposed pulse arrangement. Therefore, the non-linearity issue from current source mismatch in multi-level DACs is prevented. The jitter behavior and timing mismatch issue of the proposed time-based methods are fully analyzed. The measurement results of a chip prototype achieving 67.7dB peak SNDR and 78dB SFDR in 25MHz bandwidth properly demonstrate the design concepts and effectiveness of time-based quantization and feedback. Both continuous-time sigma-delta ADCs were fabricated in mainstream CMOS 0.18um technologies, which are the most popular in today?s consumer electronics industry.

The goal of the research in this dissertation is to develop techniques for 1) system-on-package integration of passive circuits using ultra-thin advanced polymers called RXP (Rogers experimental polymer), 2) extraction of frequency-dependent material properties up to millimeter-wave frequency, 3) development and synthesis of high-rejection filter topologies, 4) design and characterization of high performance miniaturized embedded passive circuits for microwave and millimeter-wave applications, and 5) development of via and through-silicon via (TSV) enhanced filter design method for integration in high-loss substrate. The RXP material is developed to reduce the layer-count for multi-layer configuration and adoption of advanced fabrication technologies. Frequency-dependent material properties of RXP, ceramic, and other materials have been extracted up to millimeter-wave frequency using parallel-plate resonator method. An automated extraction algorithm has been proposed to handle a large number of frequency samples efficiently. The accuracy of the extraction result has been improved by including the surface roughness effect for conductor operating at high frequency. Using extracted RXP material properties, 2.4/5 GHz WLAN bandpass filters have been designed and characterized. High-rejection bandpass filter topologies for narrow 2.4 GHz and wide 5 GHz have been proposed. The proposed topologies have been synthesized to provide design equations as well as graphical design methodologies using Z-parameters. A new capacitor design called 3D stitched capacitor has been proposed to achieve more symmetric layout by providing balanced shunt parasitics. The proposed topologies and design methodologies have been verified through the measurement of high-rejection RXP bandpass filters. Good correlation between the simulation and measurement was observed demonstrating an effective design methodology and embedding bandpass filters with good performance. Dual-band bandpass filters for WLAN applications have been implemented and measured. Instead of connecting two bandpass filter circuits, a new single bandpass filter topology has been developed with a compact size as well as high isolation between passbands. High-rejection duplexer has been designed in RXP substrate for chip-last embedded IC technology, and a novel matching circuit has been applied for the miniaturization as well. The 60 GHz V-band has special interest for wireless applications because of its high attenuation characteristics because of atmospheric oxygen. Millimeter-wave passive circuits such as bandpass filter, dual-band filter, and duplexer have been designed, and self-resonant frequency of passive components has been carefully avoided using the proposed method. For low-cost system integration, silicon interposer with through-silicon-via (TSV) technology has been studied. The filter design method for high-loss substrate has been proposed. The coupling characteristic of TSV has been investigated for obtaining good insertion loss in lossy substrates such as silicon, and TSV characteristics has been used to design bandpass and highpass filters. To demonstration of concept, bandpass filters with good insertion loss have been realized on high-loss FR4 substrate.