A twin-buck converter with zero-voltage-transition (ZVT) is proposed in this thesis. The converter comprises two identical buck conversion units connected in parallel by an interleaved inductor. The ZVT is accomplished by the resonating the currents between the interleaved inductor and the parasitic capacitances of the power MOSFETs. The circuit efficiency can be further improved by introducing synchronous rectification to reduce the condition loss on the diodes. The detailed circuit analysis and operation characteristics are provided. A laboratory circuit rated at 300 W is designed and tested. Experimental results show that the switching losses can be effectively reduced by smoothly transiting the currents of the active power switches.

The power requirements for microprocessors have been increasing per Moore's Law. According to International Technology Roadmap (ITRS), Voltage Regulator Module (VRM) for microprocessors will be about 200 W at 1 V output in 2010. With the VRM’s topology of synchronous buck, serious technical challenges such as small duty cycle, high switching frequencies, and higher current demands, contribute to decreased power density and increased cost. This thesis proposes a Continuous Input Current Multiphase Interleaved Buck topology to solve the technical challenges of powering future microprocessors. This new topology is aimed to improve past topologies by providing continuous input current and improved efficiency. An open loop system of the proposed new topology is simulated using OrCAD PSpice to evaluate the performance criteria of the VRM. A hardware prototype of a four-phase Continuous Input Current Multiphase Interleaved Buck Converter is constructed and tested to assess the targeted improvements.

Time-interleaved analog-to-digital converters are an attractive architecture for achieving a high speed, high resolution ADC in a power efficient manner. However, due to process and manufacturing variations, timing skews occur between the sampling clocks of the sub ADCs within the TI-ADC. These timing skews compromise the spurious free dynamic range of the converter. In addition, jitter on the sampling clocks, degrades the signal-to-noise ratio of the TI-ADC. Therefore, in order to maintain an acceptable spurious free dynamic range and signal to noise ratio, it is necessary to correct the timing skews while adding minimal jitter. Two analog-based architectures for correcting timing skews were investigated, with one being selected for implementation. The selected architecture and additional test circuitry were designed and fabricated in a 0.18??m CMOS process and tested using a 125 MSPS 16 bit ADC. The circuit achieves a correction precision on the order of 10???s of femtoseconds for timing skews as large as approximately 180 picoseconds, while adding less than 200 femtoseconds of rms jitter.

Teaching is a complex and stressful job and despite efforts to consolidate the understanding of professional development programs, the effectiveness of such programs in real schools remains inconsistent. In this study, habit is used to understand the barriers to teacher development when looking to implement “interleaved practice” in mathematics. Interleaved practice consists of exercises involving different concepts, as opposed to “blocked practice” where there is only one concept practiced at once, and it has a growing experimental research base although lacking evidence from naturalistic studies. After an introduction to interleaved practice and the science behind it, different teachers’ activity was tracked using weekly surveys before the completion of interviews. The results showed that secondary mathematics teachers understood the benefits of interleaved practice, particularly in comparison to their previous employment of blocked practice which they now viewed negatively. Resource creation was the greatest barrier to the implementation of interleaved practice, which all the teachers overcame by finding personal resource creation routines, resulting in differing interpretations of interleaved practice. On top of the routine to create resources, each teacher described a unique rhythm that their normal lessons followed. There was a negative correlation between stress and the use of interleaved practice, however, one outlier strongly influenced this as they uniquely reported the highest levels of stress and had minimal novel use of interleaved practice. The results showed that with a light intervention, teachers can intuitively understand the weaknesses of the predominant blocked practice, but to change this habit they needed to define a new routine for creating interleaved resources. Understanding the teachers’ habits in terms of routines brings into focus the role of pedagogies of enactment, the teaching of strategies, within professional development. In terms of interleaved practice, this means evaluating how different strategies might affect teacher choices and student learning, and in general the interaction between strategies and teachers’ routines and habits. Finally, the stress outlier raises questions for future research on the effect of stress on teachers’ habitual behaviour, the strength of any relationship and whether it is linear or non-linear. / Att undervisa är ett komplext och stressigt arbete, och trots ansträngningar för att konsolidera förståelsen för professionella utvecklingsprogram är effektiviteten av sådana program i verkliga skolor fortfarande inkonsekvent. I den här studien används vanor för att förstå hindren för lärarutveckling när man försöker införa ”interleaved practice” i matematikundervisning. Interleaved practice består av övningar som omfattar olika begrepp, till skillnad från ”blocked practice” där endast ett begrepp tränas samtidigt, och metoden har en växande experimentell forskningsbas även om den saknar evidens från naturalistiska studier. Efter en introduktion till interleaved practice och vetenskapen bakom den följdes olika lärares verksamhet upp med hjälp av veckoenkäter innan intervjuer genomfördes. Resultaten visade att matematiklärare på gymnasienivå förstod fördelarna med interleaved practice, särskilt i jämförelse med deras tidigare användning av blocked practice som de nu såg negativt på. Resurskapande var det största hindret för genomförandet av interleaved practice, vilket alla lärare övervann genom att hitta personliga rutiner för resursskapande, vilket resulterade i olika tolkningar av interleaved practice. Utöver rutinen för att skapa nytt undervisningsmaterial beskrev varje lärare en unik rytm som deras normala lektioner följde. Det fanns en negativ korrelation mellan stress och användningen av interleaved practice, men ett avvikande värde påverkade detta starkt, eftersom de rapporterade de högsta stressnivåerna och hade minimal ny användning av interleaved practice. Resultaten visade att med en lätt intervention kan lärare intuitivt förstå svagheterna i den dominerande blocked practice, men för att ändra denna vana behövde de definiera en ny rutin för att skapa resurser med syfte att använda dem genom interleaved practice. Genom att förstå lärarnas vanor i termer av rutiner sätts fokus på den roll som pedagogiska metoder för genomförande, undervisning i strategier, spelar inom professionell utveckling. När det gäller interleaved practice innebär detta att man utvärderar hur olika strategier kan påverka lärarnas val och elevernas lärande, och i allmänhet samspelet mellan strategier och lärarnas rutiner och vanor. Slutligen väcker det avvikande värdet frågor för framtida forskning om hur stress påverkar lärares vanemässiga beteende, hur starkt sambandet är och om det är linjärt eller icke-linjärt.

This thesis examines the use of ripple correlation control as a maximum power point tracking algorithm with an interleaved SEPIC converter for use with a solar array. The suitability of existing topologies for use with photovoltaic applications and the tradeoffs involved are discussed. The advantages of interleaving in converters are examined and the benefits it provides to photovoltaic applications are discussed. An interleaved SEPIC converter operated in interleaved mode with a photovoltaic array is studied. The operation of ripple correlation control as a maximum power point tracking technique applied to the interleaved SEPIC converter is examined and simulations with results are presented. / text

This thesis addresses the influence of veil architecture on interlaminar fracture toughness (IFT) of interleaved unidirectional (UD) carbon fibre-epoxy composites with the aim to provide insights. Two nonwoven veils sets formed from polyphenylene sulfide (PPS) fibres with different diameters, with a range of increasing areal density, and a sample of polyetheretherketone (PEEK) fibres, with comparable fibre diameter, are characterised gravimetrically and by tensile tests (long and zero span). Consequently, the anisotropy and maximum stress transfer efficiency (MSTE) parameters are shown by these veils. Subsequently, the veils are interleaved within UD composites and assessed for mode I and mode II IFT. In both modes the veils show a strong dependence on areal density before a plateau at high areal densities, although the lower diameter fibres showed higher IFT values. Interpretation of the results reveal that the difference is attributable to the coverage of veils and thus, to the fraction of fibres in the propagation of crack. However, the effect of fibres is quite evident through the fibre bridging mechanism in the propagation of cracks, more significantly in mode I than in mode II. Moreover, in mode I and mode II a linkage of MSTE of veils with low data variability in IFT is observed. With regard to the anisotropy, this is notably significant only for the PEEK sample, though a statistical analysis supports that the IFT values from both types of fibres are consistent. A comparison of data revealed a slight dependence of the ratio mode II/mode I on areal density only for the larger diameter PPS fibre and the anisotropy of PEEK sample has a strong influence on this ratio. In both modes, however, data presented by this study are consistent with data provided by previous work. Subsequently, mass distribution of veil handsheets is assessed for both modes of IFT into UD composites, revealing no significant dependence of mass distribution on mode I IFT, whereas for mode II this dependence is significant due to the effect a variety of fractional open area size and the floculatted fibres. Fractographic observations via SEM (Scanning Electro Microscope) from representative interleaved composites are analysed and discussed.

La generación de nuevas estructuras convertidoras y su modelado matemático son las dos temáticas principales estudiadas en esta tesis. El seguimiento de una metodología que modifica la estructura del circuito, realizando una ruptura de la simetría con base en los resultados de simulación, permitió generar la familia de convertidores en "interleaving" asimétrico compuesta por el AIDB, el AIDBB y el grupo-AIDF. En el apartado de modelado se ha desarrollado una nueva aproximación conceptual inspirada en las ideas de trabajos previos que se estudian en el estado del arte. El nombre dado a esta nueva aproximación es: Promediado Modificado Usando Métodos Gráficos. Este nuevo enfoque ha sido utilizado para obtener el modelo promediado de la nueva familia de convertidores en el espacio de estados. Las mediciones experimentales de la respuesta en frecuencia del convertidor AIDB y el diseño del controlador LQR permitieron verificar la aproximación del modelo en pequeña señal obtenido. / The two main topics presented in this thesis are the generation and mathematical modelling of new converter structures. The fundamental idea behind the methodology used to generate the new converter structures was to break the symmetry. This involved modifying the circuit structure on the basis of the simulation results. This methodology allowed the generation of the family of asymmetrical interleaved converters, which consists of the AIDB, the AIDBB and the AIDFgroup. A new conceptual modelling approach was developed on the basis of ideas taken from previous research which is reviewed in the state of the art. This approach was called Modified Averaging Using Graphical Methods. Because of its features, this new method can be used to model the state space average of the new converter family presented here. The accuracy of the AIDB converter small signal model was verified by measuring the frequency response and by designing an LQR controller.

Nowadays, Multi-GHz analog-to-digital converters (ADCs) are becoming more and more popular in radar systems, software-de ned radio (SDR) and wideband communications, because they can realize much higher operation speed through using many interleaved sub-ADCs to relax ADC sampling rates. Although the time interleaved ADC has some issues such as gain mismatch, o set mismatch and timing skew between each ADC channel, these deterministic errors can be solved by previous works such as digital calibration technique. However, time-interleaved ADCs require a precise sample clock to achieve an acceptable e ective-numberof- bits (ENOB) which can be degraded by jitter in the sample clock. The clock generation circuits presented in this work achieves sub-picosecond jitter performance in 180nm CMOS which is suitable for time-interleaved ADC. Two di erent test chips were fabricated in 180nm CMOS to investigate the low jitter design technique. The low jitter delay line in two chips were designed in two di erent ways, but both of them utilized the low jitter design technique. In rst test chip, the measured RMS jitter is 0.1061ps for each delay stage. The second chip uses the proposed low jitter Delay-Locked Loop can work from 80MHz to 120MHz, which means it can provide the time interleaved ADC with 2.4GHz to 3.6GHz low jitter sample clock, the measured delay stage jitter performance in second test chip is 0.1085ps.

Broadband wireless communication systems demand power-efficient analog-to-digital converters (ADCs) in the GHz and medium resolution regime. While high-speed architectures such as the flash and pipelined ADCs are capable of GHz operations, their high-power consumption reduces their attractiveness for mobile applications. On the other hand, the successive-approximation-register (SAR) ADC has an excellent power efficiency, but its slow speed has traditionally limited it to MHz applications. This dissertation puts forth several novel techniques to significantly increase the speed and power efficiency of the SAR architecture and demonstrates them in a low-power 10-GHz SAR ADC suitable for broadband wireless communications. The proposed 8-bit, 10-GHz, 8× time-interleaved SAR ADC utilizes a constant-matching DAC with symmetrically grouped unit finger capacitors to maximize speed by reducing the total DAC capacitance to 32 fF and minimizing the bottom plate parasitic capacitance. The capacitance reduction also saves power as both the DAC size and the driving logic size are reduced. An optimized asynchronous comparator loop and smaller driver logic push the single channel speed of the SAR ADC to 1.25 GHz, thus minimizing the total number of timeinterleaved channels to 8 to reach 10 GHz. A dual-path bootstrapped switch improves the spurious-free dynamic range (SFDR) of the sampling by creating an auxiliary path to drive the non-linear N-well capacitance apart from the main signal path. Using these techniques, the ADC achieves a measured signal-to-noise-and-distortion ratio (SNDR) and SFDR of 36.9 dB and 59 dB, respectively with a Nyquist input while consuming 21 mW of power. The ADC demonstrates a record-breaking figure-of-merit of 37 fJ/conv.-step, which is more than 2× better than the next best published design, among reported ADCs of similar speeds and resolutions.

<p> The goal of this thesis is the development of a computationally-efficient coded system that enables communication over the non-coherent Multiple-Input Multiple-Output (MIMO) fiat-fading wireless channel at high data rates. The proposed signalling technique applies the principles of Bit-Interleaved Coded Modulation (BICM) with Iterative Demapping and Decoding (IDD) to non-coherent MIMO communication systems. </p> <p> The principle of BICM is applied to a constellation that mimics the non-coherent capacity achieving distribution at high signal to noise ratios. The capacity achieving distribution is in the form of isotropically distributed unitary matrices, and the constellation can be represented by points on a Grassmannian manifold. A mapping technique that exploits the Grassmannian geometry is proposed. This mapping technique is based on the partitioning of the constellation into two subsets. The Grassmannian geometry also gives rise to an efficient list-based demapping algorithm that substantially reduces the computational complexity of the receiver while incurring some degradation in performance. For example, at a bit error rate (BER) of 10-4 the signal to noise ratio (SNR) performance degradation with respect to full constellation demapping is approximately 1. 75 dB. A technique by which the decoder can augment the demapping list is proposed, and it is shown that the performance degradation of the efficient algorithm can be rendered insignificant (approximately 0.2 dB at a BER of 10-4). </p> <p> Finally, the performance of the proposed BICM-IDD using the Grassmannian constellation will be compared to that of a corresponding training-based BICM-IDD scheme. These simulations show that the proposed scheme can provide better performance at high data rates; e.g., for a data rate of 5/3 bits per channel use, the performance gap is almost 1 dB at BER of 10^(-4). </p> / Thesis / Master of Applied Science (MASc)