Pass-transistor logic (PTL) has become an alternative design to traditional CMOS logic design due to its advantages of area/speed/power for some particular circuits such as Exclusive-OR gates. However, the standard cell library used in the logic synthesis of the conventional cell-based design flow does not include PTL circuits. In this thesis, we present a new logic synthesis approaches that consider both the PTL and CMOS cells in order to improve the area and speed performance of the synthesized circuits. In the proposed PTL synthesis, only two types of basic cells are used: a 2-to-1 multiplexer composed of two nMOSs in parallel (MUX) and an inverter with feedback pMOS (P_INV). We propose two methods for mixed PTL/CMOS synthesis. Method 1 finds better choice of library cells from the mixed PTL/CMOS cell library during the technology mapping of the synthesis stage. Method 2 searches for possible CMOS replacement in the pure PTL netlists. Both methods require the efficient inverter reduction method to eliminate unnecessary inverters during the synthesized gate-level netlists. The experimental results show that the mixed PTL/CMOS synthesis can further improve the speed performance compared with pure PTL or pure CMOS synthesis results.

Pass Transistor Logic (PTL) is a well known approach for implementing digital circuits. In order to handle larger designs and also to ensure that the total number of series devices in the resulting circuit is bounded, partitioned Reduced Ordered Binary Decision Diagrams (ROBDDs) can be used to generate the PTL circuit. The output signals of each partitioned block typically needs to be buffered. In this thesis, a new methodology is presented to perform generalized buffering of the outputs of PTL blocks. By performing the Boolean division of each PTL block using different gates in a library, we select the gate that results in the largest reduction in the height of the PTL block. In this manner, these gates serve the function of buffering the outputs of the PTL blocks, while also reducing the height and delay of the PTL block. PTL synthesis with generalized buffering was implemented in two different ways. In the first approach, Boolean division was used to perform generalized buffering. In the second approach, compatible observability don't cares (CODCs) were utilized in tandem with Boolean division to simplify the ROBDDs and to reduce the logic in PTL structure. Also CODCs were computed in two different manners: one using full simplify to compute complete CODCs and another using, approximate CODCs (ACODCs). Over a number of examples, on an average, generalized buffering without CODCs results in a 24% reduction in delay, and a 3% improvement in circuit area, compared to a traditional buffered PTL implementation. When ACODCs were used, the delay was reduced by 29%, and the total area was reduced by 5% compared to traditional buffering. With complete CODCs, the delay and area reduction compared to traditional buffering was 28% and 6% respectively. Therefore, results show that generalized buffering provides better implementation of the circuits than the traditional buffering method.

Titel: Bankrevisorers yrkesutövning i det förebyggande arbetet mot penningtvätt Syfte: Studien syfte är att öka förståelsen samt förklara hur externa och interna bankrevisorer arbetar förebyggande mot penningtvätt inom banksektorn. Syftet besvaras genom att undersöka hur penningtvättslagen tillämpas i bankrevisorers yrkesutövning, hur det arbetet förhåller sig till god revisionssed samt om berörda parter upplever ett förväntningsgap gällande bankrevisorers ansvar att upptäcka finansbrott, såsom penningtvätt. Metod: Studien har tillämpat en kvalitativ forskningsmetod för att studera hur externa och interna bankrevisorers yrkesutövande förhåller sig till det förebyggande arbetet mot penningtvätt. Detta har genomförts med hjälp av tio stycken semi-strukturerade intervjuer med externa och interna bankrevisorer samt berörda parter för att kunna bidra med ytterligare perspektiv. Resultat och slutsats: Ett resultat som studien kan påvisa är att varken interna eller externa bankrevisorer rapporterar misstänkt penningtvätt direkt till Finanspolisen. Interna bankrevisorer rapporterar misstänkt penningtvätt till Compliance-funktionen samt att externa bankrevisorer rapporterar misstänkt penningtvätt till företagets VD eller styrelse i första hand. Studien finner stöd i att god revisionssed är en betydande faktor i det förebyggande arbetet mot penningtvätt för externa och interna bankrevisorer. Det finns även ett förväntningsgap eftersom externa och interna bankrevisorer kan göra mer i deras yrkesutövning för att förebygga penningtvätt inom banksektorn. Förslag till vidare forskning: En liknande studie som enbart fokusera på banker som sysslar med kontanthantering samt att Revisorsnämndens perspektiv beaktas. Studiens bidrag: Studien bidrar till att kartlägga externa och interna bankrevisorers ansvar i det förebyggande arbetet mot penningtvätt inom banksektorn. Studiens resultat bidrar till företagsekonomisk forskning genom att öka förståelsen av samarbetet mellan samtliga parter för att förebygga penningtvätt inom banksektorn. Nyckelord: Bankrevisorer, internrevision, externrevision, penningtvätt, PTL, penningtvättslagen, god revisionssed / Title: Bank auditors professional practice in the prevention of money laundering Aim: The aim of this essay is to increase understanding and explain how external and internal bank auditors work to prevent money laundering in the banking sector. The aim is answered by examining how the Money Laundering Act apply in their professional practice, how the work relates to the generally accepted auditing standards and if concerned parties are experiencing a gap of expectations regarding bank auditors responsibility of detecting financial crimes such as money laundering. Method: The essay has applied a qualitative research method to study how external and internal bank auditors professional practice relates to the prevention of money laundering. This has been achieved by executing ten semi-structured interviews with external and internal bank auditors and other concerned parties to contribute additional perspectives. Results and Conclusions: The result of the essay shows that neither external nor internal bank auditors report suspected money laundering directly to the Finance Police. Internal bank auditors report suspected money laundering to the Compliance department and the external bank auditors report suspected money laundering to the company CEO or board in firsthand. The essay shows that the generally accepted auditing standards are a significant factor in the prevention of money laundering for external and internal bank auditors. The result shows a gap of expectations, the external and internal bank auditors can contribute more in their professional practice to the prevention of money laundering in the banking sector according to concerned parties. Suggestions for future research: A similar study focusing solely on banks with cash management including the Auditor Board´s perspective. Contributions of the essay: The essay helps to identify external and internal bank auditors responsibility in the prevention of money laundering in the banking sector. The results contribute to business research by increasing understanding of the cooperation between concerned parties to prevent money laundering in the banking sector. Keywords: bank auditors, internal audit, external audit, money laundering, PTL, the Money Laundering Act, generally accepted auditing standards

Submitted by Aline Batista (alinehb.ufpel@gmail.com) on 2017-03-24T19:58:57Z No. of bitstreams: 2 license_rdf: 0 bytes, checksum: d41d8cd98f00b204e9800998ecf8427e (MD5) Comparação de diferentes topologias de portas XOR em uma tecnologia de 45 nm.pdf: 6133925 bytes, checksum: 1acf2c33bd1187b626943c709eb21b2f (MD5) / Approved for entry into archive by Aline Batista (alinehb.ufpel@gmail.com) on 2017-04-05T19:13:36Z (GMT) No. of bitstreams: 2 Comparação de diferentes topologias de portas XOR em uma tecnologia de 45 nm.pdf: 6133925 bytes, checksum: 1acf2c33bd1187b626943c709eb21b2f (MD5) license_rdf: 0 bytes, checksum: d41d8cd98f00b204e9800998ecf8427e (MD5) / Made available in DSpace on 2017-04-05T19:13:47Z (GMT). No. of bitstreams: 2 Comparação de diferentes topologias de portas XOR em uma tecnologia de 45 nm.pdf: 6133925 bytes, checksum: 1acf2c33bd1187b626943c709eb21b2f (MD5) license_rdf: 0 bytes, checksum: d41d8cd98f00b204e9800998ecf8427e (MD5) Previous issue date: 2016-09-16 / Sem bolsa / Sistemas digitais estão presentes em grande parte das atividades humanas, e cada vez mais as pessoas interagem diariamente com uma série de circuitos nos mais diversos tipos de equipamentos. As dimensões nanométricas dos atuais dispositivos integrados geram uma série de desa?os a serem superados, entre eles a otimização de circuitos para que tenham alto desempenho e baixo consumo, preenchendo requisitos cada vez mais rígidos para que sejam apropriados ao uso em sistemas portáteis de alto desempenho. As portas lógicas XOR (Ou-Exclusivo) possuem papel fundamental para a funcionalidade de diversos circuitos lógicos e o projeto de portas lógicas XOR de alto desempenho, com imunidade a ruídos e baixo consumo de energia constitui importante frente de pesquisa na área de projeto de circuitos integrados. Baseando-se nas regras dos estilos lógicos mais utilizados, CMOS e PTL, muitos arranjos de portas XOR têm sido propostos. Este trabalho apresenta uma investigação sobre estes arranjos e as técnicas que fundamentam seu projeto, bem como os estilos híbridos que têm sido propostos. São avaliados vinte e dois arranjos XOR propostos na literatura com os resultados obtidos em simulações de consumo e atraso para uma tecnologia de 45-nm. / Digital systems are present in most human activities, and an increasing number of people interact daily with a series of circuits in a wide range of equipments. The nanometric dimensions of the current integrated devices generate a series of challenges to be overcome, including the circuit optimization in order to have high performance and low consumption, filling increasingly stringent requirements to be suitable for use in high-performance portable systems. The XOR logic gates (Exclusive-OR) play a fundamental role for the functionality of various logic circuits and the project of high performance XOR logic gates, with noise immunity and low power consumption, consists in an important line of research in the ?eld of integrated circuits project. Based on the rules of the most used logic styles, CMOS and PTL, many XOR gates arrangements have been proposed. This paper presents an investigation into these arrangements and the techniques that underlie their design, as well as hybrid styles that have been proposed. There’s an evaluation of twenty-two XOR arrangements proposed in literature, with the results obtained from consumption and delay simulations for a 45-nm technology.

The mainstream of current VLSI design and logic synthesis is based on traditional CMOS logic circuits. However, various new logic circuit design styles based on pass-transistor logic (PTL) have been proposed. The advantage of PTL is higher speed, smaller area and lower power for some particular circuits such as XOR. Since most current automatic logic synthesis tools (such as Synopsys Design Compiler) are based on conventional CMOS standard cell library, the corresponding logic minimization for CMOS logic cannot be directly employed to generate efficient PTL circuits. In this thesis, we develop a novel PTL synthesizer that can efficiently generate PTL-based circuits. We proposed a new synthesis method (hybrid PTL/CMOS Library design) that has multiple driving strengths and multiple threshold voltages to achieve better performance in area, speed, and power. Since PTL-based circuits are constructed by only a few basic PTL cells, the layouts in PTL cells can be easily updated as the process technology migrates rapidly in current Nano technology era. The proposed PTL logic synthesis flow employs the popular Synopsys Design Compiler (DC) to perform logic translation and minimization based on the standard cell library composed of PTL and CMOS logic cells. Thus, the PTL design flow can be easily embedded in the standard cell-based ASIC design flow.

Penningtvätt är ett ständigt växande problem som kräver effektiva gränsöverskridande åtgärder för att upprätthålla en god finansiell stabilitet. Ett av de mest handfasta och effektiva redskap för banker att tillgå för att förhindra penningtvätt är kundkännedomsprocessen. Under våren 2015 antog EU ett fjärde penningtvättsdirektiv, vilket innehåller förenklade men skärpta krav på när kundkännedomsåtgärder ska vidtas. Direktivet har en ökad betoning på det riskbaserade förhållningssättet, vilket innebär att bankerna ska genomföra riskbedömningar och anpassa kundkännedomsåtgärderna därefter. Under våren 2016 antog EU även en ny dataskyddsförordning, vilken ska ge ett ökat skydd för personlig integritet. Samtidigt som kraven på kundkännedom skärps ska således enskilda personer ges större kontroll över sina personuppgifter. I framställningen behandlas kundkännedomsreglerna och huruvida bankerna kan tillämpa dessa för att arbetet mot penningtvätt ska kunna företas på ett effektivt sätt. Kärnan i kundkännedomsprocessen kan vidare sägas vara insamling och hantering av, ofta känsliga, personuppgifter. Det krävs därmed att bankerna kan utföra kundkännedomsprocessen på ett sätt som inte bryter mot reglerna om personuppgifter. Till följd av detta har systemkonflikten som finns mellan kundkännedomsreglerna och reglerna om personuppgifter analyserats och diskuterats. Av resultatet framgår att kundkännedomsreglerna, särskilt med beaktade av de nya kraven i fjärde penningtvättsdirektivet, innebär ett långtgående krav på bankerna att genomföra korrekta riskbedömningar. En misslyckad övergripande riskbedömning leder till genomgående brister i verksamhetens arbete mot penningtvätt, inte minst vad avser kundkännedomsåtgärderna. Detta innebär en negativ påverkan på regelverkets effektivitet. Vidare förutsätter kundkännedomsreglerna korrekta och kvalitativa riskbedömningar för att säkerställa väl förankrade riskklassificeringar av kunderna, vilka styrker rätten att inhämta personuppgifter i viss omfattning. Systemkonflikten mellan regelverkens motstående intressen försätter bankerna i en svår bedömningssituation där intresset av att bekämpa penningtvätt måste vägas mot intresset av att värna om den personliga integriteten.

No description available.

Wireless sensor networks (WSN) play an important role in today’s monitoring and controlsystems like environmental monitoring, military surveillance, industrial sensing and control, smarthome systems and tracking systems. As the application of WSN grows by leaps and bounds, there is anincreasing demand in placing a larger number of sensors and controllers to meet the requirements. Theincreased number of sensors necessitates flexibility in the functioning of nodes. Nodes in wirelesssensor networks should be capable of being dynamically reconfigured to perform various tasks is theneed of the hour.In order to achieve flexibility in node functionality, it is common to adopt reconfigurablearchitecture for WSN nodes. FPGA-based architectures are popular reconfigurable architectures bywhich WSN nodes can be programmed to take up different roles across time. Area and power are themajor overheads in FPGA based architectures, where interconnect consumes more power and area thanlogic cells. The contemporary WSN standard requires longer battery life and micro size nodes for easyplacement and maintenance-free operation for years together.Three solutions have been studied and evaluated to approach this problem: 1) Homogenousembedded FPGA platform, 2) Power gated reconfigurable finite state machines and 3) Pass transistorlogic (PTL) based reconfigurable finite state machines. Embedded FPGA is a CMOS 65nm customdeveloped small homogenous FPGA which holds the functionality of the WSN nodes and it will bedynamically reconfigured from time to time to change the functionality of the node. In Power gatedreconfigurable FSM architecture, the functionality of the node is expressed in the form of finite statemachines, which will be implemented in a LUT based power gated design. In PTL based reconfigurablefinite state machine architecture, the finite state machines are completely realized using PTL basedcustom designed sets of library components. Low power configuration memory is used to dynamicallyreconfigure the design with various FSMs at different times.

The mainstream of current VLSI design and logic synthesis is based on traditional CMOS logic circuits. However, in the past two decades, various new logic circuit design styles based on pass-transistor logic (PTL) have been proposed. Compared with CMOS circuits, these PTL-based circuits are claimed to have better results in area, speed, and power in some particular applications, such as adder and multiplier designs. Since most current automatic logic synthesis tools (such as Synopsys Design Compiler) are based on conventional CMOS standard cell library, the corresponding logic minimization for CMOS logic cannot be directly employed to generate efficient PTL circuits. In this dissertation, we develop two novel PTL synthesizers that can efficiently generate PTL-based circuits. One is based on pure PTL cells; the other mixes CMOS and PTL cells in the standard cell library to achieve better performance in area, speed, and power. Since PTL-based circuits are constructed by only a few basic PTL cells, the layouts in PTL cells can be easily updated to design large SoC systems as the process technology migrates rapidly in current Nano technology era. The proposed PTL logic synthesis flows employ the popular Synopsys Design Compiler (DC) to perform logic translation and minimization based on the standard cell library composed of PTL and CMOS cells, thus, the PTL design flow can be easily embedded in the standard cell-based ASIC design flow. In this dissertation, we also discuss PTL-based designs of some fundamental hardware components. Furthermore, the proposed PTL cell library is used to synthesize large processor systems in applications of computer arithmetic and 3D graphics.

Varje dag möter advokaten rättsliga problem och spörsmål som ska lösas men han möter också sitt eget dilemma. Enighet råder inte alltid mellan den absoluta lojaliteten mot klienten och rättssystemet vilket innebär en prövning av de olika normer som advokaten har att förhålla sig till. Lagstiftaren har givit Svenska Advokatsamfundet befogenhet att besluta om gällande regler för god advokatsed samtidigt som lagstiftaren behållit strafflagstiftningen för advokater inom sin egen sfär. Advokatsamfundets styrelse och disciplinnämnd beslutar om disciplinära åtgärder i situationer där advokater inte tillgodosett god advokatsed. Uteslutning, varning, erinran eller varning med straffavgift är sådana disciplinära åtgärder som kan sanktionera advokaters handlande. Av stor betydelse för advokaten är biträdeslagen vilken föreskriver straffansvar för advokater som med grov oaktsamhet främjat brottslig gärning. Vårdslöst biträde är en kompletterande bestämmelse till medverkansansvaret i 23 kap. BrB. Även PTL har en central ansvarsbestämmelse i vilken advokaten kan göras ansvarig vid uppsåt eller av grov oaktsamhet för att brutit mot gransknings-, och rapporteringsskyldigheten eller mot meddelandeförbudet. PTL kommer ursprungligen från ett EG-direktiv med syftet att motverka ekonomisk brottslighet och reglerar förhållandet när advokaten har misstanke om penningtvätt i samband med klientuppdrag. Biträdeslagen och PTL kräver i vissa situationer att advokaten ska frångå sin lojalitetsplikt till förmån för rättsamhället, exempelvis bryter advokaten sin tystnadsplikt när han rapporterar misstänkt penningtvätt till Rikspolisstyrelsen. Om advokaten inte haft fog att frångå sin lojalitetsplikt drabbas han av disciplinära åtgärder. Således måste advokaten vara aktsam i sina beslut gällande främjande eller avslöjande av brott. Dels riskerar han klientens förtroende, dels riskerar han sin egen frihet, sin verksamhet och sitt anseende. Detta arbete belyser tillämpningen av kriterierna i ansvarsbestämmelserna samt hur advokaten gör sin bedömning för att tillgodose god advokatsed och rättsreglerna som inte alltid faller samman. Som hjälp finns praxis från HD och disciplinnämnden men dessa är långt ifrån uttömmande. Således måste advokaten lita till sin egen förmåga att utifrån varje situation göra en bedömning och därefter agera så långt lojalitetsplikten sträcker sig utan att bryta mot lagen.