Due to the limitations of silicon (Si), there is a paradigm shift in research focusing on wide-bandgap-based (WBG) materials. SiC power semiconductors exhibit superiority in terms of switching speed, higher breakdown electric field, and high working temperature, slowly becoming a global solution in harsh medium-voltage (MV) high-power environments. However, to utilize the SiC MOSFET device to achieve those next-generation, high-density, high-efficiency power electronics converters, one must solve a plethora of challenges. For the MV SiC MOSFET device, a high-performance gate-driver (GD) is a key component required to maximize the beneficial SiC MOSFET characteristics. GD units must overcome associated challenges of electro-magnetic interference (EMI) with regards to common-mode (CM) currents and cross-talk, low driving loop inductance required for fast switching, and device short-circuit (SC) protection. Developed GDs (for 1.2 kV, and 10 kV devices) are able to sustain dv/dt higher than 100 V/ns, have less than 5 nH gate loop inductance, and SC protection, turning off the device within 1.5 us. Even with the introduction of SiC MOSFETs, power devices remain the most reliability-critical component in the converter, due to large junction temperature (Tj) fluctuations causing accelerated wear-out. Real-time (online) measurement of the Tj can help improve long-term reliability by enabling active thermal control, monitoring, and prognostics. An online Tj estimation is accomplished by generating integrated intelligence on the GD level. The developed Tj sensor exhibits a maximum error less than 5 degrees Celsius, having excellent repeatability of 1.2 degrees Celsius. Additionally, degradation monitoring and an aging compensation scheme are discussed, in order to maintain the accuracy of the sensor throughout the device's lifetime. Since ultra high-voltage SiC MOSFET devices (20 kV) are impractical, the modular multilevel converter (MMC) emerged as a prospective topology to achieve MV power conversion. If the kernal part of the power-cell (main constitutive part of the MMC converter) is an SiC MOSFET, the design is able to achieve very high-density and high-efficiency. To ensure a successful operation of the power-cell, a systematic design and assessment methodology (DAM) is explored, based on the 10 kV SiC MOSFET power-cell. It simultaneously addresses challenges of high-voltage insulation, high dv/dt and EMI, component and system protections, as well as thermal management. The developed power-cell achieved high-power density of 11.9 kW/l, with measured peak efficiency of n=99.3 %@10 kHz. It successfully operated at Vdc=6 kV, I=84 A, fsw>5 kHz, Tj<150 degrees Celsius and had high switching speeds over 100 V/ns. Lastly, to achieve high-power density and high-efficiency on the MV converter level, challenges of high-voltage insulation, high-bandwidth control, EMI, and thermal management must be solved. Novel switching cycle control (SCC) and integrated capacitor blocked-transistor (ICBT) control methodologies were developed, overcoming the drawbacks of conventional MMC control. These novel types of control enable extreme reduction in passive component size, increase the efficiency, and can operate in dc/dc, dc/ac, mode, potentially opening the modular converter to applications in which it was not previously used. In order to explore the aforementioned benefits, a modular, scalable, 2-cell per arm, prototype MV converter based on the developed power-cell is constructed. The converter successfully operated at Vdc=12 kV, I=28 A, fsw=10 kHz, with high switching speeds, exhibiting high transient immunity in both SCC and ICBT. / Doctor of Philosophy / In medium-voltage applications, such as an electric grid interface in highly populated areas, a ship dc system, a motor drive, renewable energy, etc., land and space can be very limited and expensive. This requires the attributes of high-density, high-efficiency, and reliable distribution by a power electronics converter, whose central piece is the semiconductor device. With the recent breakthrough of SiC devices, these characteristics are obtainable, due to SiC inherent superiority over conventional Si devices. However, to achieve them, several challenges must be overcome and are tackled by this dissertation. Firstly, as a key component required to maximize the beneficial SiC MOSFET characteristics, it is of utmost importance that the high-performance gate-driver be immune to interference issues caused by fast switching and be able to protect the device against a short-circuit, thus increasing the reliability of the system. Secondly, to prevent accelerated degradation of the semiconductor devices due to high-temperature fluctuations, real-time (online) measurement of the Tj is developed on the gate-driver to help improve long-term reliability. Thirdly, to achieve medium-voltage high-power density, high-efficiency modular power conversion, a converter block (power-cell) is developed that simultaneously addresses the challenges of high-voltage insulation, high interference, component and system protections, and thermal management. Lastly, a full-scale medium-voltage modular converter is developed, exploiting the advantages of the fast commutation speed and high switching frequency offered by SiC, meanwhile exhibiting exceptional power density and efficiency.

The electric power system is undergoing a paradigm change on how electric energy is generated, transmitted, and delivered. Power electronics systems which can provide medium-voltage (MV) to high-voltage (HV) output (>13.8 kV ac, > 20 kV dc) with much faster dynamic response (> 10 kHz bandwidth) or high switching-frequency will enable new electronic energy network architectures, like MVDC power delivery, underground solid-state power substation (SSPS), and high-density power electronics building block (PEBB); help drive the levelized cost of electricity (LCOE) of renewable energy on par with conventional power generation; deliver precise and clean power to loads like high-speed electric motors; push the future power system toward 100% renewable energy and energy storage supplied. In the MV to HV area, the power conversion solution is dominated by silicon devices, like SCR, IGCT, and IGBT, which are slow in nature, posing significant switching losses and bulky auxiliary components like turn-on snubbers. Devices in series are required to reach higher voltage. High-frequency HV converter in two-level or three-level bridges running 20 kHz or higher in many emerging applications, like MVDC networks with high-frequency transformers and energy storage integration is hard to be built by silicon solutions. The emerging HV wide-bandgap (WBG) power semiconductors, e.g., 10 kV SiC MOSFETs offer higher blocking capability, faster and more efficient switching performances. This makes the high-frequency power conversion technology feasible for the MV area. To build a MV high-frequency power converter with high-power density, 10 kV SiC MOSFETs in series are required to reach >10 kV operation dc voltage as the single device rating is still limited by the semiconductor process and packaging capability. However, the knowledge of dynamic voltage sharing of high-speed HV SiC devices under high dv/dt rate and effective balancing methods are not fully explored. Both the voltage imbalance and the robust device voltage balancing control are not studied clearly in the existing literature. This dissertation evaluates the voltage imbalance of series-connected 10 kV SiC MOSFETs thoroughly. The parasitic capacitors connected with device terminals are found to be a unique factor for the voltage imbalance of series-connected SiC MOSFETs, which have a significant impact on the dv/dt of different devices based on the detailed analysis. The unbalanced dv/dt and the gate signal mismatch together result in the voltage imbalance of series-connected SiC MOSFETs and a set of new voltage balancing control methods are proposed. Passive capacitor compensation and closed-loop short pulse gate signal control are proposed to solve the voltage imbalance caused by the unbalanced dv/dt. Closed-loop gate delay time control is proposed to solve the voltage imbalance caused by the gate signal mismatch. Two gate driver prototypes are designed and verified for the proposed voltage balancing control methods. As the number of devices increases, the voltage balancing methods under the device-level will be complex and risky to coordinate. Therefore, the converter-level device voltage balancing methods are desired when over three devices are in stack. Therefore, this dissertation proposes to use the 3-level (3L) neutral-point-clamped (NPC) converter structure as a converter-level approach to simplify the voltage balancing control of series-connected SiC MOSFETs. A new modulation strategy is proposed to control the loss of clamping diodes, so compact MV SiC Schottky diodes can be selected to reduce the impact of extra components on the power density. Compared to the phase-leg with direct series-connected SiC MOSFETs, the phase-leg designed with the converter-level approach achieves similar power density, easier voltage balancing control, and better efficiency, which is attractive for both two and four devices in series connection. Finally, this dissertation studies the impact of series-connected 10 kV SiC MOSFETs on MV phase-leg volume reduction with the example of multi-level flying capacitor (FC) converters. The relation between the capacitances of FCs and the device voltage is studied and a new design procedure for FCs is developed to achieve minimum FC energy and regulate the maximum device voltage. With the design procedure, the total FC volumes of a 22 kV 5-level FC converter and a 22 kV 3-level FC converter with series-connected 10 kV SiC MOSFETs are calculated and compared. Series-connected 10 kV SiC MOSFETs are found to help significantly reduce the total FC volume (> 85 %). In summary, this dissertation demonstrates that the direct series connection of 10 kV SiC MOSFETs is a reliable solution for the MV converter design, and the converter-level approach is a better voltage balancing control method. This dissertation also presents a quantitative analysis of the volume reduction enabled by the series-connected 10 kV SiC MOSFETs in MV converter phase-leg design. / Doctor of Philosophy / Emerging industrial applications require medium voltage (MV) power converters. For existing MV converter solutions with Si IGBT, complex system structures are usually required, which affects the efficiency, power density, and cost of the system. For the design of MV converter, the recent 10 kV SiC MOSFET has the promising potential to improve efficiency and power density by adopting a simpler topology and fewer conversion stages. New design challenges also emerge with the new 10 kV SiC MOSFETs and one of them is the device voltage control during the operation. This dissertation mainly focuses on the voltage balancing control of series-connected 10 SiC MOSFETs, which is an attractive solution to build the MV converter phase-leg in a simple structure. Several voltage balance control methods are proposed and compared in this dissertation, which helps justify that the series-connected SiC MOSFET is a reliable approach for the MV converter design. In addition, this dissertation also analyzes the volume reduction enabled by the series-connected SiC MOSFETs with the example of a multi-level flying capacitor converter in dc-ac applications.

Due to the superior characteristics compared to its silicon (Si) counterpart, the wide bandgap (WBG) semiconductor enables next-generation power electronics systems with higher efficiency and higher power density. With higher blocking voltage available, WBG devices, especially the silicon carbide (SiC) metal-oxide-semiconductor field-effect transistor (MOSFET), have been widely explored in various medium-voltage (MV) applications in both industry and academia. However, due to the high di/dt and high dv/dt during the switching transient, potential overcurrent, overvoltage, and gate failure can greatly reduce the reliability of implementing SiC MOSFETs in an MV system. By utilizing the parasitic inductance between the Kelvin- and the power-source terminal, a short-circuit (SC) and overload (OL) dual-protection scheme is proposed for overcurrent protection. A full design procedure and reliability analysis are given for SC circuit design. A novel OL circuit is proposed to protect OL faults at the gate-driver level. The protection procedure can detect an SC fault within 50 nanoseconds and protect the device within 1.1 microsecond. The proposed method is a simple and effective solution for the potential overcurrent problem of the SiC MOSFET. For SiC MOSFETs in series-connection, the unbalanced voltages can result in system failure due to device breakdown or unbalanced thermal stresses. By injecting current during the turn-off transient, an active dv/dt control method is used for voltage balancing. A 6 kV phase-leg using eight 1.7 kV SiC MOSFETs in series-connection has been tested with voltage balanced accurately. Modeling of the stacked SiC MOSFET with active dv/dt control is also done to summarize the design methodology for an effective and stable system. This method provides a low-loss and compact solution for overvoltage problems when MV SiC MOSFETs are connected in series. Furthermore, a scalable auxiliary power network is proposed to prevent gate failure caused by unstable gate voltage or EMI interference. The two-stage auxiliary power network (APN) architecture includes a wireless power transfer (WPT) converter supplied by a grounded low voltage dc bus, a high step-down-ratio (HSD) converter powered from dc-link capacitors, and a battery-based mini-UPS backup power supply. The auxiliary-power-only pre-charge and discharge circuits are also designed for a 6 kV power electronics building block (PEBB). The proposed architecture provides a general solution of a scalable and reliable auxiliary power network for the SiC-MOSFET-based MV converter. For the WPT converter, a multi-objective optimization on efficiency, EMI mitigation, and high voltage insulation capability have been proposed. Specifically, a series-series-CL topology is proposed for the WPT converter. With the optimization and new topology, a 120 W, 48 V to 48 V WPT converter has been tested to be a reliable part of the auxiliary power network. For the HSD converter, a novel unidirectional voltage-balancing circuit is proposed and connected in an interleaved manner, which provides a fully modular and scalable solution. A ``linear regulator + buck" solution is proposed to be an integrated on-board auxiliary power supply. A 6 kV to 45 V, 100 W converter prototype is built and tested to be another critical part of the auxiliary power network. / Doctor of Philosophy / The wide bandgap semiconductor enables next-generation power electronics systems with higher efficiency and higher power density which will reduce the space, weight, and cost for power supply and conversion systems, especially for renewable energy. However, by pushing the system voltage level higher to medium-voltage of tens of kilovolts, although the system has higher efficiency and simpler control, the reliability drops. This dissertation, therefore, focusing on solving the possible overcurrent, overvoltage, and gate failure issues of the power electronics system that is caused by the high voltage and high electromagnetic interference environment. By utilizing the inductance of the device, a dual-protection method is proposed to prevent the overcurrent problem. The overcurrent fault can be detected within tens of nanoseconds so that the device will not be destroyed because of the huge fault current. When multiple devices are connected in series to hold higher voltage, the voltage sharing between different devices becomes another issue. The proposed modeling and control method for series-connected devices can balance the shared voltage, and make the control system stable so that no overvoltage problem will happen due to the non-evenly distributed voltages. Besides the possible overcurrent and overvoltage problems, losing control of the devices due to the unreliable auxiliary power supply is another issue. This dissertation proposed a scalable auxiliary power network with high efficiency, high immunity to electromagnetic interference, and high reliability. In this network, a wireless power transfer converter is designed to provide enough insulation and isolation capability, while a switched capacitor converter is designed to transfer voltage from several kilovolts to tens of volts. With the proposed overcurrent protection method, voltage sharing control, and reliable auxiliary power network, systems utilizing medium-voltage wide-bandgap semiconductor will have higher reliability to be implemented for different applications.

With GaN and SiC switching devices becoming more commercially available, higher switching frequency is being applied to achieve higher efficiency and power density in power converters. However, electro-magnetic interference (EMI) becomes a more severe problem as a result. In this thesis, the switching frequency effect on conducted EMI noise is assessed. As EMI noise increases, the EMI filter plays a more important role in a power converter. As a result, an effective EMI modeling technique of the power converter system is required in order to find an optimized size and effective EMI filter. The frequency-domain model is verified to be an efficient and easy model to explore the EMI noise generation and propagation in the system. Of the various models, the unterminated behavioral model can simultaneously predict CM input and output noise of an inverter, and the prediction falls in line with the measurement around 10 MHz or higher. The DM terminated behavioral model can predict the DM input or output noise of the motor drive higher than 20 MHz. These two models are easy to extract and have high prediction capabilities; this is verified on a 10 kHz-switching-frequency Si motor drive. It is worthwhile to explore the prediction capability of the two models when they are applied to a SiC-based power inverter with switching frequency ranges from 20 kHz to 70 kHz. In this thesis, the CM unterminated behavioral model is first applied to the SiC power inverter, and results show that the model prediction capability is limited by the noise floor of the oscilloscope measurement. The proposed segmented-frequency-range measurement is developed and verified to be a good solution to the noise floor. With the improved impedance fixtures, the prediction from CM model matches the measurement to 30 MHz. To predict the DM input and output noise of the SiC inverter, the DM terminated behavioral model can be used under the condition that the CM and DM noise are decoupled. With the system noise analysis, the DM output side is verified to be independent of the CM noise and input side. The DM terminated behavioral model is extracted at the inverter output and predicts the DM output noise up to 30 MHz after solving the noise floor and DM choke saturation problem. At the DM input side, the CM and DM are seen to be coupled with each other. It is found experimentally that the mixture of the CM and DM noise results from the asymmetric impedance of the system. The mixed mode terminated behavioral model is proposed to predict the DM noise when a mixed CM effect exists. The model can capture the DM noise up to to 30 MHz when the impedance between the inverter to CM ground is not balanced. The issue often happens in extraction of the model impedance and is solved by the curving-fitting optimization described in the thesis. This thesis ends with a summary of contributions, limitations, and some future research directions. / Master of Science

Nanostructured ferritic alloy and silicon carbide composite materials (NFA-SiC) were sintered with spark plasma sintering (SPS) method and systematically investigated through X-ray diffraction (XRD), scanning electron microscopy (SEM), as well as density and Vickers hardness tests. Pure NFA, pure SiC, and their composites NFA-SiC with different compositions (2.5 vol% NFA-97.5 vol% SiC, 5 vol% NFA-95 vol% SiC, 97.5 vol% NFA-2.5 vol% SiC, and 95 vol% NFA-5 vol% SiC) were successfully sintered through SPS. In the high-NFA samples, pure NFA and NFA-SiC, minor gamma-Fe phase formation from the main alfa-Fe matrix occurred in pure NFA 950 degree C and 1000 degree C. The densities of the pure NFA and NFA-SiC composites increased with sintering temperature but decreased with SiC content. The Vickers hardness of the pure NFA and NFA-SiC composites was related to density and phase composition. In the high-SiC samples, NFA addition of 2.5 vol% can achieve full densification for the NFA-SiC samples at relative low temperatures. With the increase in sintering temperature, the Vickers hardness of the pure SiC and NFA-SiC composite samples were enhanced. However, the NFA-SiC composites had relative lower hardness than the pure SiC samples. A carbon layer was introduced in the NFA particles to prevent the reaction between NFA and SiC. Results indicated that the carbon layer was effective up to 1050 degree C sintering temperature. Green samples of gradient-structured NFA-SiC composites were successfully fabricated through slip casting of an NFA-SiC co-suspension. / Master of Science

As the oil industry continues to drill deeper to reach new wells, electronics are being required to operate at extreme pressures and temperatures. Coupled with substantial real-time data targets, the need for robust high speed electronics is quickly on the rise. This paper presents a high temperature wideband low noise amplifier (LNA) with zero temperature coefficient maximum available gain (ZTCMAG) biasing for a downhole communication system. The proposed LNA is designed and prototyped using 0.25μm GaN on SiC RF transistor technology, which is chosen due to the high junction temperature capability. Measurements show that the proposed LNA can operate reliably up to an ambient temperature of 230°C with a minimum noise figure (NF) of 2.0 dB, gain of 16.1 dB, and P1dB of 19.1 dBm from 230.5MHz — 285.5MHz. The maximum variation with temperature from 25°C to 230°C is 1.53dB for NF and 0.65dB for gain. / Master of Science

Over the past two decades, power consumption has increased exponentially worldwide, posing new challenges to power grids to meet the load requirements. With this growing power demand, the need for efficient high-density medium-voltage (MV) power converters has increased to support flexible power distribution grids. The modular multilevel converters (MMC) became the most typical MV power converters in applications from 2010. This topology has many advantages, such as voltage scalability, excellent output performance, and low voltage ratings for switching devices. However, without the excellent reliability of the MMC, applications cannot reap these benefits. The MMC topology comprises several series-connected submodules (typically a half-bridge or a full-bridge inverter). As a result of increased switching devices, the converter becomes vulnerable since a single device fault can disrupt the whole converter operation. Therefore, fault-tolerant strategies to replace faulty SM with a redundant SM are developed using additional bypass switches. Conventionally TRIACs and vacuum switches are employed as bypass switches that operate in the range of 2-10 microseconds. Despite having performance advantages, MMCs are still not fully employed in aerospace and naval industries due to their enormous size. Many Power Electronics Building Blocks (PEBB) are proposed, with size optimization, as submodules for modular converters. The PEBB1000, a 1000 V- PEBB proposed by Dr. Jun Wang, achieved a significant size reduction of 80% with a novel switching cycle control (SCC) scheme. This novel control scheme requires high switching frequency and high di/dt-currents for MMC operation. Due to di/dt-rate limitations, TRIAC-based switch cannot perform bypass operation. Therefore, research work has been conducted on bypass switches for PEBB1000 using wide-bandgap SiC devices. This thesis presents the design of a SiC MOSFET-based bypass switch for PEBB1000 in MMC application. A detailed fault case analysis is presented to show the feasibility of the bypass operation for 90% PEBB-level faults. Significant variations in PEBB1000 bypass requirements are observed through SCC-based MMC simulations. Accordingly, a 1700 V, 100 A bypass switch has been designed using the anti-series topology of MOSFETs. Various specifications, such as 142 nanoseconds operation time, 500 nanoseconds bypass commutation time, and 277A transient current conduction capability, are validated through practical tests. Results prove that SiC-MOSFETs work better than TRIACs in high di/dt-current conduction and operation times. For future work, false-triggering endurance has to be analyzed for 1000 V switching voltage. / Master of Science / When a building is on fire, the safety of people inside depends on the timely arrival of the fire rescue departments. Similarly, for an electrical fault, the safety of electrical systems depends on fast and secure fault protection devices. This thesis presents work on one such fault-protection device used in the power distribution grid: solid-state bypass switch. Distribution grids supply power majorly to households and industries at the city or state level. They employ medium-voltage (MV) converters to step down the voltages to meet the distribution requirements. In MV converters, several low-voltage modules are connected in series to achieve the high-voltage power conversion. When a fault occurs at one of the low-voltage modules in MV converters, power flow gets disrupted due to a series connection like a chain. Therefore, bypass switches are connected in parallel to low-voltage modules for an alternate power flow path. Conventionally used bypass switches have 2-10 microseconds operation time. Recent advancements in semiconductor devices, SiC MOSFETs, allow operation times less than one microsecond. Therefore, research work has been conducted on bypass switches using SiC MOSFETs. Finally, the SiC-MOSFET based bypass switch is built and tested according to converter requirements. Results proved that the designed switch operates in 142 nanoseconds, ten times faster than a conventional switch.

Silicon carbide (SiC) outperform Si chips in terms of high blocking voltage capability, low on-resistance, high-temperature operation, and high switching frequency. Several SiC MOSFETs are usually paralleled to increase current capability, considering cost effectiveness and manufacturability. For a SiC power module with current rating higher than 100 A, high did/dt and dvds/dt could possibly cause cross-turn-on (crosstalk-induced turn-on) through the gate-to-drain capacitance Cgd of the MOSFET dies and the package inductances. Mismatches in threshold voltage (Vth) up to 33% have been observed among paralleled SiC MOSFETs. This leads to unbalanced transient peak currents and switching energies. Both cross-turn-on and current unbalance degrade the reliability of a power module. Increasing the immunity to cross-turn-on while maintaining the similar switching energies and balancing the transient peak currents below 10% without sacrificing the voltage stress are the goals of this work. Development of a SPICE model free of non-convergence – A simulation model for a SiC power module is necessary for evaluations of cross-turn-on and current unbalance; however, most SiC power modules do not have models. No existing modeling methods discuss how to build an accurate SPICE model that is free of non-convergence when hundreds of parasitic inductances are present. A modeling process is introduced for paralleled MOSFETs encapsulated in a power module that gives access to both the internal channel current and voltage of each bare die inside the package. This model is free of non-convergence and accurate. Parasitic ac resistances, dc resistances, and ac inductances are extracted by Q3D Extractor. Non-convergence is avoided by including the ac resistance of the conduction trace in the model. Also, a series model which is set default in Q3D Extractor is converted to parallel model to accurately reflect how the current flows through the dc and ac resistances of the trace. A complete SPICE model of a commercial SiC power module was derived and validated by experiments. The error between predicted turn-on peak current of the developed model and that of the experimental data is 2%, significantly lower than the 28% difference between prediction result of commercial model and experimental data. Detection of internal cross-turn-on – Terminal current of a power module does not reflect the internal channel current due to the numerous parasitic inductances of the package. No existing method is able to detect the cross-turn-on in a power module since dies are usually encapsulated and the channel currents are hard to measure. A nonintrusive method to identify cross-turn-on based on the changing ringing current is developed. The detection method was analyzed theoretically and validated by experiments using a 1.2-kV SiC module. The negative drive voltage and gate resistance for safe operation can be determined by the detection method. Influence of layout symmetry on immunity to cross-turn-on – Gate resistance, gate-to-drain capacitance of the MOSFET, slew rate of drain-to-source voltage, and temperature have been recognized as the only elements impacting the immunity to cross-turn-on for a single chip and module. Layout symmetry is newly discovered to be another factor that contributes to the immunity. Asymmetrical and symmetrical modules following commercial layouts were tested by a double pulse tester. The peak cross-turn-on currents, high-side switching energy, and total switching energy at various input voltages, low-side gate resistances, and load currents are normalized for comparison. The peak cross-turn-on current of the symmetrical module is 84% lower than that of the asymmetrical module at nominal condition. Longer power-loop and gate-drive loop are required to achieve symmetrical layout for more than two dies in parallel. This increases the low-side switching energy of the symmetrical module. The total switching energies of the two modules are similar. In this case, a symmetrical layout is still recommended since current stress caused by cross-turn-on is much smaller in symmetrical module than in the asymmetrical module and chances to have shoot-through between the high side and the low side are reduced. Magnetic integration into a power module for current balancing – Existing power modules do not have balanced transient currents when threshold voltage mismatch exists. A module with integrated coupled inductors was designed, fabricated, and validated to be effective to balance the currents without sacrificing voltage stress and switching energy. The designed integrated coupled inductors achieve inverse coupling by utilizing the copper trace of the substrate and bond wires and have the following features: size comparable to the silicon carbide (SiC) die, coupling coefficient higher than 0.98, tens of nH operating at tens of MHz, and current rating of tens of Amperes. The coupled inductors with the magnetic material of low-temperature co-fired ceramics (LTCC) are compatible with existing packaging technology for module fabrication. The effectiveness of reducing transient-current mismatch at various input voltages, load currents, and gate resistances was verified by experiments. Compared with the baseline module following commercial practice, the module with integrated coupled inductors reduces current unbalance from 36% to 6.4% and turn-on-energy difference from 28% to 2.6% while maintaining the same total switching energy and a negligible change of voltage stress. / Ph. D. / A silicon carbide (SiC) power module with high di_d/dt and dv_ds/dt could possibly cause crossturn-on (crosstalk-induced turn-on) through the gate-to-drain capacitance C_gd of the MOSFET dies and package inductances. Mismatches in threshold voltage (V_th) up to 33% have been observed among paralleled SiC MOSFETs. This leads to unbalanced transient peak currents. Both crossturn-on and current unbalance degrade the reliability. Increasing the immunity to cross-turn-on while maintaining the similar switching energies and balancing the transient peak currents below 10% without sacrificing the voltage stress are the goals of this work. The development of a SPICE model for a SiC power module is necessary for evaluations of cross-turn-on and current unbalance; however, no existing modeling methods discuss how to build an accurate SPICE model of a power module free of non-convergence when hundreds of parasitic inductances are present. The modeling method to overcome these challenges is introduced. The error between predicted turn-on peak current of the developed model and that of the experimental data is 2%, significantly lower than the 28% difference between prediction result of commercial model and experimental data. No existing method is able to detect the cross-turn-on in a power module since the dies are usually vi encapsulated and the channel currents are hard to measure. A nonintrusive method to identify the cross-turn-on based on the changing ringing current is developed. The detection method was analyzed theoretically and validated by experiments using a 1.2-kV SiC module. Layout symmetry is newly discovered to be another factor that contributes to the immunity. The peak cross-turn-on current of the symmetrical module is 84% lower than that of the asymmetrical module at nominal condition. The symmetrical layout greatly decreases cross-turn-on currents without increasing total switching energy. Power modules in the market cannot have balanced transient currents when mismatches in threshold voltage V_th exist. A module with integrated coupled inductors was designed, fabricated, and validated to be effective to balance the currents with the presence of V_th mismatch. Compared with the baseline module following commercial practice, the module with integrated coupled inductors reduces current unbalance from 36% to 6.4% and turn-on-energy difference from 28% to 2.6% while maintaining the same total switching energy and negligible change of voltage stress.

Numerous power electronics building blocks (PEBB) based power conversion systems have been developed to explore modular design, scalable voltage and current ratings, low-cost operations, etc. This paper further extends the modular concept from the power stage to the control system. The communication network in SiC-based modular power converters is becoming significant for distributed control architecture, with the requirements of tight synchronization and low latency. The influence of the synchronization accuracy on harmonics under the phase-shifted carrier pulse width modulation (PSC-PWM) is evaluated. When the synchronization is accurate, the influence of an increase in harmonics can be ignored. Thus, a synchronous distributed control and communication protocol with well-performed synchronization of 25 ns accuracy is proposed and verified for a 120 kHz SiC-based impedance measurement unit (IMU) with cascaded H-bridge PEBBs. An improved synchronization method with additional analog circuits is further implemented and verified with sub-ns synchronization accuracy. / The power electronics building block (PEBB) concept is proposed for medium-voltage converter applications in order to realize the modular design of the power stage. Traditionally, the central control architecture is popular in converter systems. The voltage and current are sensed and then processed in one central controller. The control hardware interfaces and software have to be customized for a specified number of power cells, and the scalability of controller is lost. In stead, in the distributed control architecture, a local controller in each PEBB can communicate with the sensors, gate drivers, etc. A high-level controller collects the information from each PEBB and conducts the control algorithm. In this way, the design can be more modular, and the local controller can share the computation burden with the high-level controller, which is good for scalability. In such distributed control architecture, a synchronous communication system is required to transmit data and command between the high-level controller and local controllers. A power converter always requires a highly synchronized operation to turn on or turn off the devices. In this work, a synchronous communication protocol is proposed and experimentally validated on a SiC-based modular power converter.

Nowadays, major public concern is concentrated on reducing the usage of fossil fuels and reducing emissions of CO₂ by different energy advancement. Electric vehicle technology presents extremely effective way of reducing carbon emissions and paves the way of having sustainable and renewable energy future. In order to wear the cost of electric vehicles down, batteries have to be improved as well as higher power density and high reliability has to be achieved. This research work mainly focuses on achieving higher power density and higher reliability of the inverter stage by utilizing wide-bandgap SiC MOSFET semiconductor devices in electric vehicle application. In order to achieve higher reliability of the inverter stage, high bandwidth, high performance Rogowski coil switch current sensors are employed. These sensor were embedded on the PCB and integrated on the gate driver. High bandwidth switch current sensor measurement is used for fast short-circuit detection and protection of the SiC MOSFET semiconductor switches. Furthermore, comparison with conventional detection and protection method used in automotive IGBT applications is shown where novel protection showed superior performance. This thesis also shows principle of how to obtain phase currents of the system using Rogowski coil switch current sensor measurements. Digital reconstruction principle is employed to obtain the phase currents. Accurate and linear current sensor is achieved. By successfully realizing this integrated phase current measurement on the gate driver, elimination of the commercial current sensors from the system is possible. By eliminating existing phase current sensors, higher power density could be achieved. Sensor is evaluated in both continuous and discontinuous PWM schemes. / Master of Science / Together with renewable sources, electric vehicle will play an important role as a part of sustainable and renewable energy future by significantly reducing emissions of CO₂ into the atmosphere. In order to make electric cars more acceptable and accessible and make a significant impact on the environment, cost must be lowered down. To wear the cost of the electric vehicles down, powertrain of the car must be significantly improved and made smaller as well as lighter. This thesis mainly focuses on improving the reliability of the motor driving stage by implementing novel protection during fault periods such as short-circuit event. Furthermore, this novel protection allows current sensing that is crucial for motor control during normal operation periods. This will enable more compact motor driving stage since existing current sensing elements can be eliminated.