The main focus of the present work was the Ge-rich part of the binary Ba – Ge system, in which by inspecting the behavior of the clathrate-I Ba8Ge43 under pressure, several new phases were found. The new phases in this system have the following compositions: BaGe3 (with two modifications), BaGe5, BaGe5.5 and BaGe6, therefore they are quite close in composition range: 75% - ~85% at. Ge. Concerning the conditions required for the synthesis of each phase, several combinations of temperature and pressure were employed in order to find a stability range. It was possible to establish such a formation range for all phases. In some cases two phases were found for a given conditions and in many other cases three or more phases were found to coexist. Thus, the stability range of pressure and temperature for single phase formation turned out to be very narrow. By inspecting of some structural features, for instance the interatomic distances, it is found that the average of the Ge – Ge distances change in line with the composition, i.e. the shorter contacts belong to BaGe6 while the longer distances are present in BaGe3 (both modification). An opposite trend is observed for the calculated density of each phase (neglecting the tI32 form of BaGe3): the lower density is found for BaGe3 and the denser compound is found to be BaGe6. Of course this is not coincidence, since due to the Ge content, BaGe6 has the largest molar mass. Similarly, by examining the density as a function of the interatomic distance. In such case, the denser compound is characterized by shorter Ge – Ge contacts, while the less dense phase holds the longest Ge – Ge contacts. This is in agreement with the building motifs within each crystal structure: columns in BaGe3 (open framework) passing through layers in BaGe5, ending in a three-dimensional network (closed framework) in BaGe6.

Cette thèse porte sur l'étude des phénomènes qui se produisent lors de la réaction métal-silicium (siliciuration) en couches minces et dans des nanofils. En effet, les phénomènes tels que la germination, la croissance latérale, la croissance normale et la diffusion doivent être compris pour réaliser les contacts des futurs dispositifs de la microélectronique. La comparaison entre la siliciuration en couches minces et dans les nanofils est l'un des principaux aspects de ce travail. La distribution atomique en 3D des éléments chimiques dans les différentes siliciures de Ni a été obtenue par sonde atomique tomographique (SAT). Pour permettre l'analyse par SAT de différents types des nanofils à base de silicium, plusieurs méthodes originales de préparation des échantillons par faisceau d'ions focalisés ont été développées et testées. D'autre part, des mesures in situ et en temps réel de diffusion réactive par diffraction de rayons X ont permis de mettre en évidence l'importance de la germination dans la formation des phases et de déterminer les cinétiques de formation des siliciures de Ni allié en Pt, notamment des régimes de réaction aux interfaces et de croissance latérale. La forme caractéristique associée à la croissance latérale a été déterminée par des analyses ex situ de microscopie électronique en transmission et comparée aux modèles existants. La détermination par SAT de l'espèce qui diffuse majoritairement donne aussi des indications sur les mécanismes de formation des phases et de relaxation des contraintes dans les siliciures. / This thesis focuses on the phenomena that occur during the reaction between metal and silicon (silicide) on thin films and nanowires. Indeed, phenomena such as nucleation, lateral growth, normal growth and diffusion must be understood to make contacts for future microelectronic devices. The comparison between the silicide formation on thin films and nanowires is one of the main aspects of this work. Atomic distribution in 3D for the elements in different Ni silicide phase was obtained by atom probe tomography (APT). To enable the analysis of different types of silicon nanowires by APT, several original methods for sample preparation by focused ion beam has been developed and tested. On the other hand, in situ and real-time analysis by X-ray diffraction during the reactive diffusion helped to highlight the importance of the nucleation of a phase and to determine the kinetics of formation of Ni(Pt) silicides, including the reaction on the interfaces and the lateral growth. The characteristic shape associated with the lateral growth was determined by ex-situ transmission electron microscopy analyzes and was compared with the existing theoretical models. Moreover, the determination of the fastest diffusing species by APT provided information on the mechanisms of phase formation and stress relaxation in the silicide.

A demanda por combustível nuclear para reatores de pesquisa está aumentando em nível mundial, enquanto várias de suas fábricas têm pequeno volume de produção. Este trabalho estabeleceu um modelo conceitual com duas estratégias para o aumento da capacidade produtiva dessas fábricas. Foram abordadas as fábricas que produzem elementos combustíveis tipo placa carregados com LEU U3Si2-Al, tipicamente usados em reatores nucleares de pesquisa. A primeira estratégia baseia-se na literatura da área de administração da produção e é uma prática frequente nas fábricas em geral. A segunda estratégia aproveita a possibilidade de desmembrar setores produtivos, comum em instalações de produção de combustível nuclear. Ambas as estratégias geraram diferentes cenários de produção, os quais devem ser seguros em relação à criticalidade. Foram coletados dados de uma fábrica real de combustível nuclear para reatores de pesquisa. As duas estratégias foram aplicadas a esses dados com a finalidade de testar o modelo proposto, o que configurou um estudo de caso. A aplicação das estratégias aos dados coletados deu-se por meio de simulação de eventos discretos em computador. Foram criados diversos modelos de simulação para abranger todos os cenários gerados, de forma que o teste indicou um aumento da capacidade produtiva de até 207% sem necessidade de aquisição de novos equipamentos. Os resultados comprovam que o modelo atingiu plenamente o objetivo proposto. Como principal conclusão pode-se apontar a eficácia do modelo proposto, fato que foi validado pelos dados da fábrica. / Although many nuclear fuel factories have small production volumes, the demand for nuclear fuel for research reactors is increasing worldwide. This work established a conceptual model with two strategies to increase the production capacity of these factories. We addressed factories that produce plate-type fuel elements loaded with LEU U3Si2-Al, which are typically used in nuclear research reactors. The first strategy is based on production management literature and is a regular practice in general manufacturing plants. The second strategy takes advantage of the fact that productive sectors can be separated in nuclear fuel production facilities. Both strategies have generated different production scenarios that are assumed to be safe in relation to nuclear criticality. We collected data from a real plant that produces nuclear fuel for research reactors and applied the model to that data, aiming to test the proposed model by setting up a case study. Through the use of computer software, we applied the two strategies to this data by means of discrete events simulation and created several simulation models in order to cover all generated scenarios. Our tests indicated an increase of up to 207% in productive capacity without the need of acquiring new equipment, thus showing that the model has fully achieved its proposed objective. One of the main conclusions that we point out is the models effectiveness, which was validated by the factory data.

L'objectif de cette étude est de comprendre l'influence du silicium sur la microstructure d'alliages base TiAl. En effet, de faibles additions de silicium peuvent améliorer la tenue à chaud de ces intermétalliques. Nous montrons que le silicium a tendance à ségréger fortement durant la solidification, à l'échelle microscopique, provoquant l'apparition de siliciures primaires dans les zones interdendritiques. Après étude de cette ségrégation, nous avons procédé à des traitements thermiques d'homogénéisation afin d'étudier quantitativement les transformations solide-solide ayant lieu dans ces alliages. Ainsi, nous avons pu observer la précipitation de siliciures aux interfaces gamma/alpha2 dans des structures lamellaires homogènes. Mais, la structure lamellaire tend à se modifier en même temps que les siliciures germent et croissent. Les liens entre ces deux transformations simultanées sont mis en évidence expérimentalement, avant d'être modélisés à partir d'hypothèses simples. La réalisation d'essais mécaniques sur des microstructures contrôlées permet, en guise de conclusion, de donner des tendances quant à l'influence du silicium sur le comportement à chaud des alliages TiAl / The goal of this study is the understanding of the influence of silicon on the microstructure of TiAl-based alloys. Small additions of silicon are actually known to improve the heat resistance of these intermetallics. It is shown here that silicon segregates strongly at the microscopic scale during solidification, leading to the apparition of primary silicides in the interdendritic regions. After a study of this segregation, homogenization heat treatments were performed in order to focus on a quantitative study of the solid-solid transformations occuring in these alloys. Thus, silicide precipitation was observed at the gamma/alpha2 interfaces in homogeneous lamellar structures. However, the lamellar structure undergoes its own evolution as the silicides nucleate and grow. The links between these simultaneous transformations are shown by our experimental results, then modelled through simple considerations. As a conclusion, mechanical tests on controlled microstructures give some trends on the influence of silicon on the high temperature mechanical properties of TiAl alloys

The steady and aggressive downscaling of the physical dimensions of the conventional metal-oxide-semiconductor field-effect-transistor (MOSFET) has been the main driving force for the IC industry and information technology over the past decades. As the device dimensions approach the fundamental limits, novel double/trigate device architecture such as FinFET is needed to guarantee the ultimate downscaling. Furthermore, Schottky barrier source/drain technology presents a promising solution to reducing the parasitic source/drain resistance in the FinFET. The ultimate goal of this thesis is to integrate Schottky barrier source/drain in FinFETs, with an emphasis on process development and integration towards competitive devices. First, a robust sidewall transfer lithography (STL) technology is developed for mass fabrication of Si-nanowires in a controllable manner. A scalable self-aligned silicide (SALICIDE) process for Pt-silicides is also developed. Directly accessible and uniform NWs of Ni- and Pt-silicides are routinely fabricated by combining STL and SALICIDE. The silicide NWs are characterized by resistivity values comparable to those of their thin–film counterparts. Second, a systematic experimental study is performed for dopant segregation (DS) at the PtSi/Si and NiSi/Si interfaces in order to modulate the effective SBHs needed for competitive FinFETs. Two complementary schemes SIDS (silicidation induced dopant segregation) and SADS (silicide as diffusion source) are compared, and both yield substantial SBH modifications for both polarities of Schottky diodes (i.e. φbn and φbp). Third, Schottky barrier source/drain MOSFETs are fabricated in UTB-SOI. With PtSi that is usually used as the Schottky barrier source/drain for p-channel SB-MOSFETs, DS with appropriate dopants leads to excellent performance for both types of SBMOSFETs. However, a large variation in position of the PtSi/Si interface with reference to the gate edge (i.e., underlap) along the gate width is evidenced by TEM. Finally, integration of PtSi NWs in FinFETs is carried out by combining the STL technology, the Pt-SALICIDE process and the DS technology, all developed during the course of this thesis work. The performance of the p-channel FinFETs is improved by DS with B, confirming the SB-FinFET concept despite device performance fluctuations mostly likely due to the presence of the PtSi-to-gate underlap. / QC 20100923

Silizide spielen ein wesentliche Rolle in den technologisch fortschrittlichsten CMOS Bauteilen. Sie finden Verwendung als Kontaktmaterial auf den Aktivgebieten und dem Silizium Gatter von Transistoren. Diese Arbeit beschäftigt sich mit den Systemen: Co-Si, Co-Ni-Si und Ni-Si. Sowohl in situ Hochtemperatur-SR-XRD Experimente als auch CBED wurden zur Phasenidentifikation herangezogen. AES erlaubte es, Elementverteilungen in Schichtstapeln zu bestimmen. Für Studien über Agglomerationserscheinungen wurde REM eingesetzt. TEM und analytisches TEM trugen nicht nur zu Einblicken in Schichtstrukturen und Kornformen bei, sondern lieferten auch Daten zu Elementverteilungen in Silizidschichten. Diese Dissertation gliedert sich in zwei Hauptteile. Der erste Teil beschäftigt sich mit den Phasenbildungsabfolgen und den Phasenbildungs- und Umwandlungstemperaturen in nanoskaligen dünnen Schichten. Als Trägermaterial wurden einkristalline und polykristalline Siliziumsubstrate verwendet. Der Einfluß verschiedener Dotierungen im Vergleich zu undotierten Substraten sowie die Beeinflussung der Silizidierung durch eine Deckschicht wurden untersucht. Im zweiten Teil waren Größeneffekte verschiedener Schichtdicken und Agglomerationserscheinungen Gegenstand von Untersuchungen. Unterschiede bei der Silizidierung in Zusammenhang mit unterschiedlichen Schichtdicken wurden bestimmt. Darüberhinaus wurde eine ternäre CoTiSi Phase gefunden und identifiziert. Außerdem konnte die stark eingeschränkte Mischbarkeit der Monosilizide CoSi und NiSi gezeigt werden. Der thermische Ausdehnungskoeffizient von NiSi im Temperaturbereich 400?700°C und sein nicht-lineares Verhalten wurden bestimmt. / Silicides are an essential part of state-of-the-art CMOS devices. They are used as contact material on the active regions as well as on the Si gate of a transistor. In this work, investigations were performed in the systems Co-Si, Co-Ni-Si, and Ni-Si. In situ high temperature SR-XRD and CBED techniques were used for phase identification. AES enabled the determination of elemental concentrations in layer stacks. SEM was applied to agglomeration studies. TEM imaging and analytical TEM provided insights into layer structures, grain morphology as well as information about the distribution of chemical elements within silicide layers. This thesis is divided into two main parts. The first part deals with the phase formation sequences and the phase formation and conversion temperatures in nanoscale thin films on either single crystal or polycrystalline Si substrates. The effect of different types of dopants vs. no doping and the impact of a capping layer on the phase formation and conversion temperatures were studied. In the second part, size effects and agglomeration of thin silicide films were investigated. The effect of different layer thicknesses on the silicidation process was studied. Additionally, the degree of agglomeration of silicide films was calculated. Furthermore, the ternary CoTiSi phase was found and identified as well as the severely limited miscibility of the monosilicides CoSi and NiSi could be shown. The CTE of NiSi between 400?700 ±C and its non-linear behavior was determined.

Les siliciures métalliques constituent un élément crucial des contacts électriques des transistors que l'on retrouve au coeur des circuits intégrés modernes. À mesure qu'on réduit les dimensions de ces derniers apparaissent de graves problèmes de formation, liés par exemple à la limitation des processus par la faible densité de sites de germination. L'objectif de ce projet est d'étudier les mécanismes de synthèse de siliciures métalliques à très petite échelle, en particulier le NiSi, et de déterminer l’effet de l’endommagement du Si par implantation ionique sur la séquence de phase. Nous avons déterminé la séquence de formation des différentes phases du système Ni-Si d’échantillons possédant une couche de Si amorphe sur lesquels étaient déposés 10 nm de Ni. Celle-ci a été obtenue à partir de mesures de diffraction des rayons X résolue en temps et, pour des échantillons trempés à des températures critiques du processus, l’identité des phases et la composition et la microstructure ont été déterminées par mesures de figures de pôle, spectrométrie par rétrodiffusion Rutherford et microscopie électronique en transmission (TEM). Nous avons constaté que pour environ la moitié des échantillons, une réaction survenait spontanément avant le début du recuit thermique, le produit de la réaction étant du Ni2Si hexagonal, une phase instable à température de la pièce, mélangée à du NiSi. Dans de tels échantillons, la température de formation du NiSi, la phase d’intérêt pour la microélectronique, était significativement abaissée. / Currently metal silicide constitutes a crucial component in the formation of electrical contacts for transistors that forms the heart of modern day integrated circuits. As we reduce the dimensions of the latter, we are faced with serious problems of formation, related for example to the process limitation due to the weak density of germination sites. The objective of this project is to study at small scale the synthesis mechanisms of metal silicide, in particular NiSi, and to determine the effect of Si implantation damage on the phase sequence. We have determined the different phase sequences of the Ni-Si system for samples composed of a 10 nm Ni surface layer deposited on a-Si. These were obtained by time resolved x-ray diffraction (TR-XRD) measurements. As for samples quenched at critical temperatures we identified the different phases, their composition and their microstructure were determined by pole figures, Rutherford back scattering (RBS) spectrometry and transmission electron microscopy (TEM). We noted that for approximately half the samples, a spontaneous reaction happened before annealing. The result of the reaction was hexagonal Ni2Si, a phase unstable at room temperature, mixed with NiSi. In theses samples, the temperature of formation for the phase of interest, the NiSi, was lower.

As scaling of CMOS technology continues, the control of parasitic source/drain (S/D) resistance (RSD) is becoming increasingly challenging. In order to control RSD, metallic source/drain MOSFETs have attracted significant attention, due to their low resistivity, abrupt junction and low temperature processing (≤700 °C). A key issue is reducing the contact resistance between metal and channel, since small Schottky barrier height (SBH) is needed to outperform doped S/D devices. A promising method to decrease the effective barrier height is dopant segregation (DS). In this work several relevant aspects of Schottky barrier (SB) contacts are investigated, both by simulation and experiment, with the goal of improving performance and understanding of SB-MOSFET technology:First, measurements of low contact resistivity are challenging, since systematic error correction is needed for extraction. In this thesis, a method is presented to determine the accuracy of extracted contact resistivity due to propagation of random measurement error.Second, using Schottky diodes, the effect of dopant segregation of beryllium (Be), bismuth (Bi), and tellurium (Te) on the SBH of NiSi is demonstrated. Further study of Be is used to analyze the mechanism of Schottky barrier lowering.Third, in order to fabricate short gate length MOSFETs, the sidewall transfer lithography process was optimized for achieving low sidewall roughness lines down to 15 nm. Ultra-thin-body (UTB) and tri-gate SB-MOSFET using PtSi S/D and As DS were demonstrated. A simulation study was conducted showing DS can be modeled by a combination of barrier lowering and doped Si extension.Finally, a new Schottky contact model was implemented in a multi-subband Monte Carlo simulator for the first time, and was used to compare doped-S/D to SB-S/D for a 17 nm gate length double gate MOSFET. The results show that a barrier of ≤ 0.15 eV is needed to comply with the specifications given by the International Technology Roadmap for Semiconductors (ITRS). / QC 20111206

Valoriser l'énergie perdue sous forme de chaleur par les moteurs thermiques en électricité via desgénérateurs thermoélectriques permettrai de diminuer l'empreinte carbone des transports routiers. Unesélection des matériaux basée sur des critères de performance, de coût et de développement durable aconduit au choix du siliciure de manganèse MnSi (semi-conducteur de type p). En s'appuyant sur uneapproche couplant la métallurgie et la chimie du solide, ce travail revisite l'état de l'art sur ces alliageset révèle les relations entre la structure (inco/commensurabilité), la microstructure et le procédé. Unemeilleure compréhension de ces liens a permis d'acquérir un contrôle plus précis des microstructures,et par conséquent d'optimiser les propriétés thermoélectriques, et a conduit à la mise au point d'unenouvelle voie de synthèse pour MnSi. De plus, la production de matériaux purs et texturés a permisde mettre en évidence l'isotropie des propriétés de transport de la phase MnSi. Enfin, cette étudesuggère une relation entre la texture des joints de grains et la ségrégation dans des alliages dopés,ouvrant de nouvelles perspectives pour améliorer les propriétés thermoélectriques. / Generating electricity from waste heat by means of thermoelectric generators may represent a very interestingopportunity to significantly reduce the impact of road transportation. In this context, HigherManganese Silicide (HMS) based alloys are studied as p-type semiconductors to achieve a sustainablescale-up of this technology. Through a strategy coupling metallurgy and solid state chemistry, thiswork revisits the knowledge on HMS and reveals the relationship between the phases, the microstructureand the manufacturing process. This systematic study has lead to the establishment of designguidance to maximize the performance and thus, to a new synthesis route. In addition, the productionof grain oriented and highly pure HMS materials evidences the isotropy of the transport properties ofHMS. Finally, this study suggests a relationship between grain boundary texture and segregation indoped-HMS, opening new directions for enhancing thermoelectric properties.

Une alternative à la réduction des dimensions caractéristiques des transistors est la 3D séquentielle. L’intégration 3D séquentielle requiert la fabrication de plusieurs niveaux de composant directement les uns au dessus des autres. Les procédés de fabrication utilisables pour les niveaux supérieurs sont limités par le budget thermique maximal que peuvent supporter les niveaux inférieurs. Pour la technologie FDSOI cette limite est fixée entre 500 °C et 550°C, 5 h dépendant de la siliciuration utilisée. Malgré le travail fourni pour réduire le BT des procédés de fabrication du transistor FDSOI, il est difficile d’atteindre cette limite pour certaines étapes, comme l’épitaxie des sources et drains surélevés. Dans ce contexte, cette thèse propose d’étudier et d’améliorer la stabilité thermique des niveaux bas, c’est à dire des transistors FDSOI et des niveaux de routages intermédiaires. L’étude de stabilité thermique du transistor FDSOI a permis d’identifier le siliciure comme étant l’élément le plus sensible aux budgets thermiques. Sa détérioration entraîne la dégradation de la résistance d’accès du transistor et favorise la diffusion du siliciure dans le canal. L’utilisation du Ni0.90Pt0.10 est limitée à 500 °C, 5 h, celle du Ni0.85Pt0.15 à 550 °C, 5 h. En alternative au NiPt, un nouveau siliciure a été étudié : le Ni0.90Co0.10. Afin de repousser sa stabilité thermique à 600 °C, 2 h, son intégration a dû être couplée à deux facteurs d’améliorations : l’amorphisation partielle des sources et drains par implantation et l’intégration d’un film de silicium intrinsèque epitaxié au-dessus des sources et drains composés de Si0.70Ge0.30. Les effets de ces différents « boosters » ont ainsi été analysés et expliqués. Pour la première fois, les avancées obtenues ont été implémentées sur des dispositifs FDSOI du noeud 14 nm. Ce premier essai est concluant car des performances identiques aux transistors pMOS fabriqués avec le siliciure Ni0.85Pt0.15, étudié depuis les années 2000, ont été obtenues. Néanmoins, la stabilité thermique évaluée sur transistor Ni0.90Co0.10 reste à améliorer. L’intégration de niveaux de routage entre les niveaux de transistors requiert des matériaux thermiquement stables et peu contaminants. Dans cette optique, la stabilité thermique d’une liste de diélectriques a été étudiée et caractérisée principalement par ellipsométrie, FTIR et ellipsométrie-porosimértie. Ainsi des couples isolant/barrière ont pu être déterminés pour chaque budget thermique appliqué entre 500 °C et 600 °C, 2 h. En ce qui concerne le métal intermédiaire, le tungstène a été étudié comme matériau conducteur, en plus du cuivre, en raison de son caractère moins contaminant. Ces deux matériaux ont montré une bonne stabilité thermique : jusqu’à 500 °C, 2 h pour le cuivre et 550 °C, 5 h pour le tungstène. Cependant, la résistance d'une ligne en cuivre est six fois moins résistante d'une ligne en tungstène. Cette valeur pourra être abaissée dans le cas de l’utilisation d’une nouvelle barrière en tungstène sans fluore qui a été étudiée et intégrée avec succès. Pour finir, la fiabilité du diélectrique à l’état de l’art, le SiOCH poreux, a été analysé dans des structures intégrant des lignes en tungstène. Dans ces conditions, la durée de vie du diélectrique est estimée à 1e16 années. Malgré la diminution de cette valeur après budget thermique à 600 °C, 2 h, (1e7 années), celle-ci reste bien supérieure à celle du cuivre dans des conditions identiques. / The 3D sequential integration is a smart alternative to planar device scaling. In this integration, the stacked transistors are processed sequentially, thus implying the reduction of the top thermal budget processes in order to preserve the bottom levels. For the FDSOI technology, the maximum thermal budget is set at 500 °C, 2 h. Despite the work done to reduce the thermal budget of the FDSOI processes, it is difficult to comply with this limit, as for example for the epitaxial raised source and drain which would need a thermal budget limit relaxation. In the frame of this Ph.D work, the thermal stability of the FDSOI transistors and the intermediate Back-End-Of-Line have been studied and optimized. The FDSOI transistor silicide has been identified as the most sensitive element to the thermal budget. Its degradation imply the access resistance degradation and favor the diffusion of the silicide into the channel. For this purpose, the Ni0.90Co0.10 silicide has been studied. To increase its thermal stability up to 600 °C, 2 h, two enhancers have been integrated: the pre-amorphization implant and the integration of a silicon capping over the Si0.70Ge0.30 source and drain. The effects of these enhancers on the thermal stability have been analyzed and understood. In addition to those, the Ni0.90Co0.10 has been integrated for the first time on 14 nm node FDSOI transistors. This first attempt is positive: identical performances on pMOS transistors have been obtained with Ni0.90Co0.10 silicide compare to Ni0.85Pt0.15 silicide, which is studied since the 2000’s. However, the improvement of thermal stability is not yet achieved on FDSOI transistors with Ni0.90Co0.10 silicide. Concerning the stability of the intermediate BEOL, the stability of dielectrics has first been studied and characterized by ellipsometry, FTIR and ellipsometric–porosimetry. Thus, insulating/barrier pairs have been defined for each thermal budget between 500 °C and 600 °C, 2 h. The metal lines have been studied using a 28nm node layout. Due to its limited contaminant characteristic, tungsten has been analyzed in addition to copper. Both materials show a good thermal stability: 500 °C, 2 h for copper and 550 °C, 5 h for tungsten despite the higher resistivity of tungsten. A factor 6 has been measured between these two materials. The resistance of a tungsten line has been improved by the integration of a new barrier. Finally, the state of the art Back-End-Of-Line dielectric reliability, the porous SiOCH, has been studied, function of the thermal budget, in structure integrated tungsten metal lines. In these conditions, the dielectric lifetime is estimated at 1e16 years. Despite its reduction due to thermal budget at 600 °C, 2 h (1e7 years), the tungsten lifetime estimation remains higher than the one obtained with copper lines without thermal budget.