This work investigates the voltage scaling feasibility of several low voltage SiC MOSFET modules operated as a single series-connected switch using active gate control. Both multilevel and two-level topologies are capable of achieving higher blocking voltages in high-power converter applications. Compared to multilevel topologies, two-level switching topologies are of interest due to less complex circuitry, higher density, and simpler control techniques. In this work, to balance the voltage between series-connected MOSFETs, device turn-off speeds are dynamically controlled on active gate-drivers using active gate control. The implementation of the active gate control technique (specifically, turn-off dv/dt control) is described in this thesis. Experimental results of the voltage balancing behavior across eight 1.7 kV rated SiC MOSFET devices in series (6 kV total dc bus voltage) with the selected active dv/dt control scheme are demonstrated. Finally, the voltage balancing performance and switching behavior of series-connected SiC MOSFET devices are discussed. / Master of Science / According to ABB, 40% of the world's power demand is supplied by electrical energy. Specifically, in 2018, the world's electrical demand has grown by 4% since 2010. The growing need for electric energy makes it increasingly essential for systems that can efficiently and reliably convert and control energy levels for various end applications, such as electric motors, electric vehicles, data centers, and renewable energy systems. Power electronics are systems by which electrical energy is converted to different levels of power (voltage and current) depending on the end application. The use of power electronics systems is critical for controlling the flow of electrical energy in all applications of electric energy generation, transmission, and distribution. Advances in power electronics technologies, such as new control techniques and manufacturability of power semiconductor devices, are enabling improvements to the overall performance of electrical energy conversion systems. Power semiconductor devices, which are used as switches or rectifiers in various power electronic converters, are a critical building block of power electronic systems. In order to enable higher output power capability for converter systems, power semiconductor switches are required to sustain higher levels of voltage and current. Wide bandgap semiconductor devices are a particular new category of power semiconductors that have superior material properties compared to traditional devices such as Silicon (Si) Insulated-Gate Bipolar Junction Transistors (IGBTs). In particular, wide bandgap devices such as Silicon Carbide (SiC) Metal Oxide Semiconductor Field Effect Transistors (MOSFETs) have better ruggedness and thermal capabilities. These properties provide wide bandgap semiconductor devices to operate at higher temperatures and switching frequencies, which is beneficial for maximizing the overall efficiency and volume of power electronic converters. This work investigates a method of scaling up voltage in particular for medium-voltage power conversion, which can be applied for a variety of application areas. SiC MOSFET devices are becoming more attractive for utilization in medium-voltage high-power converter systems due to the need to further improve the efficiency and density of these systems. Rather than using individual high voltage rated semiconductor devices, this thesis demonstrates the effectiveness of using several low voltage rated semiconductor devices connected in series in order to operate them as a single switch. Using low voltage devices as a single series-connected switch rather than a using single high voltage switch can lead to achieving a lower total on-state resistance, expectedly maximizing the overall efficiency of converter systems for which the series-connected semiconductor switches would be applied. In particular, this thesis focuses on the implementation of a newer approach of compensating for the natural unbalance in voltage between series-connected devices. An active gate control method is used for monitoring and regulating the switching speed of several devices operated in series in this work. The objective of this thesis is to investigate the feasibility of this method in order to achieve up to 6 kV total dc bus voltage using eight series-connected SiC MOSFET devices.

L’augmentation du nombre d’interfaces dans une matrice céramique permet d’améliorer sa ténacité. L’étude de la structure feuilletée de la nacre a démontré que cette ténacité pouvait être accrue par la présence de pontages entre les couches. Dans la première partie, le modèle de décohésion proposé par Pompidou et al. a été utilisé pour choisir un bicouche dont l’interface est naturellement favorable aux décohésions. Compte tenu du contexte de l’étude, cette analyse a permis de choisir le couple SiC/pyC comme bi-couche de base pour l’étude des interfaces. Par la suite, des matrices multicouches modèles (SiC/pyC)n (SiC, carbure de silicium issu du mélange CH3SiCl3/H2 – pyC, pyrocarbone à partir du propane) ont été élaborées par dépôt chimique en phase vapeur (CVD). Deux voies de pontage ont été abordées. La première met en œuvre une discontinuité entre les couches : les conditions d’élaboration ont été optimisées de façon à contrôler la croissance de couches minces massives et le développement de particules de surface (submicroniques) faisant office de pontage. La deuxième est basée sur un gradient de composition entre les couches de SiC grâce au développement d’une couche de SiC riche en co-dépôt de carbone, une interphase mixte est créée. Le pontage est assuré par la présence simultanée dans les couches à gradient de composition de grains de SiC et d’une phase carbonée. Les propriétés physico-chimiques et structurales des différents éléments des matrices ont été analysées et les différents comportements des fissures dans chacune des matrices ont été observés à la suite d’essais mécaniques. / The improvement of ceramic matrix toughness may be achieved through the presence of interfaces. Moreover, studies on a mother of pearl structure have shown the usefulness of mineral bridges between the layers. On the first part of this work, the Pompidou model was used for the selection of a bi-layered ceramic with an interface which is naturally favorable to crack deflection. SiC/pyC was taken as basic material for the interfaces study. Then, multilayered ceramic matrices (SiC/pyC)n (silicon carbide from CH3SiCl3/H2 mixture – pyC from propane) were fabricated using chemical vapor deposition (CVD). In the study, two bypass ways were proposed. On the one hand, a physical discontinuity exists between the different layers: elaboration parameters were optimized in order to develop both bulk layers and submicronic surface particles, acting as ceramic bypass. On the other hand, composition gradient films were developed between each SiC layers: by realizing carbon rich SiC layers, a mixed interphase was created. The presence of both SiC grains and carbon phases ensures the bypass structure. Physico-chemical and structural properties of multilayered ceramic matrices were analyzed and the crack propagation in each of them was observed following mechanical tests.

Actuellement, le développement de semiconducteurs et la demande croissante de convertisseurs en électronique de puissance dans les différents domaines de l’énergie électrique, notamment pour des applications dans l’aéronautique et les réseaux de transport et de distribution, imposent de nouvelles spécifications comme le fonctionnement à hautes fréquences de commutation, densités de puissance élevées, hautes températures et hauts rendements. Tout ceci contribue au fort développement des composants en SiC (Carbure de Silicium). Cependant, ces composants créent de nouvelles contraintes en Compatibilité Electromagnétique (CEM) à cause des conditions de haute fréquence de commutation et fortes vitesses de commutation (forts di/dt et dv/dt) en comparaison à d’autres composants conventionnels de l'électronique de puissance. Une étude des perturbations générées par les composants SiC est donc nécessaire. L'objectif de ce travail est de donner aux ingénieurs amenés à concevoir des convertisseurs une méthode capable de prédire les niveaux d'émissions conduites générées par un convertisseur électronique de puissance qui intègre des composants en SiC. La nouveauté du travail présenté dans cette thèse est l’intégration de différents modèles de type circuit pour tous les constituants d’un convertisseur (un hacheur série est pris comme exemple). Le modèle est valable pour une gamme de fréquences de 40Hz à 30MHz. Des approches de modélisation des parties passives du convertisseur sont présentées. Ces approches sont différentes selon que les composants modélisés soient disponibles ou à concevoir : elles sont basées sur des mesures pour la charge et les capacités ; elles sont basées sur des simulations prédictives pour routage du convertisseur. Le modèle complet du convertisseur (éléments passifs et actifs) est utilisé en simulation pour prédire les émissions conduites reçues dans le réseau stabilisateur d’impédance de ligne. Le modèle est capable de prédire l'impact de différents paramètres comme le routage, les paramètres de contrôle comme les différents rapports cycliques et les résistances de grille avec des résultats satisfaisants dans les domaines temporels et fréquentiels. Les résultats obtenus montrent que le modèle peut prédire les perturbations en mode conduit pour les différents cas jusqu'à une fréquence de 15MHz. Finalement, une étude paramétrique du convertisseur a été élaborée. Cette étude a permis de voir l’influence de la qualité des différents modèles comme les éléments parasites du routage, des composants passifs et actifs et d'identifier les éléments qui ont besoin d’un modèle précis pour avoir des résultats valides dans la prédiction des perturbations conduites. / The recent technological progress of semiconductors and increasing demand for power electronic converters in the different domains of electric energy particularly for applications in aeronautics and networks of transport and distribution impose new specifications such as high frequencies, high voltages, high temperatures and high current densities. All of this contributes in the strong development of SiC (Silicon Carbide) components. However these components create new issues in Electromagnetic Compatibility (EMC) because of the conditions of high frequency switching and high commutation speeds (high di/dt and dv/dt) compared to other conventional components in power electronics. A precise study of the emissions generated by SiC components is therefore necessary. The aim of this work is to give a method able to predict levels of conducted emissions generated by a power electronics converter with SiC components to engineers which design power converters. The novelty of the work presented in this thesis is the integration of different modeling approaches to form a circuit model of a SiC-based converter (a buck dc–dc converter is considered as an example). The modeling approach is validated in the frequency range from 40Hz to 30MHz. Modeling approaches of the passive parts of the converter are presented. Theses approaches differs according to whether the component is existing or to be designed : they are based on measurements for the load and capacitors; they are based on numerical computation and analytical formulations for PCB. The complete model obtained (passive and active components) is used in simulations to predict the conducted emissions received by the line impedance stabilization network. The model is able to predict the impact of various parameters such as PCB routing, the control parameters like duty cycles and different gate resistors in the time and frequency domains. A good agreement is obtained in all cases up to a frequency of 15MHz. Finally, a parametric study of the converter has been elaborated. This study allowed to see the influence of different models such as parasitic elements of the PCB, passive and active components and to identify the elements that need a precise model to obtain valid results in the prediction of conducted EMI.

Esta pesquisa engloba o estudo e desenvolvimento de novas heteroestruturas semicondutoras, tomando como base as estruturas SOI (Silicon-On-Insulator - silício sobre isolante) obtidas pela técnica Smart Cut, estudadas nestes últimos anos no Departamento de Engenharia de Sistemas Eletrônicos da Escola Politécnica da Universidade de São Paulo (EPUSP). Esta técnica combina a solda direta para a união de lâminas e a implantação iônica (I/I) de íons leves para a separação de camadas especificadas. São essenciais na preparação destas estruturas SOI, processos de I/I, limpeza e ativação das superfícies das lâminas e recozimentos em fornos a temperaturas moderadas. Estudamos também, diferentes métodos para a obtenção de novas heteroestruturas, basicamente combinando as técnicas de fabricação da estrutura SOI e os métodos de formação do carbeto de silício (SiC), que chamaremos de heteroestruturas SiCOI (Silicon Carbide-On-Insulator). O método usado para a formação do SiC depende, em cada caso, das características desejadas para o filme que, ao mesmo tempo, estão relacionadas com a aplicação à qual estará destinado. Analisamos três métodos de obtenção do material SiC com características específicas diferentes. A metodologia proposta aborda as seguintes tarefas: Tarefa 1: Obtenção de estruturas SOI pelo método convencional utilizado em trabalhos anteriores e melhoramento das características superficiais da estrutura resultante. Tarefa 2: partindo de uma lâmina de Si previamente coberta por uma camada isolante, fabricar a heteroestrutura SiC/isolante/Si, onde a camada de SiC é crescida pelo método de deposição química de vapor assistida por plasma (PECVD). O filme obtido por deposição PECVD é amorfo e portanto são necessárias etapas de cristalização posteriores ao crescimento. Tarefa 3: partindo de uma estrutura SOI, fabricar a heteroestrutura SiC/SiO2/Si, onde a camada de SiC é obtida por implantação de íons de carbono (C+) na camada ativa de Si da estrutura SOI para sua transformação em SiC. Tarefa 4: partindo de uma estrutura SOI, fabricar a heteroestrutura SiC/SiO2/Si, onde a camada de SiC é obtida por conversão direta da camada ativa de Si da estrutura SOI em SiC como resultado da carbonização do Si usando exposição a ambiente de hidrocarbonetos. Como resultado deste trabalho foram obtidas estruturas SOI Smart Cut com valor médio de rugosidade superficial dentro dos valores esperados segundo a bibliografia consultada. Durante o desenvolvimento de heteroestruturas SiC/isolante/Si obtidas utilizando a técnica de PECVD obtivemos filmes com boas características estruturais. Os recozimentos feitos em ambiente de N2 aparentemente trazem resultados satisfatórios, conduzindo à completa cristalização dos filmes. Nas análises feitas para a fabricação de heteroestruturas SiC/isolante/Si utilizando I/I de carbono confirma-se a formação de c-SiC depois de realizado o recozimento térmico. / In this work we study new semiconductors heterostructures, based on SOI (Silicon-On- Insulator) structures obtained by \"Smart-Cut\" process, that were studied in the last years at Departamento de Engenharia de Sistemas Eletrônicos da Escola Politécnica da Universidade de São Paulo (EPUSP). This technique combines high-dose hydrogen ion implantation (I/I) and direct wafer bonding. To produce SOI structures some processes are essential: I/I process, cleaning and activation of the surfaces, and conventional thermal treatments at moderated temperatures. We also investigate different methods to obtain new heterostructures, basically combining SOI technologies and silicon carbide (SiC) growth processes, which will be called as SiCOI (Silicon Carbide-On-Insulator) heterostructures. The utilized methods to obtain the SiC are related, in each case, with the desired film\'s characteristics, which at the same time are associated with the final application. We analyze three methods to obtain SiC material with specific different characteristics. The proposed methodology approaches the following tasks: Task 1: Fabrication of SOI structures by the conventional technology previously used by us, and the improvement of superficial characteristic of the final structure. Task 2: Fabrication of SiC/insulator/Si heterostructures from Si substrate previously covered with an insulator capping layer, where the SiC layer is deposited by plasma enhanced chemical vapor deposition (PECVD). The PECVD film is amorphous and therefore, a thermal annealing step is necessary for crystallization. Task 3: Fabrication of SiC/SiO2/Si heterostructures from SOI structure, where the SiC layer is synthesized through a high dose carbon implantation into the thin silicon overlayer of a SOI wafer. Task 4: Fabrication of SiC/SiO2/Si heterostructures from SOI structure, where the SiC layer is achieved by direct carbonization conversion of the silicon overlayer of a SOI wafer In this work we have obtained Smart Cut SOI structures with surface roughness similar to the previous reported. We also obtained SiC/insulator/Si heterostructures with good structural characteristics using PECVD technique. The investigated N2 thermal annealing appears to be suitable for the crystallization of all the amorphous films deposited by PECVD. We have shown the possibility of using carbon ion implantation and subsequent thermal annealing to form c-SiC for SiC/insulator/Si heterostructures.

Esta pesquisa engloba o estudo e desenvolvimento de novas heteroestruturas semicondutoras, tomando como base as estruturas SOI (Silicon-On-Insulator - silício sobre isolante) obtidas pela técnica Smart Cut, estudadas nestes últimos anos no Departamento de Engenharia de Sistemas Eletrônicos da Escola Politécnica da Universidade de São Paulo (EPUSP). Esta técnica combina a solda direta para a união de lâminas e a implantação iônica (I/I) de íons leves para a separação de camadas especificadas. São essenciais na preparação destas estruturas SOI, processos de I/I, limpeza e ativação das superfícies das lâminas e recozimentos em fornos a temperaturas moderadas. Estudamos também, diferentes métodos para a obtenção de novas heteroestruturas, basicamente combinando as técnicas de fabricação da estrutura SOI e os métodos de formação do carbeto de silício (SiC), que chamaremos de heteroestruturas SiCOI (Silicon Carbide-On-Insulator). O método usado para a formação do SiC depende, em cada caso, das características desejadas para o filme que, ao mesmo tempo, estão relacionadas com a aplicação à qual estará destinado. Analisamos três métodos de obtenção do material SiC com características específicas diferentes. A metodologia proposta aborda as seguintes tarefas: Tarefa 1: Obtenção de estruturas SOI pelo método convencional utilizado em trabalhos anteriores e melhoramento das características superficiais da estrutura resultante. Tarefa 2: partindo de uma lâmina de Si previamente coberta por uma camada isolante, fabricar a heteroestrutura SiC/isolante/Si, onde a camada de SiC é crescida pelo método de deposição química de vapor assistida por plasma (PECVD). O filme obtido por deposição PECVD é amorfo e portanto são necessárias etapas de cristalização posteriores ao crescimento. Tarefa 3: partindo de uma estrutura SOI, fabricar a heteroestrutura SiC/SiO2/Si, onde a camada de SiC é obtida por implantação de íons de carbono (C+) na camada ativa de Si da estrutura SOI para sua transformação em SiC. Tarefa 4: partindo de uma estrutura SOI, fabricar a heteroestrutura SiC/SiO2/Si, onde a camada de SiC é obtida por conversão direta da camada ativa de Si da estrutura SOI em SiC como resultado da carbonização do Si usando exposição a ambiente de hidrocarbonetos. Como resultado deste trabalho foram obtidas estruturas SOI Smart Cut com valor médio de rugosidade superficial dentro dos valores esperados segundo a bibliografia consultada. Durante o desenvolvimento de heteroestruturas SiC/isolante/Si obtidas utilizando a técnica de PECVD obtivemos filmes com boas características estruturais. Os recozimentos feitos em ambiente de N2 aparentemente trazem resultados satisfatórios, conduzindo à completa cristalização dos filmes. Nas análises feitas para a fabricação de heteroestruturas SiC/isolante/Si utilizando I/I de carbono confirma-se a formação de c-SiC depois de realizado o recozimento térmico. / In this work we study new semiconductors heterostructures, based on SOI (Silicon-On- Insulator) structures obtained by \"Smart-Cut\" process, that were studied in the last years at Departamento de Engenharia de Sistemas Eletrônicos da Escola Politécnica da Universidade de São Paulo (EPUSP). This technique combines high-dose hydrogen ion implantation (I/I) and direct wafer bonding. To produce SOI structures some processes are essential: I/I process, cleaning and activation of the surfaces, and conventional thermal treatments at moderated temperatures. We also investigate different methods to obtain new heterostructures, basically combining SOI technologies and silicon carbide (SiC) growth processes, which will be called as SiCOI (Silicon Carbide-On-Insulator) heterostructures. The utilized methods to obtain the SiC are related, in each case, with the desired film\'s characteristics, which at the same time are associated with the final application. We analyze three methods to obtain SiC material with specific different characteristics. The proposed methodology approaches the following tasks: Task 1: Fabrication of SOI structures by the conventional technology previously used by us, and the improvement of superficial characteristic of the final structure. Task 2: Fabrication of SiC/insulator/Si heterostructures from Si substrate previously covered with an insulator capping layer, where the SiC layer is deposited by plasma enhanced chemical vapor deposition (PECVD). The PECVD film is amorphous and therefore, a thermal annealing step is necessary for crystallization. Task 3: Fabrication of SiC/SiO2/Si heterostructures from SOI structure, where the SiC layer is synthesized through a high dose carbon implantation into the thin silicon overlayer of a SOI wafer. Task 4: Fabrication of SiC/SiO2/Si heterostructures from SOI structure, where the SiC layer is achieved by direct carbonization conversion of the silicon overlayer of a SOI wafer In this work we have obtained Smart Cut SOI structures with surface roughness similar to the previous reported. We also obtained SiC/insulator/Si heterostructures with good structural characteristics using PECVD technique. The investigated N2 thermal annealing appears to be suitable for the crystallization of all the amorphous films deposited by PECVD. We have shown the possibility of using carbon ion implantation and subsequent thermal annealing to form c-SiC for SiC/insulator/Si heterostructures.

Over the last decade, electronics operating at high temperatures have been increasingly demanded to support in situ sensing applications such as automotive, deep-well drilling and aerospace. However, few of these applications have requirements above 460 °C, as the surface temperature of Venus, which is a specific target for the seismic sensing application in this thesis. Due to its wide bandgap, Silicon Carbide (SiC) is a promising candidate to implement integrated circuits (ICs) operating in such extreme environments. In this thesis, various analog and mixed-signal ICs in 4H-SiC bipolar technology for high-temperature sensing applications are explored, in which the device performance variation over temperatures are considered. For this purpose, device modeling, circuit design, layout design, and device/circuit characterization are involved. In this thesis, the circuits are fabricated in two batches using similar technologies. In Batch 1, the first SiC sigma-delta modulator is demonstrated to operate up to 500 °C with a 30 dB peak SNDR. Its building blocks including a fully-differential amplifier, an integrator and a comparator are characterized individually to investigate the modulator performance variation over temperatures. In the succeeding Batch 2, a SiC electromechanical sigma-delta modulator is designed with a chosen Si capacitive sensor for seismic sensing on Venus. Its building blocks including a charge amplifier, a multiplier and an oscillator are designed. Compared to Batch 1, a smaller transistor and two metal-interconnects are used to implement higher integration ICs in Batch 2. Moreover, the first VBIC-based compact model featured with continuous-temperature scalability from 27 to 500 °C is developed based on the SiC transistor in Batch 1, in order to optimize the design of circuits in Batch 2. The demonstrated performance of ICs in Batch 1 show the feasibility to further develop the SiC readout ICs for seismic sensor system operating on Venus. / <p>QC 20170911</p>

Advances in wide-bandgap semiconductor devices have increased the allowable operating temperature of power electronic systems. High-temperature devices can benefit applications such as renewable energy, electric vehicles, and space-based power electronics that currently require bulky cooling systems for silicon power devices. Cooling systems can typically be reduced in size or removed by adopting wide-bandgap semiconductor devices, such as silicon carbide. However, to do this, semiconductor device packaging with high reliability at high temperatures is necessary. Transient liquid phase (TLP) die-attach has shown in literature to be a promising bonding technique for this packaging need. In this work TLP has been comprehensively investigated and characterized to assess its viability for high-temperature power electronics applications. The reliability and durability of TLP die-attach was extensively investigated utilizing electrical resistivity measurement as an indicator of material diffusion in gold-indium TLP samples. Criteria of ensuring diffusive stability were also developed. Samples were fabricated by material deposition on glass substrates with variant Au–In compositions but identical barrier layers. They were stressed with thermal cycling to simulate their operating conditions then characterized and compared. Excess indium content in the die-attach was shown to have poor reliability due to material diffusion through barrier layers while samples containing suitable indium content proved reliable throughout the thermal cycling process. This was confirmed by electrical resistivity measurement, EDS, FIB, and SEM characterization. Thermal and mechanical characterization of TLP die-attached samples was also performed to gain a newfound understanding of the relationship between TLP design parameters and die-attach properties. Samples with a SiC diode chip TLP bonded to a copper metalized silicon nitride iv substrate were made using several different values of fabrication parameters such as gold and indium thickness, Au–In ratio, and bonding pressure. The TLP bonds were then characterized for die-attach voiding, shear strength, and thermal impedance. It was found that TLP die-attach offers high average shear force strength of 22.0 kgf and a low average thermal impedance of 0.35 K/W from the device junction to the substrate. The influence of various fabrication parameters on the bond characteristics were also compared, providing information necessary for implementing TLP die-attach into power electronic modules for high-temperature applications. The outcome of the investigation on TLP bonding techniques was incorporated into a new power module design utilizing TLP bonding. A full half-bridge inverter power module for low-power space applications has been designed and analyzed with extensive finite element thermomechanical modeling. In summary, TLP die-attach has investigated to confirm its reliability and to understand how to design effective TLP bonds, this information has been used to design a new high-temperature power electronic module.

Wide bandgap (WBG) semiconductor devices are becoming increasing popular in power electronics applications. However, WBG semiconductor devices generate a substantial amount of conducted electromagnetic interference (EMI) compared to silicon (Si) devices due to their ability to operate at higher switching frequencies, higher operating voltages and faster slew rates. This thesis explores and analyzes EMI mitigation techniques that can be applied to a power module architecture at the packaging level. In this thesis, the EMI footprint of four different module architectures is measured experimentally. A time domain LTspice simulation model of the experimental test setup is then built. The common mode (CM) EMI emissions that escape the baseplate of the module into the converter is then examined through the simulation. The simulation is used to explore the CM noise footprint of eight additional module architectures that were found in literature. The EMI trends and the underlying mitigation principle for the twelve modules is explained by highlighting key differences in the architectures using common mode equivalent modelling and substitution and superposition theorem. The work aims to help future module designers by not only comparing the EMI performance of the majority of module architectures available in literature but by also providing an analysis methodology that can be used to understand the EMI behavior of any new module architecture that has not been discussed. Although silicon carbide (SiC) modules are used for this study, the results are applicable for any WBG device. / M.S. / As society moves towards the electric grid of the future, there have been increasing calls for high efficiency, high power density, and low electromagnetic interference (EMI) power electronic converters. EMI is a big problem when using wide-bandgap (WBG) devices as these devices can switch very quickly and handle higher voltages when compared to silicon devices. In this study, ways to reduce EMI in a WBG power module through twelve different types of packaging are explored. Four WBG power modules are designed and fabricated in the lab, whereas a simulation model was created to study the EMI behavior of the remaining eight power module. The EMI behavior of these modules is explained using common mode (CM) equivalent modeling and substitution and superposition theorem. This study is important because WBG devices are becoming more and more popular in power electronic applications. The author hopes the findings and analysis presented in this paper can help future module designers reduce the EMI footprint of modules they design.

Organic coatings are extensively used as protective coatings in several industries including the automotive and aircraft industries. The last few years have witnessed an increased interest in improving not only the mechanical properties but also the corrosion protection properties of organic coatings. Among the currently investigated methods of improving the performance of organic coatings is the incorporation of additives in the organic paint matrix. Vapor grown carbon nanofibers (VGCNFs) are a class of carbon fibers that are produced by catalytic dehydrogenation of a hydrocarbon at high temperatures. Depending on the method of synthesis and the post-treatment processes, the diameter of the VGCNFs is normally in the 10-300 nm range. The small size, light weight, high aspect ratio, and unique physical, thermal, mechanical, and electrical properties of VGCNF make it an ideal reinforcing filler in polymer matrix nanocomposites to enhance the mechanical properties of the pure polymeric material in high performance applications in several industries such as the automotive, aircraft, battery, sensors, catalysis, electronics, and sports industries. The main objective of the current investigation was to study the corrosion protection offered by the incorporation of VGCNFs into a commercial alkyd paint matrix applied to the surface of mild steel coupons. The corrosion protection was investigated by immersing samples in air saturated 3% NaCl solution (artificial seawater). The samples were studied by electrochemical impedance spectroscopy (EIS) along with other measurements, including electrochemical (open circuit potential, cyclic voltammetry), chemical (salt spray test), electrical conductivity, and surface analysis (SEM, AFM, optical profilometry, and nanoindentation). The study involved the investigation of the effect of the weight percent (wt %) of the VGCNF as well as the coating film thickness on the corrosion protection performance of the coated steel samples when exposed to the corrosive electrolyte. By way of contrast, the EIS behavior of steel coupons coated with a paint coating incorporating different weight percents of powdered silicon carbide (SiC) particles was also studied. The EIS spectra were used to calculated and graph several corrosion parameters for the investigated systems. At the end, the studied coatings were ranked in order of their anticorrosive properties.

Le carbure de silicium est un matériau souvent employé comme matrice dans les composites thermostructuraux. Le précurseur classiquement utilisé pour son élaboration par dépôt/infiltration par voie gazeuse est CH3SiCl3. La thèse vise à évaluer le remplacement de ce précurseur par des précurseurs gazeux bi-sourcés de SiC où carbone et silicium sont apportés séparément.A partir du système SiHCl3/C3H8/H2, l’influence du débit total, de la température, de la pression totale et de (C/Si)gaz sont évaluées et comparées aux résultats obtenus avec le système CH3SiCl3/H2. La mesure in situ de la vitesse de dépôt permet de définir des lois cinétiques apparentes. L’analyse IRTF de la phase gazeuse indique que les évolutions des pressions partielles des différents produits stables sont corrélées avec les transitions cinétiques et les changements de composition du solide. Les simulations numériques de l’évolution de la phase gazeuse montrent une bonne corrélation avec les résultats expérimentaux et permettent de proposer des mécanismes homogènes et hétérogènes qui pourraient expliquer les écarts à la stoechiométrie du dépôt.L’étude de six précurseurs supplémentaires permet de mieux identifier le rôle des principales espèces en phase homogène et hétérogène, et notamment les précurseurs effectifs de dépôt. Enfin, l’étude de l’infiltration de matériaux poreux modèles révèle des améliorations significatives en termes d’homogénéité de vitesse de dépôt.Ainsi, des conditions propices à l’infiltration de carbure de silicium peuvent être obtenues en adaptant la réactivité de la phase gazeuse par la sélection de précurseurs initiaux et des chemins réactionnels qui en découlent. / Silicon carbide (SiC) is material of choice for the matrix of Ceramic Matrix Composites (CMC).CH3SiCl3/H2 mixtures are currently used as gas precursor for the synthesis of the CVI-SiC matrices.The present work considers the dual-source approach with two separate carbon and silicon precursorsmolecules.In the case of SiHCl3/C3H8/H2 mixture, systematic studies of total flow rate, temperature, total pressureand C/Si ratio of initial gaseous phase are realized. Kinetics obtained with growth rate measurements and solid composition are compared with results from CH3SiCl3/H2 mixture. On the basis of the apparent reaction orders and activation energies, experimental kinetic laws are derived. Through IRTF analysis of the gas phase, the partial pressures of the different stable products are correlated with deposition kinetic and solid composition. Results obtained in gas-phase kinetic simulation show a good correlation with the experimental results and a mechanism of homogeneous decomposition is proposed. A better understanding of the role of the principal species in homogenous and heterogeneous phase is obtained through the study of six other gas systems and the roles of some effective precursors are discussed. Finally, infiltration results of porous material models with different precursor systems reveal significant improvements as homogeneity of kinetic deposit.Hence, favourable conditions to silicon carbide infiltration can be obtained by adapting the reactivity of the gas phase, with the choice of initial precursors and homogeneous chemistry associated. Asystematic study of the process evidences promising working windows for the infiltration of pure SiCin porous performs.