International Telemetering Conference Proceedings / October 26-29, 1998 / Town & Country Resort Hotel and Convention Center, San Diego, California / Presentation of Alcatel Espace last studies and developments regarding TT&C receiver Products for satellite. This document lays on 3 parts: · a technical point of view showing digital demodulation principles used (base band recovery, analytical head, PM or FM demodulation) and their related offered possibilities(digital controlling loop, lock status detection, jammer detection,....) · a technology/design description · a synthesis showing performance and results

La version intégrale de ce mémoire est disponible uniquement pour consultation individuelle à la bibliothèque de musique de l'Université de Montréal (www.bib.umontreal.ca/MU) / Ce mémoire présente les résultats de mes deux années d’études à la maîtrise en composition instrumentale à l’Université de Montréal. J’ai concentré mes recherches sur l’intégration du synthétiseur dans la musique de concert instrumentale, en plus de tenter de développer un langage personnel, en particulier en ce qui a trait à l’harmonie et au rythme. Ce texte présentera une analyse de ces différents éléments, à travers l’étude du corpus d’œuvres composées en vue de ce mémoire. En ce qui concerne la recherche sur l’intégration du synthétiseur, il sera question de la relation entre cet instrument électronique et les instruments acoustiques traditionnels, que ce soit par opposition, fusion ou dialogue musical. De plus, les problématiques propres à cet instrument seront abordées (programmation des sonorités, interprétation, notation, etc.). / This masters thesis presents the results of my two-year study in musical composition at Université de Montréal. My research focused on developing an original and personal musical language, with an emphasis on harmony and rhythm. It focused also on the integration of the synthesizer in a traditional concert setting. This paper will analyze these elements by studying a body of pieces composed for this masters degree. Regarding the study of the synthesizer, this text will be about the relationship between this electronic instrument and the traditional acoustic instruments, whether it be opposition, blending to an ensemble or musical dialogue. Furthermore, some questions about this instrument will be addressed (patch programming, live interpretation, notation problems, and so on).

Approved for public release, distribution is unlimited / This thesis discusses VHDL modeling and simulation of a full custom Application Specific Integrated Circuit (ASIC) for a Digital Image Synthesizer (DIS). The DIS synthesizes the characteristic echo signature of a pre-selected target. It is mainly used against Inverse Synthetic Aperture Radars as an electronic counter measure. The VHDL description of the DIS architecture was exported from Tanner S-Edit, modified, and simulated in Aldec Active HDLTM. Simulation results were compared with C++ and Matlab simulation results for verification. Main subcomponents, a single Range Bin Processor (RBP), a cascade of 4 RBP s and a cascade of 16 RBP s were tested and verified. The overhead control circuitry, including Self Test Circuitry and Phase Extractor, was tested separately. Finally overall DIS was tested and verified using the control circuitry and a cascade of 4 RBP s together, representing the actual 512 RBP s. As a result of this research, the majority of the DIS was functionally tested and verified. / First Lieutenant, Turkish Army

La théorie de l'information développée par Claude Shannon (1916 - 2001) met en évidence le fait que pour accroître la capacité d'un canal de transmission, il est préférable d'élargir la bande de fréquences sur laquelle les informations sont émises plutôt que les puissances d'émissions. Cette constatation est le point de départ de nombreux travaux de recherche sur les communications Ultra-Large Bande (ULB) qui ont abouti en 2002 à la création aux Etats-Unis d'une bande fréquence dîtes ULB où aucun mode de communication n'est privilégié. C'est ainsi que 2 années plus tard ont débuté à l'IM2NP des travaux portant sur les communications ULB impulsionnelles, et notamment la conception d'amplificateur faible bruit, de détecteur d'énergie, mais également de générateurs d'impulsions qui est l'élément clé des émetteurs impulsionnels. Ces derniers constituent la base des travaux présentés dans le manuscrit qui se sont déroulés de 2008 à 2011. La nature discontinue des communications impulsionnelles a tout d'abord impliquée l'introduction de nouvelles figures de mérite permettant de mesurer les performances des générateurs d'impulsions. Ensuite, il est question de méthodes de conception permettant de dimensionner des structures fonctionnant aux fréquences en jeu mais également d'en réduire les consommations statiques principalement de fuite, et ce en vue de répondre aux contraintes de consommation des systèmes embarqués. Enfin sont développées 3 architectures de générateurs d'impulsions, chacune permettant de répondre à des contraintes différentes en termes de bande de fréquences, de consommation et de portée. / The information theory developed by Claude Shannon (1916 - 2001) highlights the fact that in order to increase the capacity of a transmission channel, it is preferable to extend the bandwidth used rather than the transmission power. This finding is the starting point of many papers on Ultra-Wideband (UWB) which led to the creation in the United States of UWB band since 2002 where no modulation is privileged. Two years later, many works on Impulsionnal Radio UWB (IR-UWB) communications began at IM2NP including the design of low noise amplifier, power detector, but also pulse generators which is the key element of IR-UWB emitters. These form basis of works presented in the manuscript that took place from 2008 to 2011. The discontinuous nature of communications impulse was first implied the introduction of new figures of merit for measuring performances of pulse generators. Then it deals with design techniques for sizing structures operating at frequencies involved, but also to reduce consumption and especially static leakage to reduce enough power consumption for embedded systems. Finally three architectures of pulse generators are developed, each one responding to different constraints in terms of frequency, consumption and range.

Orientador: Nobuo Oki / Banca: Saulo Finco / Banca: Cláudio Kitano / Resumo: Nesse trabalho, propõe-se o projeto e implementação de um sintetizador de sinais ortogonais utilizando técnicas de circuito integrado e processo CMOS. O circuito do sintetizador baseia-se em um modelo matemático que utiliza multiplicadores e integradores analógicos, para geração de bases de funções ortogonais, tais como os polinômios de Legendre, as funções de base coseno e seno, a smoothed-cosine basis e os polinômios de Hermite. Funções ortogonais são bastante empregadas em processamento de sinais, e a implementação deste método matemático é capaz de gerar vários tipos de funções em um mesmo circuito integrado. O projeto proposto utiliza blocos analógicos funcionais para implementar o sintetizador. Os blocos que compõem o sintetizador foram projetados utilizando circuitos diferenciais, processamento em modo de corrente e técnicas de low-voltage. Algumas topologias utilizadas estão descritas na literatura, sendo que algumas foram adaptadas e mesmo modificadas, como no caso do multiplicador de corrente. Outras tiveram que ser propostas. As simulações e os resultados experimentais mostraram que o sintetizador é capaz de gerar funções ortogonais com amplitude e distorções satisfatórias. O sintetizador pode ser alimentado em 3V, tal qual foi projetado, tem faixa de entrada de ±20 μA e apresenta DHT (distorção harmônica total) inferior a 4% no quinto e último estágio em cascata. / Abstract: In this work, a design and implementation of a synthesizer of orthogonal signals using CMOS technology and design technique for integrated circuits is proposed. The synthesizer circuit used analog multipliers and integrators for produce orthogonal functions such as Legendre polynomials, cosine and sine basis of functions, smoothed-cosine basis and Hermite polynomials. Orthogonal functions can be employed in signal processing and the implementation proposed can generate several kinds of functions in the same integrated circuit. In the synthesizer design building blocks was employed. The synthesizer's blocks were design using differential circuits, low-voltage and current-mode techniques. Some topologies from papers were adapted or modified, as in the case of the current multiplier. Other topologies had to be proposed. The simulation and experimental results have shown that the synthesizer is able to produce orthogonal functions with satisfactory quality in distortions and amplitude. The synthesizer has a 3V supply voltage, a input current range of ±20 μA and it presents less than 4% of THD (Total Harmonic Distortion) in the last output in cascade. / Mestre

The mainstream of current VLSI design and logic synthesis is based on traditional CMOS logic circuits. However, in the past two decades, various new logic circuit design styles based on pass-transistor logic (PTL) have been proposed. Compared with CMOS circuits, these PTL-based circuits are claimed to have better results in area, speed, and power in some particular applications, such as adder and multiplier designs. Since most current automatic logic synthesis tools (such as Synopsys Design Compiler) are based on conventional CMOS standard cell library, the corresponding logic minimization for CMOS logic cannot be directly employed to generate efficient PTL circuits. In this dissertation, we develop two novel PTL synthesizers that can efficiently generate PTL-based circuits. One is based on pure PTL cells; the other mixes CMOS and PTL cells in the standard cell library to achieve better performance in area, speed, and power. Since PTL-based circuits are constructed by only a few basic PTL cells, the layouts in PTL cells can be easily updated to design large SoC systems as the process technology migrates rapidly in current Nano technology era. The proposed PTL logic synthesis flows employ the popular Synopsys Design Compiler (DC) to perform logic translation and minimization based on the standard cell library composed of PTL and CMOS cells, thus, the PTL design flow can be easily embedded in the standard cell-based ASIC design flow. In this dissertation, we also discuss PTL-based designs of some fundamental hardware components. Furthermore, the proposed PTL cell library is used to synthesize large processor systems in applications of computer arithmetic and 3D graphics.

Emerging technologies such as Bluetooth and 802.11b (Wi-Fi) have fuelled the growth of the short-range communication industry. Bluetooth, the leading WPAN (wireless personal area network) technology, was designed primarily for cable replacement applications. The first generation Bluetooth products are focused on providing low-cost radio connections among personal electronic devices. In the WLAN (wireless local area network) arena, Wi-Fi appears to be the superior product. Wi-Fi is designed for high speed internet access, with higher radio power and longer distances. Both technologies use the same 2.4GHz ISM band. The differences between Bluetooth and Wi-Fi standard features lead to a natural partitioning of applications. Nowadays, many electronics devices such as laptops and PDAs, support both Bluetooth and Wi-Fi standards to cover a wider range of applications. The cost of supporting both standards, however, is a major concern. Therefore, a dual-mode transceiver is essential to keep the size and cost of such system transceivers at a minimum. A fully integrated low-IF Bluetooth receiver is designed and implemented in a low cost, main stream 0.35um CMOS technology. The system includes the RF front end, frequency synthesizer and baseband blocks. It has -82dBm sensitivity and draws 65mA current. This project involved 6 Ph.D. students and I was in charge of the design of the channel selection complex filter is designed. In the Bluetooth transmitter, a frequency modulator with fine frequency steps is needed to generate the GFSK signal that has +/-160kHz frequency deviation. A low power ROM-less direct digital frequency synthesizer (DDFS) is designed to implement the frequency modulation. The DDFS can be used for any frequency or phase modulation communication systems that require fast frequency switching with fine frequency steps. Another contribution is the implementation of a dual-mode 802.11b/Bluetooth receiver in IBM 0.25um BiCMOS process. Direct-conversion architecture was used for both standards to achieve maximum level of integration and block sharing. I was honored to lead the efforts of 7 Ph.D. students in this project. I was responsible for system level design as well as the design of the variable gain amplifier. The receiver chip consumes 45.6/41.3mA and the sensitivity is -86/-91dBm.

Orientador: Nobuo Oki / Banca: Suely Cunha Amaro Mantovani / Banca: Jozué Vieira Filho / Banca: Marcelo Arturo Jara Perez / Banca: Paulo Augusto Dal fabbro / Resumo: Nesta tese, propõe-se um sintetizador de freqüência baseado em phase locked loops (PLL) usando uma arquitetura que utiliza um dual-path loop filter, constituído de componentes passivos e um integrador digital. A proposta é empregar técnicas digitais, para reduzir o custo da implementação do sintetizador de freqüência, e flexibilizar o projeto do loop filter, para possibilitar que a arquitetura opere em uma faixa de freqüência larga de operação e com redução de tons espúrios. O loop filter digital é constituído de um contador crescente/ decrescente cujo clock é proveniente da amostragem da diferença de fase de entrada. As técnicas digitais aplicadas ao loop filter se baseiam em alterações da operação do contador, em tempos pré-estabelecidos, os quais são controlados digitalmente. Essas técnicas possibilitam reduzir o tempo de estabelecimento do PLL ao mesmo tempo em que problemas de estabilidade são resolvidos. No desenvolvimento da técnica de dual-path foi realizado o estudo de sua estabilidade, primeiramente, considerando a aproximação do PLL para um sistema linear e depois usando controle digital. Nesse estudo foram deduzidas as equações do sistema, no domínio contínuo e discreto, tanto para o projeto da estabilidade, quanto para descrever o comportamento do PLL. A metodologia top-down é usada no projeto do circuito integrado. As simulações em nível de sistema são usadas, primeiramente, para as criações das técnicas e posteriormente para a verificação do seu comportamento, usando modelos calibrados com os blocos projetados em nível de transistor. O circuito integrado é proposto para ser aplicado em identificação por rádio freqüência (RFID) na banda de UHF (Ultra High Frequency), usando multi-standard, e deve operar na faixa de 850 MHz a 1010 MHz. O sintetizador de freqüência foi projetado na tecnologia CMOS... (Resumo completo, clicar acesso eletrônico abaixo) / Abstract: In this thesis, a frequency synthesizers phase locked loops (PLL) based with an architecture that uses a dual-path loop filter consisting of passive components and a digital integrator are proposed. The objective is to employ digital techniques to reduce the implementation cost and get loop filter design flexibility to enable the architecture to have a large tuning range operation and spurious reduction. The digital loop filter is based in an up/down counter where the phase difference is sampled to generate the clock of the counter. The techniques applied in the digital path are based in digitally controlled changes in the counter operation in predefined time points. These techniques provide PLL settling time reductions whiling the stability issues are solved. The stability study of the proposed dual path has been developed. First the linear system approximation for the PLL has been assumed and then employing digital control. The continuous and discrete time equations of architecture were derived in that study applied to stability design as well as to describe the architecture behavior. The top-down methodology has been applied to the integrated circuit design. In the beginning, the system level simulations are used for the techniques creation and then the behavioral models that were calibrated with transistor level blocks are simulated. The application of the circuit is proposed to Radio Frequency Identification (RFID) using UHF (Ultra High Frequency) band for multi-standards application and will operate in range of 850 MHz to 1010 MHz. The proposed frequency synthesizer has been designed in the AMS 0.35 μm CMOS technology with 2V power supply. A 300 μs of settling time and 140 Hz of resolution was obtained in simulations. The proposed frequency synthesizer have low complexity and shown a reference noise suppression about 45.6 dB better than the conventional architecture / Doutor

Orientador: Luiz Cesar Martini / Dissertação (mestrado) - Universidade Estadual de Campinas, Faculdade de Engenharia Eletrica e de Computação / Made available in DSpace on 2018-08-06T10:40:00Z (GMT). No. of bitstreams: 1 Eberlin_Samer_M.pdf: 1431060 bytes, checksum: 0cd41a07e95c21a6a407e87001437452 (MD5) Previous issue date: 2006 / Resumo: A acelerada difusão do software "livre", tanto no Brasil como no exterior, vem se mostrando cada vez mais evidente nos mais diversos âmbitos (governo, empresas, escolas, etc.). A principal motivação para a transição do software "proprietário" para o "livre" é a redução de custos, mas para efetivar essa migração é necessário que ferramentas compatíveis estejam disponíveis para a manutenção da usabilidade do sistema. Essa é ainda uma barreira para a migração do usuário deficiente visual brasileiro, pois até este momento, nenhuma das tecnologias assistivas desenvolvidas para sistemas operacionais "livres" encontram-se disponíveis no idioma português. Como solução para esse problema, esta dissertação apresenta uma alternativa que efetivará essa migração, habilitando usuários cegos para realização de tarefas como edição de texto, acesso à internet, gerenciamento de arquivos, entre outras. O trabalho baseia-se na implementação de um sintetizador de voz para o português do Brasil e na tradução de uma tecnologia assistiva desenvolvida para sistemas operacionais "livres". Como parte integrante estão documentados também o desenvolvimento de um modelo compacto de computador pessoal e os resultados de testes realizados com usuários voluntários / Abstract: The accelerated diffusion of the "free" software, as much in Brazil as in the foreign, has beem shown more and more evident in the most diverse scopes (government, companies, schools, etc) The main motivation to the transition from "proprietary" software to the "free" one is the costs reduction, but to accomplish this migration compatible tools need to be available for the maintenance of the system usability. This is still a barrier for the migration of the brazilian visually impaired user, because up to this moment, none of the assistive technologies developed to "free" operating systems are available in portuguese language. As solution for this problem, this dissertation presents an alternative that will accomplish this migration, enabling blind users to carrying out tasks like text edition, internet access, file management, among others. The work is based on the implementation of a voice synthesizer for the portuguese from Brazil and on the translation of an assistive technology developed to "free" operating systems. As integrated part are also documented the development of a compact model of personal computer and the results of tests carried out with voluntary users / Mestrado / Telecomunicações e Telemática / Mestre em Engenharia Elétrica

This thesis deals with problematics of direct frequency digital synthesis. Principle and basic characteristics of this method of signal generating are explained in the introduction. It considers impact on purity of spectrum of output signal. Next chapter considers conception of the generator, namely choice of DDFS circuit and other basic blocks. Design of frequency multiplier, reconstruction filter and power amplifier are included. It also deals with choice of control circuit. The device is controlled by computer through USB. There was created user programme for this purpose. Measured characteristics are stated at the end of the work. This work includes schemes of connetions of designed parts including simulations and measured parameters.