Submitted by PPG Ci?ncia da Computa??o (ppgcc@pucrs.br) on 2018-06-15T14:23:09Z No. of bitstreams: 1 LEONARDO REZENDE JURACY_DIS.pdf: 2268947 bytes, checksum: bedc63f7c14296e039a798403cdeec80 (MD5) / Approved for entry into archive by Sheila Dias (sheila.dias@pucrs.br) on 2018-06-26T12:27:11Z (GMT) No. of bitstreams: 1 LEONARDO REZENDE JURACY_DIS.pdf: 2268947 bytes, checksum: bedc63f7c14296e039a798403cdeec80 (MD5) / Made available in DSpace on 2018-06-26T12:45:06Z (GMT). No. of bitstreams: 1 LEONARDO REZENDE JURACY_DIS.pdf: 2268947 bytes, checksum: bedc63f7c14296e039a798403cdeec80 (MD5) Previous issue date: 2018-03-21 / Atualmente, a abordagem s?ncrona ? a mais utilizada em projeto de circuitos integrados por ser altamente automatizado pelas ferramentas comerciais e por incorporar margens de tempo para garantir o funcionamento correto nos piores cen?rios de varia??es de processo e ambiente, limitando otimiza??es no per?odo do rel?gio e aumentando o consumo de pot?ncia. Por um lado, circuitos ass?ncronos apresentam algumas vantagens em potencial quando comparados com os circuitos s?ncronos, como menor consumo de pot?ncia e maior vaz?o de dados, mas tamb?m podem sofrer com varia??es de processo e ambiente. Por outro lado, circuitos resilientes s?o uma alternativa para manter o circuito funcionando na presen?a de efeitos de varia??o. Sendo assim, foi proposto o circuito Blade que combina as vantagens de circuitos ass?ncronos com circuitos resilientes. Blade utiliza latches em sua implementa??o e mant?m seu desempenho em cen?rios de caso m?dio. Independentemente do estilo de projeto (s?ncrono ou ass?ncrono), durante o processo de fabrica??o de circuitos integrados, algumas imperfei??es podem acontecer, causando defeitos que reduzem o rendimento de fabrica??o. Circuitos defeituosos podem apresentar um comportamento falho, gerando uma sa?da diferente da esperada, devendo ser identificados antes de sua comercializa??o. Metodologias de teste podem ajudar na identifica??o e diagn?stico desse comportamento falho. Projeto visando testabilidade (do ingl?s, Design for Testability - DfT) aumenta a testabilidade do circuito adicionando um grau de controlabilidade e observabilidade atrav?s de diferentes t?cnicas. Scan ? uma t?cnica de DfT que fornece para um equipamento de teste externo acesso aos elementos de mem?ria internos do circuito, permitindo inser??o de padr?es de teste e compara??o da resposta. O objetivo deste trabalho ? propor uma abordagem de DfT estrutural, completamente autom?tica e integrada com as ferramentas comerciais de projeto de circuitos, incluindo uma s?rie de m?todos para lidar com os desafios relacionados ao teste de circuitos ass?ncronos e resilientes, com foco no Blade. O fluxo de DfT proposto ? avaliado usando um m?dulo criptogr?fico e um microprocessador. Os resultados obtidos para o m?dulo criptogr?fico mostram uma cobertura de falha de 98,17% para falhas do tipo stuck-at e 89,37% para falhas do tipo path-delay, com um acr?scimo de ?rea de 112,16%. Os resultados obtidos para o microprocessador mostram uma cobertura de 96,04% para falhas do tipo stuck-at e 99,00% para falhas do tipo path-delay, com um acr?scimo de ?rea de 50,57%. / Nowadays, the synchronous circuits design approach is the most used design method since it is highly automated by commercial computer-aided design (CAD) tools. Synchronous designs incorporate timing margins to ensure the correct behavior under the worstcase scenario of process and environmental variations, limiting its clock period optimization and increasing power consumption. On one hand, asynchronous designs present some potential advantages when compared to synchronous ones, such as less power consumption and more data throughput, but they may also suffer with the process and environmental variations. On the other hand, resilient circuits techniques are an alternative to keep the design working in presence of effects of variability. Thus, Blade template has been proposed, combining the advantages of both asynchronous and resilient circuits. The Blade template employs latches in its implementation and supports average-case circuit performance. Independently of the design style (synchronous or asynchronous), during the fabrication process of integrated circuits, some imperfections can occur, causing defects that reduce the fabrication yield. These defective ICs can present a faulty behavior, which produces an output different from the expected, and it must be identified before the circuit commercialization. Test methodologies help to find and diagnose this faulty behavior. Design for Testability (DfT) increases circuit testability by adding a degree of controllability and observability through different test techniques. Scan design is a DfT technique that provides for an external test equipment the access to the internal memory elements of a circuit, allowing test pattern insertion and response comparison. The goal of this work is to propose a fully integrated and automated structural DfT approach using commercial EDA tools and to propose a series of design methods to address the challenges related to testing asynchronous and resilient designs, with focus on Blade template. The proposed DfT flow is evaluated with a criptocore module and a microprocessor. The obtained results for the criptocore module show a fault coverage of 98.17% for stuck-at fault model and 89.37% for path-delay fault model, with an area overhead of 112.16%. The obtained results for the microprocessor show a fault coverage of 96.04% for stuck-at fault model and 99.00% for path-delay fault model, with an area overhead of 50.57%.

Nesta tese, introduzimos o conceito de sequência convergente de permutações e provamos a existência de um objeto limite para tais sequências. Introduzimos ainda um novo modelo de permutação aleatória baseado em tais objetos e introduzimos um conceito novo de distância entre permutações. Provamos então que sequências de permutações aleatórias são convergentes e provamos a equivalência entre esta noção de convergência e convergência nesta nova distância. Obtemos ainda resultados de amostragem e quase-aleatoriedade para permutações. Provamos também uma caracterização para parâmetros testáveis de permutações. / We introduce the concept of convergent sequence of permutations and we prove the existence of a limit object for these sequences. We also introduce a new and more general model of random permutation based on these limit objects and we introduce a new metric for permutations. We also prove that sequences of random permutations are convergent and we prove the equivalence between this notion of convergence and convergence in this new metric. We also show some applications for samplig and quasirandomness. We also prove a characterization for testable parameters of permutations.

Teste de Software tem o objetivo de executar um programa sob teste com o objetivo de revelar suas falhas, portanto é uma das fases mais importante do ciclo de vida do desenvolvimento de um software. A testabilidade é um atributo de qualidade fundamental para o sucesso da atividade de teste, pois ela pode ser entendida como o esforço necessário para criar, executar e avaliar os casos de teste em um software. Este atributo não é uma qualidade intrínseca do software, portanto não pode ser medido diretamente como a quantidade de linhas de código, por exemplo. Entretanto, ela pode ser inferida por meio das características ou métricas internas e externas de um software. Entre as características comumente utilizadas na análise da testabilidade estão as métricas CK, que foram propostas por Chidamber e Kemerer com objetivo de analisar software orientado a objetos. A maioria dos trabalhos nesta linha, entretanto, relaciona o tamanho e a quantidade de casos testes com a testabilidade de um software. Entretanto, é fundamental analisar a qualidade dos testes para saber se eles atingem os objetivos para os quais foram propostos, independente de quantidade e tamanho. Portanto, este trabalho de mestrado apresenta um estudo empírico sobre a relação entre as métricas CK e a testabilidade de um software com base na análise da adequação de seus casos de teste unitários, critérios de teste estrutural e de mutação. Inicialmente foi realizada uma Revisão Sistemática cujo objetivo foi avaliar o estado da arte da testabilidade e as métricas CK. Os resultados mostraram que apesar de existirem várias pesquisas relacionadas ao tema, existem lacunas que motivam novas pesquisas no que concerne a análise da qualidade dos testes e identificação das características das métricas que podem ser inferidas para medir e analisar a testabilidade. Em seguida, foram realizadas duas análises empíricas. Na primeira análise, as métricas foram analisadas por meio da correlação das métricas CK com a cobertura de linha de código, cobertura de \\textit (arestas, ramos ou desvio de fluxo) e escore de mutação. Os resultados desta análise demonstraram a importância de cada métrica dentro do contexto da testabilidade. Na segunda análise, foi realizada uma proposta de clusterização das métricas para tentar identificar grupos de classes com características semelhantes relacionadas à testabilidade. Além das análises empíricas, foi desenvolvida e apresentada uma ferramenta de coleta e análise de métricas CK com objetivo de contribuir com novas pesquisas relacionados a proposta deste projeto. Apesar das limitações das análises, os resultados deste trabalho mostraram a importância de cada métrica CK dentro do contexto da testabilidade e fornece aos desenvolvedores e projetistas uma ferramenta de apoio e dados empíricos para melhor desenvolverem e projetarem seus sistemas com o objetivo de facilitar a atividade de teste de software / Software testing have aim to run a program under test with the aim of revealing its failures, so it is one of the most important phases of the software development lifecycle. Testability is a key quality attribute for the success of the test activity, because it can be understood as the effort required to create, execute and evaluate test cases in software. This attribute is not an intrinsic quality of the software, so it can not be measured directly as the number of lines code, for example. However, it can be inferred through the or internal and external metrics of a software. Among the features commonly used in testability analysis are CK metrics, which were proposed by Chidamber and Kemerer in order to analyze object-oriented software. Most of the works in this line, however, relate the size and quantity of test cases with software testability. However, it\'s critical to analyze the quality of the tests to see if they achieve the objectives for which they were proposed, independent of quantity and size. Therefore, this Master\'s degree work presents an empirical study on the relationship between CK metrics and software testability based on the analysis of the adequacy of its unit test cases, structural test criteria and mutation. Initially, a Systematic Review was carried out to evaluate the state of the art of testability and CK metrics. The results showed that although there are several researches related to the subject, there are gaps that motivate new research in what concerns the analysis of the quality of the tests and identification of the features of the metrics that can be inferred to measure and analyze the testability. Two empirical analyzes were performed. In the first analysis, the metrics were analyzed through the correlation of the CK metrics with the code line coverage, branch coverage or mutation score. The results of this analysis showed the importance of each metric within the context of testability. In the second analysis, a metric clustering proposal was made to try to identify groups of classes with similar features related to testability. In addition to the empirical analysis, a tool for the collection and analysis of CK metrics was developed and presented, with aim to contribute with new researches related to the proposal of this project. Despite the limitations of the analyzes, the results of this work showed the importance of each CK metric within the context of testability and provides developers and designers with a support tool and empirical data to better develop and design their systems with the aim of facilitate the activity of software testing

This project examines how the quality of a code generator used in an Object-Relational Mapping (ORM) framework can be improved in terms of maintainability, testability and reusability by changing the design from a top-down perspective to a bottom up. The resulting generator is tested in a case study to verify that the new design is more cohesive and less coupled than an existing code generator.

Les travaux présentés dans ce mémoire de thèse s'intéressent à la génération et à la mise en œuvre de séquences de test pour le test de conformité de contrôleurs logiques. Dans le cadre de ces travaux, le Grafcet (IEC 60848 (2002)), langage de spécification graphique utilisé dans un contexte industriel, a été retenu comme modèle de spécification. Les contrôleurs logiques principalement considérés dans ces travaux sont les automates programmables industriels (API). Afin de valider la mise en œuvre du test de conformité pour des systèmes de contrôle/commande critiques, les travaux présentés proposent: - Une formalisation du langage de spécification Grafcet. En effet, l'application des méthodes usuelles de vérification et de validation nécessitent la connaissance du comportement à partir de modèles formels. Cependant, dans un contexte industriel, les modèles utilisés pour la description des spécifications fonctionnelles sont choisis en fonction de leur pouvoir d'expression et de leur facilité d'utilisation, mais ne disposent que rarement d'une sémantique formelle. - Une étude de la mise en œuvre de séquences de test et l'analyse des verdicts obtenus lors du changement simultané de plusieurs entrées logiques. Une campagne d'expérimentation a permis de quantifier, pour différentes configurations de l'implantation, le taux de verdicts erronés dus à ces changements simultanés. - Une définition du critère de SIC-testabilité d'une implantation. Ce critère, déterminé à partir de la spécification Grafcet, définit l'aptitude d'une implantation à être testée sans erreur de verdict. La génération automatique de séquences de test minimisant le risque de verdict erroné est ensuite étudiée. / The works presented in this PhD thesis deal with the generation and implementation of test sequences for conformance test of logic controllers. Within these works, Grafcet (IEC 60848 (2002)), graphical specification language used in industry, has been selected as the specification model. Logic controllers mainly considered in these works are Programmable Logic Controllers (PLC). In order to validate the carrying out of conformance test of critical control systems, this thesis presents: - A formalization of the Grafcet specification language. Indeed, to apply usual verification and validation methods, the behavior is required to be expressed through formal models. However, in industry, the models used to describe functional specifications are chosen for their expression power and usability, but these models rarely have a formal semantics. - A study of test sequences execution and analysis of obtained verdicts when several logical inputs are changed simultaneously. Series of experimentation have permitted to quantify, for different configurations of the implantation under test, the rate of erroneous verdicts due to these simultaneous changes. - A definition of the SIC-testability criterion for an implantation. This criterion, determined on the Grafect specification defines the ability of an implementation to be tested without any erroneous verdict. Automatic generation of test sequences that minimize the risk of erroneous verdict is then studied.

Nesta tese, introduzimos o conceito de sequência convergente de permutações e provamos a existência de um objeto limite para tais sequências. Introduzimos ainda um novo modelo de permutação aleatória baseado em tais objetos e introduzimos um conceito novo de distância entre permutações. Provamos então que sequências de permutações aleatórias são convergentes e provamos a equivalência entre esta noção de convergência e convergência nesta nova distância. Obtemos ainda resultados de amostragem e quase-aleatoriedade para permutações. Provamos também uma caracterização para parâmetros testáveis de permutações. / We introduce the concept of convergent sequence of permutations and we prove the existence of a limit object for these sequences. We also introduce a new and more general model of random permutation based on these limit objects and we introduce a new metric for permutations. We also prove that sequences of random permutations are convergent and we prove the equivalence between this notion of convergence and convergence in this new metric. We also show some applications for samplig and quasirandomness. We also prove a characterization for testable parameters of permutations.

The article identifies the challenges during the system and specifically the software development process for safety critical electro-hydraulic control systems by using the example of the hydrostatic driveline with a four speed transmission of a feeder mixer. An optimized development approach for mobile machinery has to fulfill all the requirements according to the Machinery Directive 2006/42/EC, considering functional safety, documentation and testing requirements from the beginning and throughout the entire machine life cycle. The functionality of the drive line control could be verified in advance of the availability of a prototype by using a “software-in-the-loop” development approach, based on a MATLAB/SIMULINK model of the drive line in connection with the embedded software.

Studiens syfte är att bedöma till vilken utsträckning AI kan ersätta en människa i rollen som mjukvaruutvecklare utifrån ett kvalitativt perspektiv på kod. Detta görs genom att besvara forskningsfrågorna som lyder: “Hur använder mjukvaruutvecklare sig av generativ AI vid utvecklingsutmaningar?” och “Vad är mjukvaruutvecklares uppfattning om kvaliteten på autogenererad kod skapad av en generativ AI såsom Chat GPT?”. För att besvara frågorna har en kvalitativ metod applicerats. En litteraturundersökning startade studien och tillsammans med en ny modell som baseras på McCall quality model och Boehm quality model. Från detta har en intervjuguide skapats som används i semistrukturerade intervjuer genomförda med erfarna mjukvaruutvecklare. Resultatet visar att kod skapad av generativ AI är ett bra hjälpmedel och verktyg som kan effektivisera en mjukvaruutvecklare och att det används på det sättet idag. Däremot så visar resultaten också att koden som genereras av en generativ AI inte är tillräckligt bra och kan inte användas utan att förändringar eller åtgärder görs då det saknas kvalitet. Slutsatserna som dras är att mjukvaruutvecklare använder sig av generativ AI som ett hjälpmedel men att AI:n inte är kapabel att hantera en uppgift på egen hand, därav är det inget hot mot någon anställning för mjukvaruutvecklare. Framtida forskning bör göras på autogenererad kod. Fler verktyg bör undersökas för att utvidga kunskapen om dess kapacitet samt bör det undersökas vilken inverkan generativ AI kan ha på andra branscher. / The aim of this study, conducted and written in Swedish, is to assess the potential of replacing a human software developer with generative AI. The study evaluates the quality of code generated by a generative AI model, this is done by answering the following research questions: “How do software developers use generative AI for development challenges'' and “How do software developers perceive the quality of code autogenerated by a generative AI such as Chat GPT”. To answer the questions we employ a qualitative research method. The study began with a literature review and based our evaluation of software quality on a hybrid model that modifies and combines McCall quality model and Boehm software quality model. The literature review and the hybrid model was used as a base to shape an interview guide. The interview guide was used in semistructured interviews conducted with experienced software developers. The results suggest that autogenerated code from generative AI is a viable aid for software developers as it makes them more effective in a number of tasks. However, the results also show that the autogenerated AI code has insufficient quality as a complete solution, and therefore often requires further fine-tuning and improvements from software developers. From the results, we conclude that software developers do use generative AI as a tool while writing code. Generative AI enhances software developers effectiveness but the current state of generative AI cannot fully replace a human software developer hence it is not a threat to any employment. Future research should be conducted on auto generated code. Some more tools should be studied to broaden the knowledge on its capabilities as well as looking at the implications that generative AI have on other industries.

Práce se zabývá metodami pro testování lineárních analogových obvodů v kmitočtové oblasti. Cílem je navrhnout efektivní metody pro automatické generování testovacího plánu. Snížením počtu měření a výpočetní náročnosti lze výrazně snížit náklady za testování. Práce se zabývá multifrekveční parametrickou poruchovou analýzou, která byla plně implementována do programu Matlab. Vhodnou volbou testovacích kmitočtů lze potlačit chyby měření a chyby způsobené výrobními tolerancemi obvodových prvků. Navržené metody pro optimální volbu kmitočtů byly statisticky ověřeny metodou MonteCarlo. Pro zvýšení přesnosti a snížení výpočetní náročnosti poruchové analýzy byly vyvinuty postupy založené na metodě nejmenších čtverců a přibližné symbolické analýze.

The 21st century is considered as the era of mass communication and electronic information exchange. There is a dramatic increase in electronic communications and e-transactions worldwide. However, this advancement results in the appearance of many security issues, especially when the exchanged information is sensitive and/or confidential. A significant aspect of security is authentication, which in most of the cases is provided through a cryptographic hash function. As happens for the majority of security primitives, software design and implementation of hash functions is becoming more prevalent today. However, hardware is the embodiment of choice for military and safety-critical commercial applications due to the physical protection and increased performance that they offer. Hence, similarly to general hardware designs, regarding cryptographic hash function ones, three crucial issues, among others, arise: performance, reliability, and flexibility. In this PhD dissertation, hardware solutions regarding cryptographic hash functions, addressing the aforementionted three crucial issues are proposed. Specifically, a design methodology for developing high-throughput and area-efficient sole hardware architectures of the most widely-used cryptographic hash families, i.e. the SHA-1 and SHA-2, is proposed. This methodology incorporates several algorithmic-, system-, and circuit-level techniques in an efficient, recursive way, exploiting the changes in the design’s graph dependencies that are resulted by a technique’s application. Additionally, high-throughput and area-efficient hardware designs for the above families as well as new ones (e.g. JH and Skein), are also proposed. These architectures outperform significantly all the similar ones existing in the literature. Furthermore, a design methodology for developing Totally Self-Checking (TSC) architectures of the most widely-used cryptographic hash families, namely the SHA-1 and SHA-2 ones is proposed for the first time. As any RTL architecture for the above hash families is composed by similar functional blocks, the proposed methodology is general and can be applied to any RTL architecture of the SHA-1 and SHA-2 families. Based on the above methodology, TSC architectures of the two representatice hash functions, i.e. SHA-1 and SHA-256, are provided, which are significantlty more efficient in terms of Throughput/Area, Area, and Power than the corresponding ones that are derived using only hardware redundancy. Moreover, a design methodology for developing hardware architectures that realize more than one cryptographic hash function (mutli-mode architectures) with reasonable throughput and area penalty is proposed. Due to the fact that any architecture for the above hash families is composed by similar functional blocks, the proposed methodology can be applied to any RTL architecture of the SHA-1 and SHA-2 families. The flow exploits specific features appeared in SHA-1 and SHA-2 families and for that reason it is tailored to produce optimized multi-mode architectures for them. Based on the above methodology, two multi-mode architectures, namely a SHA256/512 and a SHA1/256/512, are introduced. They achieve high throughput rates, outperforming all the existing similar ones in terms of throughput/area cost factor. At the same time, they are area-efficient. Specifically, they occupy less area compared to the corresponding architectures that are derived by simply designing the sole hash cores together and feeding them to a commercial FPGA synthesis/P&R/mapping tool. Finally, the extracted knowledge from the above research activities was exploited in three additional works that deal with: (a) a data locality methodology for matrix–matrix multiplication, (b) a methodology for Speeding-Up Fast Fourier Transform focusing on memory architecture utilization, and (c) a near-optimal microprocessor & accelerators co-design with latency & throughput constraints. / Ο 21ος αιώνας θεωρείται η εποχή της μαζικής επικοινωνίας και της ηλεκτρονικής πληροφορίας. Υπάρχει μία δραματική αύξηση των τηλεπικοινωνιών και των ηλεκτρονικών συναλλαγών σε όλο τον κόσμο. Αυτές οι ηλεκτρονικές επικοινωνίες και συναλλαγές ποικίλουν από αποστολή και λήψη πακέτων δεδομένων μέσω του Διαδικτύου ή αποθήκευση πολυμεσικών δεδομένων, έως και κρίσιμες οικονομικές ή/και στρατιωτικές υπηρεσίες. Όμως, αυτή η εξέλιξη αναδεικνύει την ανάγκη για περισσότερη ασφάλεια, ιδιαίτερα στις περιπτώσεις όπου οι πληροφορίες που ανταλλάσονται αφορούν ευαίσθητα ή/και εμπιστευτικά δεδομένα. Σε αυτές τις περιπτώσεις, η ασφάλεια θεωρείται αναπόσπαστο χαρακτηριστικό των εμπλεκομένων εφαρμογών και συστημάτων. Οι συναρτήσεις κατακερματισμού παίζουν έναν πολύ σημαντικό ρόλο στον τομέα της ασφάλειας και, όπως συμβαίνει στην πλειοψηφία των βασικών αλγορίθμων ασφαλείας, οι υλοποιήσεις σε λογισμικό (software) επικρατούν στις μέρες μας. Παρόλα αυτά, οι υλοποιήσεις σε υλικό (hardware) είναι η κύρια επιλογή οσον αφορά στρατιωτικές εφαρμογές και εμπορικές εφαρμογές κρίσιμης ασφάλειας. Η NSA, για παράδειγμα, εξουσιοδοτεί μόνο υλοποιήσεις σε υλικό. Αυτό γιατί οι υλοποιήσεις σε υλικό είναι πολύ γρηγορότερες από τις αντίστοιχες σε λογισμικό, ενώ προσφέρουν και υψηλά επίπεδα «φυσικής» ασφάλειας λόγω κατασκευής. Έτσι, όσον αφορά τις κρυπτογραφικές συναρτήσεις κατακερματισμού, όπως ίσχυει γενικά στις υλοποιήσεις υλικού, ανακύπτουν τρία (ανάμεσα σε άλλα) κύρια θέματα: Επιδόσεις, Αξιοπιστία, Ευελιξία. Σκοπός της παρούσας διατριβής είναι να παράσχει λύσεις υλοποίησης σε υλικό για κρυπτογραφικές συναρτήσεις κατακερματισμού, στοχεύοντας στα τρία κύρια ζητήματα που αφορούν υλοποιήσεις σε υλικό, τα οποία και προαναφέρθηκαν (Επιδόσεις, Αξιοπιστία, Ευελιξία). Συγκεκριμένα, προτείνονται μεθοδολογίες σχεδιασμού αρχιτεκτονικών υλικού (καθώς και οι αρχιτεκτονικές αυτές καθαυτές) για τις οικογένειες SHA-1 και SHA-2 οι οποίες επιτυγχάνουν υψηλή ρυθμαπόδοση με λογική αύξηση της επιφάνειας ολοκλήρωσης. Επίσης, προτείνονται αρχιτεκτονικές οι οποίες επιτυγχάνουν υψηλή ρυθμαπόδοση με λογική αύξηση της επιφάνειας ολοκλήρωσης για νέες κρυπτογραφικές συναρτήσεις, δηλαδή για τις JH και Skein. Ακόμα, προτείνονται μεθοδολογίες σχεδιασμού αρχιτεκτονικών υλικού (καθώς και οι αρχιτεκτονικές αυτές καθαυτές) για τις οικογένειες SHA-1 και SHA-2 οι οποίες έχουν τη δυνατότητα να ανιχνέυουν πιθανά λάθη κατά τη λειτουργία τους ενώ επιτυγχάνουν υψηλή ρυθμαπόδοση με λογική αύξηση της επιφάνειας ολοκλήρωσης. Τέλος, προτείνονται μεθοδολογίες σχεδιασμού πολύ-τροπων αρχιτεκτονικών υλικού (καθώς και οι αρχιτεκτονικές αυτές καθ’αυτές) για τις οικογένειες SHA-1 και SHA-2 οι οποίες έχουν τη δυνατότητα να υποστηρίξουν παραπάνω από μία συνάρτηση ενώ επιτυγχάνουν υψηλή ρυθμαπόδοση με λογική αύξηση της επιφάνειας ολοκλήρωσης.