Power consumption is one of the main design constraints in today’s integrated circuits. For systems powered by small non-rechargeable batteries over their entire lifetime, such as medical implant devices, ultra-low power consumption is paramount. In these systems, analog-to-digital converters (ADCs) are key components as the interface between the analog world and the digital domain. This thesis addresses the design challenges, strategies, as well as circuit techniques of ultra-low-power ADCs for medical implant devices. Medical implant devices, such as pacemakers and cardiac defibrillators, typically requirelow-speed, medium-resolution ADCs. The successive approximation register (SAR) ADC exhibits significantly high energy efficiency compared to other prevalent ADC architectures due to its good tradeoffs among power consumption, conversion accuracy, and design complexity. To design an energy-efficient SAR ADC, an understanding of its error sources as well as its power consumption bounds is essential. This thesis analyzes the power consumption bounds of SAR ADC: 1) at low resolution, the power consumption is bounded by digital switching power; 2) at medium-to-high resolution, the power consumption is bounded by thermal noise if digital assisted techniques are used to alleviate mismatch issues; otherwise it is bounded by capacitor mismatch.  Conversion of the low frequency bioelectric signals does not require high speed, but ultra-low-power operation. This combined with the required conversion accuracy makes the design of such ADCs a major challenge. It is not straightforward to effectively reduce the unnecessary speed for lower power consumption using inherently fast components in advanced CMOS technologies. Moreover, the leakage current degrades the sampling accuracy during the long conversion time, and the leakage power consumption contributes to a significant portion of the total power consumption. Two SAR ADCs have been implemented in this thesis. The first ADC, implemented in a 0.13-µm CMOS process, achieves 9.1 ENOB with 53-nW power consumption at 1 kS/s. The second ADC, implemented in a 65-nm CMOS process, achieves the same resolution at 1 kS/s with a substantial (94%) improvement in power consumption, resulting in 3-nW total power consumption. Our work demonstrates that the ultra-low-power operation necessitates maximum simplicity in the ADC architecture.

With the introduction of Internet of Things (IoT) technology in several sectors, wireless, reliable, and energy-saving communication in distributed sensor networks are more important than ever. Thereby, wake-up technologies are becoming increasingly important as they significantly contribute to reducing the energy consumption of wireless sensor nodes. In an indoor environment, the use of wireless sensors, in general, is more challenging due to signal fading and reflections and needs, therefore, to be critically investigated. This paper discusses the performance analysis of wakeup receiver (WuRx) architectures based on two low frequency (LF) amplifier approaches with regard to sensitivity, power consumption, and package error rate (PER). Factors that affect systems were compared and analyzed by analytical modeling, simulation results, and experimental studies with both architectures. The developedWuRx operates in the 868MHz band using on-off-keying (OOK) signals while supporting address detection to wake up only the targeted network node. By using an indoor setup, the signal strength and PER of received signal strength indicator (RSSI) in different rooms and distances were determined to build a wireless sensor network. The results show a wake-up packets (WuPts) detection probability of about 90% for an interior distance of up to 34 m.

Thesis (PhD)-- Stellenbosch University, 2013. / ENGLISH ABSTRACT: Superconducting electronics can make the Square Kilometre Array (SKA) a better instrument. The largest radio telescope in the world will consist of several arrays, the largest of which, consisting of more than 3000 dishes, will be situated primarily in South Africa. The ambitions of the SKA are grand and their realisation requires technology that does not exist today. Current plans see signals in the band of interest ampli ed, channelised, mixed down and then digitised. An all-digital frontend could simplify receiver structure and improve its performance. Semiconductor (analog-to-digital converters) ADCs continue to make great progress and will likely nd applications in the SKA, but superconductor ADCs bene t from higher clock speeds and quantum accurate quantisation. We propose a superconducting softwarede ned radio frontend. The key component of such a frontend is a superconducting ash ADC. We show that employing such an ADC, even a small- to moderately-sized one, will signi cantly improve the instantaneous bandwidth observable by the SKA, yet retain adequate signal-to-noise ratio so as to achieve a net improvement in sensitivity. This improvement could approach factor 2 when compared to conventional technologies (at least for continuum observations). We analyse key components of such an ADC analytically, numerically and experimentally and conclude that fabrication of such an ADC for SKA purposes is certainly possible and useful. Simultaneously, we address the power requirements of high-performance computing (HPC). HPC on a hitherto unprecedented scale is a necessity for processing the vast raw data output of the SKA. Utilising the ultra-low-energy switching events of superconducting switches (certain Josephson junctions), we develop rst demonstrators of the promising eSFQ logic family, achieving experimentally veri ed shift-registers and deserialisers with sub-aJ/bit energy requirements. We also propose and show by simulation how to expand the applicability of the eSFQ design concept to arbitrary (unclocked) gates. / AFRIKAANSE OPSOMMING: Supergeleier-elektronika kan 'n beter instrument maak van die \Square Kilometre Array" (SKA). Die wêreld se grootse radioteleskoop sal bestaan uit etlike skikkings, waarvan die grootste - met meer as 3 000 skottels - hoofsaaklik in Suid-Afrika gesetel sal wees. Die SKA is ambisieus en vereis tegnologie wat nog nie vandag bestaan nie. Volgens huidige planne sal seine in die band van belang versterk, gekanalisieer, afgemeng en dan versyfer word. 'n Heel-digitale kopstuk sal die ontvangerstruktuur kan vereenvoudig en sy prestasie kan verbeter. Halfgeleier analoog-na-digital omsetters (ADOs) verbeter voortdurend en sal waarskynlik toepassings in die SKA vind, maar supergeleier ADOs trek voordeel uit hoër klok spoed en kwantumakkurate kwantisering. Ons stel 'n supergeleier sagteware-gede nieerde radio kopstuk voor. Die sleutelkomponent van so 'n kopstuk is 'n supergeleier \ ash" ADO. Ons toon hoe die gebruik van so 'n ADO, selfs een van klein tot matige bisgrootte, die oombliklike bandwydte waarneembaar deur die SKA aansienlik sal verbeter en 'n voldoende sein-tot-ruis verhouding sal behou, en gevolglik 'n netto verbetering in sensitiwiteit sal bereik. Hierdie verbetering kan, vergeleke met konvensionele tegnologie, 'n faktor van 2 nader (ten minste vir kontinuum waarnemings). Ons analiseer belangrike komponente van so 'n ADO analities, numeries and eksperimenteel en lei af dat die vervaardiging van so 'n ADO vir SKA doeleindes beide moontlik en nuttig is. Terselfdertyd spreek ons die drywingsverkwisting van Hoë-verrigting rekenaars aan. Sulke rekenaars van 'n tot dusver ongekende skaal is 'n noodsaaklikheid vir die verwerking van die enorme rou data uitset van die SKA. Deur die gebruik van die ultra-lae-energie skakels van supergeleier skakelaars (sekere Josephson-vlakke), ontwikkel ons die eerste demonstratiewe hekke van die veelbelowende eSFQ logiese familie, en toon eksperimenteel bevestigte skuifregisters en deserieëliseerders met sub-aJ/bis energievereistes. Ons stel verder voor en wys met simulasies hoe om die toepaslikheid van die eSFQ ontwerpkonsep na arbitr^ere (ongeklokte) hekke uit te brei.

Since their emergence, Wireless Sensor Networks (WSN) have been growing continually becoming a key player in many applications such as military tracking, remote monitoring, bio-sensing and home automation. These networks are based on IEEE 802.15.4 standard which is dedicated to low rate wireless personal area networks (LR-WPANs) in the unlicensed radio band (868MHz/915MHz/2.4GHz). Low power consumption, low cost of implementation and high level of integration are the main challenges of these systems. As radio frequency transceiver is one of the most power hungry block in wireless sensor node, power consumption of radio frequency front-end (RFFE) must be reduced. To deal with, several approaches are possible, either at circuit level by investigating operating modes of transistors and merging functionalities or at system level by searching novel demodulation architecture. This thesis explores the specific requirements and challenges for the design of ultra-low power radio frequency integrated circuits (RFICs), leading to the design of a compact demodulator implemented in 65 nm CMOS technology and compatible with all modulation schemes.

Nanomagnetic logic, incorporating logic bits in the magnetization orientations of single-domain nanomagnets, has garnered attention as an alternative to transistor-based logic due to its non-volatility and unprecedented energy-efficiency. The energy efficiency of this scheme is determined by the method used to flip the magnetization orientations of the nanomagnets in response to one or more inputs and produce the desired output. Unfortunately, the large dissipative losses that occur when nanomagnets are switched with a magnetic field or spin-transfer-torque inhibit the promised energy-efficiency. Another technique offering superior energy efficiency, “straintronics”, involves the application of a voltage to a piezoelectric layer to generate a strain which is transferred to an elastically coupled magnetrostrictive layer, causing magnetization rotation. The functionality of this scheme can be enhanced further by introducing magnetocrystalline anisotropy in the magnetostrictive layer, thereby generating four stable magnetization states (instead of the two stable directions produced by shape anisotropy in ellipsoidal nanomagnets). Numerical simulations were performed to implement a low-power universal logic gate (NOR) using such 4-state magnetostrictive/piezoelectric nanomagnets (Ni/PZT) by clocking the piezoelectric layer with a small electrostatic potential (~0.2 V) to switch the magnetization of the magnetic layer. Unidirectional and reliable logic propagation in this system was also demonstrated theoretically. Besides doubling the logic density (4-state versus 2-state) for logic applications, these four-state nanomagnets can be exploited for higher order applications such as image reconstruction and recognition in the presence of noise, associative memory and neuromorphic computing. Experimental work in strain-based switching has been limited to magnets that are multi-domain or magnets where strain moves domain walls. In this work, we also demonstrate strain-based switching in 2-state single-domain ellipsoidal magnetostrictive nanomagnets of lateral dimensions ~200 nm fabricated on a piezoelectric substrate (PMN-PT) and studied using Magnetic Force Microscopy (MFM). A nanomagnetic Boolean NOT gate and unidirectional bit information propagation through a finite chain of dipole-coupled nanomagnets are also shown through strain-based "clocking". This is the first experimental demonstration of strain-based switching in nanomagnets and clocking of nanomagnetic logic (Boolean NOT gate), as well as logic propagation in an array of nanomagnets.

Dans les dernières années, beaucoup de travail a été consacré par l’industrie électronique pour réduire la consommation d’énergie des composants micro-électroniques qui représente un fardeau important dans la spécification des nouveaux systèmes.Afin de réduire la consommation d’énergie, nombreuses stratégies peuvent être adoptées au niveau des systèmes micro-électroniques et des simples dispositifs nano-électroniques. Récemmentle Transistor Tunnel `a effet de champ (Tunnel-FET) s’est imposé comme un candidat possible pour remplacer les dispositifs MOSFET conventionnels pour applications de tr`es basse puissance à des tensions d’alimentation VDD < 0.5V. Nous présentons un modèle Multi-Subband Monte Carlo modifié (MSMC) qui a été adapté pour la simulation de TFET Ultra Thin Body Fully Depleted Seminconductor on Insulator (FDSOIUTB) avec homo- et hétéro-jonctions et des matériaux semi-conducteurs arbitraires. Nous prenons en considération la quantification de la charge avec une correction quantique heuristique mais précise, validée via des modèles quantiques complets et des résultats expérimentaux.Le modèle MSMC a été utilisé pour simuler et évaluer la performance de FD-SOI TFET sidéealisées avec homo- et hétéro-jonction en Si, alliages SiGe ou composés InGaAs. Dans la deuxième partie de l’activité de doctorat un travail de caractérisation à basse températurea été réalisé sur les TFETs en Si et SiGe homo- et hétéro-jonction fabriqués par le centre de recherche français du CEA -LETI. L’objectif est d’estimer la présence de l’effet Tunnel comme principal mécanisme d’injection et la contribution d’autres mécanismes d’injection comme le Trap Assisted Tunneling. / In the last years a significant effort has been spent by the microelectronic industry to reducethe chip power consumption of the electronic systems since the latter is becoming a majorlimitation to CMOS technology scaling.Many strategies can be adopted to reduce the power consumption. They range from thesystem to the electron device level. In the last years Tunnel Field Effect Transistors (TFET)have imposed as possible candidate devices for replacing the convential MOSFET in ultra lowpower application at supply voltages VDD < 0.5V. TFET operation is based on a Band-to-BandTunneling (BtBT) mechanism of carrier injection in the channel and they represent a disruptiverevolutionary device concept.This thesis investigates TFET modeling and simulation, a very challenging topic becauseof the difficulties in modeling BtBT accurately. We present a modified Multi Subband MonteCarlo (MSMC) that has been adapted for the simulation of Planar Ultra Thin Body (UTB)Fully Depleted Semiconductor on Insulator (FD-ScOI) homo- and hetero-junction TFET implementedwith arbitrary semiconductor materials. The model accounts for carrier quantizationwith a heuristic but accurate quantum correction validated by means of comparison with fullquantum model and experimental results.The MSMC model has been used to simulate and assess the performance of idealized homoandhetero-junction TFETs implemented in Si, SiGe alloys or InGaAs compounds.In the second part of the thesis we discuss the characterization of TFETs at low temperature.Si and SiGe homo- and hetero-junction TFETs fabricated by CEA-LETI (Grenoble,France) are considered with the objective to identify the possible presence of alternative injectionmechanisms such as Trap Assisted Tunneling. / Negli ultimi anni uno sforzo significativo `e stato speso dall’industria microelettronica per ridurreil consumo di potenza da parte dei sistemi microelettronici. Esso infatti sta diventando unadelle limitazioni pi`u significative per lo scaling geometrico della tecnologia CMOS.Diverse strategie possono essere adottate per ridurre il consumo di potenza considerando ilsistema microelettronico nella sua totalit`a e scendendo fino a giungere all’ottimizzazione delsingolo dispositivo nano-elettronico. Negli ultimi anni il transistore Tunnel FET (TFET) si`e imposto come un possibile candidato per rimpiazzare, in applicazioni a consumo di potenzaestremamente basso con tensioni di alimentazione inferiori a 0.5V, i transistori convenzionaliMOSFET. Il funzionamento del TFET si basa sul meccanismo di iniezione purament quantisticodel Tunneling da banda a banda (BtBT) e che dovrebbe permettere una significativa riduzionedella potenza dissipata. Il BtBT nei dispositivi convenzionali `e un effetto parassita, nel TFETinvece esso `e utilizzato per poter ottenere significativi miglioramenti delle performance sottosogliae pertanto esso rappresenta una nuova concezione di dispositivo molto innovativa erivoluzionaria.Questa tesi analizza la modellizazione e la simulazione del TFET. Questi sono argomenti moltocomplessi vista la difficolt`a che si hanno nel modellare accuratamente il BtBT. In questo lavoroviene presentata una versione modificata del modello di trasporto Multi Subband Monte Carlo(MSMC) adattato per la simulazione di dispositivi TFET planari Ultra Thin Body Fully DepletedSilicon on Insulator (UTB FD-SOI), implementati con un canale composto da un unicosemiconduttore (omogiunzione) o con differenti materiali semiconduttori (eterogiunzione). Ilmodello proposto tiene il conto l’effetto di quantizzazione dovuto al confinamento dei portatoridi carica, con un’euristico ma accurato sistema di correzione. Tale modello `e stato poivalidato tramite una comparazione con altri modelli completamente quantistici e con risultatisperimentali.Superata la fase di validazione il modello MSMC `e utilizzato per simulare e verificare le performancedi dispositivi TFET implementati come omo o eterogiunzione in Silicio, leghe SiGe,o composti semiconduttori InGaAs.Nella seconda parte della tesi viene illustrato un lavoro di caratterizazione di TFET planari abassa temperatura (fino a 77K). Sono stati misurati dispositivi in Si e SiGe a omo o eterogiuzioneprodotti nella camera bianca del centro di ricerca francese CEA-LETI di Grenoble. Tramite talimisure `e stato possibile identificare la probabile presenza di meccanismi di iniezione alternativial BtBT come il Tunneling assistito da trappole (TAT) dimostrando come questo effetto `e,con ogni probabilit`a, la causa delle scarse performance in sottosoglia dei dispositivi TFETsperimentali a temperatura ambiente.

Les progrès réalisés durant ces dernières années dans le domaine de la microélectronique et notamment vis-à-vis de l’augmentation exponentielle de la densité d’intégration des composants et des systèmes a participé activement à l’apparition et au développement de systèmes portables communicants de plus en plus performants et polyvalents. La R&D dans les technologies de stockage d’énergie n’a pas suivi cette tendance d’évolution très rapide ; ce qui constitue un handicap majeur dans les évolutions futures des systèmes portables. La transmission d’énergie sans fils sur des distances considérables (plusieurs dizaines de mètres) grâce aux microondes constitue une solution très prometteuse pour pallier aux problèmes d’autonomie dans le cas des systèmes sans fils communicants. De plus, du fait de l’omniprésence des ondes électromagnétiques dans notre environnement avec des niveaux plus ou moins importants, la récupération et l’exploitation de cette énergie libre est également possible. La rectenna (Rectifying Antenna) est le dispositif permettant de capter et de convertir une onde électromagnétique en une tension continue. Plusieurs travaux de thèse axés sur l’étude et l’optimisation de la rectenna ont été réalisés au sein du laboratoire. Ces travaux avaient montré que pour des faibles niveaux de champs les tensions délivrées par la rectenna sont généralement très faibles et inexploitables. Aussi, comme la majorité des micro-sources d’énergie et à cause de son impédance interne, les performances de la rectenna dépendent fortement de sa charge de sortie. Ainsi, le développement d’un système d’interfaçage de la rectenna est nécessaire afin de pallier ces manquements inhérents du convertisseur RF/DC. Ce genre de système d’interfaçage est généralement absent dans la littérature à cause des faibles niveaux de puissance exploités. Par conséquent, la rectenna est très souvent utilisée tel quelle ; ce qui limite fortement le champ applicatif. Dans ce projet de recherche, un système de gestion énergétique de la rectenna complètement autonome a été conçu, développé et optimisé afin de garantir les performances optimales de la rectenna quelques soient les fluctuations de la puissance d’entrée et celles de la charge de sortie. Le circuit d’interfaçage permet également de fournir à la charge des niveaux de tension utilisables. Le système réalisé est basé tout d’abord sur l’utilisation d’un convertisseur DC/DC résonant pouvant fonctionner d’une manière complètement autonome à partir de niveaux très bas de la tension et de la puissance de la source. Ce convertisseur permet donc de garantir l’autonomie du système en éliminant la nécessité d’une source d’énergie auxiliaire. A cause de ses faibles performances énergétiques, ce convertisseur ne sera utilisé que durant la phase de démarrage. L’efficacité du système en termes de rendement énergétique et d’adaptation d’impédance est garantie grâce à l’utilisation d’un convertisseur Flyback fonctionnant dans son régime de conduction discontinu. Ainsi, une adaptation d’impédance très efficace est réalisée entre la rectenna et la charge de sortie. Ce convertisseur principal fonctionnera durant le régime permanent. Les deux convertisseurs ont été optimisés pour des niveaux de tension et de puissance aussi bas que quelques centaines de mV et quelques μW respectivement. Des mesures expérimentales réalisées sur plusieurs prototypes ont démontré le bon fonctionnement et les excellentes performances prédites par la procédure de conception ; ce qui nous permet de valider notre approche. De plus, les performances obtenues se distinguent parfaitement vis-à-vis de l’état de l’art. Enfin, en fonction de l’application désirée, plusieurs synoptiques d’association des deux structures sont proposés. Ceci inclut également la gestion énergétique de la charge de sortie. / Latest advancements in microelectronic technologies and especially with the exponential increase of components and devices integration density have yield novel high technology and polyvalent portable systems. Such polyvalent communication devices need more and more available energy. Nonetheless, research in energy storage technology did not evolve with a similar speed. This constitutes a substantial handicap for the future evolution of portable devices. Wireless energy transfer through large distances such as tens of meters using microwaves is a very promising solution in order to deal with the autonomy problem in portable devices. In addition, since electromagnetic waves are ubiquitous in our environment, harvesting and using this free and available energy is also possible. Rectenna (Rectifying Antenna) is the device that allows to collect and to convert an electromagnetic wave into DC power. Several thesis research projects focusing on studying and optimizing the rectenna was carried-out into the Ampere laboratory. It has been shown that for a low level of the electromagnetic field the voltage provided by the rectenna is ultra-low and thus impractical. Further, as it is the case for the majority of energy harvesting micro-sources, the performances of the rectenna depend highly with the loading conditions. So, the development of an interfacing circuit for the rectenna is a necessary task in order to relieve the RF/DC converter inherent flaws. As it is pointed out into the literature, such power management circuit is in most cases absent due to the ultra-low power levels. In most cases, the rectenna is used as it; which reduces strongly the applications area. Within this research project, an ultra-low power and fully-autonomous power management system dedicated to rectennas was developed and optimized. It allows to guarantee highest performances of the rectenna whatever are the fluctuation of the input power level and the output load conditions. In addition, this power management system allows to provide a conventional voltage level to the load. The first part of the developed system is composed by a resonant DC/DC converter which plays the role of start-up circuit. In this case, no external energy source is required even with low voltage and ultra-low power source conditions. Because of its general poor energetic performances, this resonant converter will be used only during the start-up phase. The second part of the developed system is composed by a Flyback converter operating in its discontinuous conduction mode. Using this mode, the converter realizes static and very effective impedance matching with the rectenna in order to extract the maximum available power whatever are the input and the output conditions. Furthermore, thanks to the optimization procedure, the converter shows excellent efficiency performances even for μW power levels based on a discrete demonstrator. Finally, the converter provides conventional voltage levels allowing to power standard electronics. Experimental tests based on discrete prototypes for the both converters show distinguish results for the start-up voltage, the impedance matching effectiveness and the efficiency as regard to the state of the art.

<p> </p><div> <div> <div> <p> </p><div> <div> <div> <p> </p><div> <div> <div> <p>The current state of the art in biopotential recordings rely on radiative electromagnetic (EM) fields. In such transmissions, only a small fraction of this energy is received since the EM fields are widely radiated resulting in lossy inefficient systems. Using the body as a communication medium (similar to a ’wire’) allows for the containment of the energy within the body, yielding order(s) of magnitude lower energy than radiative EM communication. The first part of this work introduces Animal Body Communication for untethered rodent biopotential recording and for the first time this work develops the theory and models for animal body communication circuitry and channel loss. In vivo experimental analysis proves that ABC successfully transmits acquired electrocardiogram (EKG) signals through the body with correlation greater than 99% when compared to traditional wireless communication modalities, with a 50x reduction in power consumption. The second part of this work focusses on the analysis and design of an Electro-Quasistatic Human Body Communication (EQS-HBC) system for simultaneous sensing and transmission of biopotential signals. In this work, detailed analysis on the system level interaction between the sensing and transmitting circuitry is studied and a design to enable simultaneous sensing and transmission is proposed. Experimental analysis was performed to understand the interaction between the Right Leg-Drive circuitry and the HBC transmission along with the effect of the ADC quantization on signal quality. Finally, experimental trials proves that EKG signals can be transmitted through the body with greater than 96% correlation when compared to Bluetooth systems at extremely low powers. </p> </div> </div> </div> </div> </div> </div> </div> </div> </div>

In ultra-low power Wireless Sensor Networks (WSNs) sensor nodes need to interact, depending on the application, even at a rapid pace while preserving battery life. Wireless communication brings thereby quite the burden as the radio transceiver requires a relative huge amount of power during both transmission or reception phases. In WSNs with on demand communication, the sensor nodes are required to maintain responsiveness and to act the sooner they receive a request, reducing the overall latency of the network. The aspect is more challenging in asynchronous WSN as the receiver possesses no information about the packet arrival time. In a purely on-demand communication, duty-cycling shows little to almost no improvement. The receiving node, in such scheme, is expected to last for years while also being accessible to other peers. Here arises the utility of an external ultra-low power radio receiver known as Wake-up Receiver (WuRx). Its essential task is to remain as the only part of the system running while the rest of the systems enters the lowest power mode (i.e., sleep state). Once a request signal is received, it notifies the host processor and other peripherals for an incoming communication. With the sensor node being in sleep state (WuRx active only), substantial power levels can be achieved. If the WuRx is able to interact rapidly, the added latency remains negligible. As crucial performance figures, the sensitivity and bit rate are immediately affected by the extreme low-power budget at diifferent magnitudes, depending mainly on the incorporated architecture. This thesis focuses on the design of a feature-balanced WuRx. The passive radio frequency architecture (PRF) relies on passive detection while consuming zero power to extract On-Off-Keying (OOK) modulated envelopes. The featured sensitivity, however, is reduced compared to more complex architectures. A WuRx based on PRF architecture can effectively enable short-range applications. The sensitivity can vary with respect to several parameters including the total generated noise, circuit technology and topology. Two variants of the PRF WuRxs are introduced with the baseband amplifier being the main change. The first revision employs a high performance amplifier with reduced average energy consumption, thanks to a novel power gating control. The second variant focuses on employing an ultra-low power baseband amplifier as it is expected to be in a continuous active state. This thesis also brings the necessary analysis on the passive front-end with the intention to enhance the overall WuRx sensitivity. Proof of concepts are embedded in sensor node boards and feature -61 dBm and -64 dBm of sensitivity for the first and the second variant, respectively, at a packet-error-rate (PER) of 1% whilst demanding a similar power of 7.2 µW during packet listening. During packet decoding, the first variant demands a 150 µW of power, caused greatly by the baseband amplifier. The achieved latency is less than 30 ms and the bit rate is 4 kbit/s, Manchester encoding. For long-range applications, a higher sensitivityWuRx is proposed based on Tuned-RF (TRF) architecture. By embedding a low-noise amplifier (LNA) in the receiver chain, very weak radio signal can be detected. TheWuRx emphasizes higher sensitivity of -90 dBm. The design of the LNA prioritized the highest gain and lowest bias current by sacrifcing the linearity that poses little impact on signal integrity for the OOK modulated signals. The total active power consumption of the TRF WuRx is 1.38 mW. In this work, a fast sampling approach based on power gating protocol allows a drastic reduction in energy consumption on average. By being able to sample in matter of few microseconds, the WuRx is able to detect the presence of a packet and return to sleep state right after packet decoding. Being power-gated dropped the average power consumption to 2.8 µW at a packet detection latency of 32 ms for less than 2 s of interval time between communication requests. The proposed solutions are able to decode a minimum length of 16-bit pattern and operate in the license-free ISM band 868 MHz. This thesis also includes the analysis and implementation of low-power front-end building blocks that are employed by the proposed WuRx.:1 Introduction 1.1 Motivation 1.2 Wake-up Receiver Design Requirements 1.2.1 Energy Consumption 1.2.2 Network Coverage and Robustness 1.2.3 Wake-up Packet Addressing 1.2.4 WuPt Detection Latency 1.2.5 Hosting System, Form-factor and Fabrication Technology 1.3 Thesis Organisation 2 Wireless Sensor Networks 2.1 Radio Communication 2.1.1 Electromagnetic Spectrum 2.1.2 Link Budget Analysis 2.2 Asynchronous Radio Receiver Duty-cycle Control 2.2.1 B-MAC and X-MAC Protocols 2.2.2 Energy and Latency Analysis 2.3 Power Supply Requirements 2.3.1 Low Self-discharge Battery 2.3.2 Energy Harvester 2.4 Summary 3 State-of-the-Art of Wake-up Receivers 3.1 Wake-up Receiver Architectural Analysis 3.1.1 Passive RF Detector 3.1.2 Classical Radio Architectures 3.2 Wake-up Receiver Back-end Stages 3.2.1 Baseband Amplifiers 3.2.2 Analog to Digital Conversion 3.2.3 Wake-up Packet Decoder 3.3 Power Consumption Reduction at Circuit Level 3.3.1 Power Gating 3.3.2 Interference Rejection and Filtering 3.4 Summary 4 Proposal of Novel Wake-up Receivers 4.1 Ultra-low Power On-demand Communication in Wireless Sensor Networks: Challenges and Requirements 4.2 Passive RF Wake-up Receiver 4.3 Power-gated Tuned-RF Wake-up Receiver 5 Low-power RF Front-end 5.1 Narrow-band Low-noise Amplifier (LNA) 5.1.1 Topology 5.1.2 Voltage Gain 5.1.3 Stability 5.1.4 Noise Figure 5.1.5 Linearity 5.2 Envelope Detector 5.2.1 Theory of Square-law Detection and Sensitivity Analysis 5.2.2 Single-Diode Envelope Detector 5.2.3 Voltage Multiplier Envelope Detector 5.3 Hardware Assessment 5.3.1 LNA 5.3.2 Envelope Detector 5.4 Summary 6 Passive RF Wake-up Receiver 6.1 Circuit Implementation 6.1.1 Address Decoder 6.1.2 Envelope Detector 6.1.3 Power-gated Baseband Amplifier 6.1.4 Ultra Low-power Baseband Amplifier 6.2 Experimental Results 6.2.1 Wireless Sensor Node 6.2.2 Measurements 6.3 Summary 7 Power-gated Tuned-RF Wake-up Receiver 7.1 Power-gating Protocol 7.2 Circuit Design 7.2.1 Radio Front-end 7.2.2 Data Slicer 7.2.3 Digital Baseband 7.3 Performance Evaluation 7.4 Summary 8 Conclusion 8.1 Performance Summary 8.2 Future Perspective 8.3 Applications A Two-tone Simulation Setup B Diode Models and Simulation Setup C Preamble Detection C Code Implementation Bibliography Publications / In drahtlosen Sensornetzwerken (WSNs) mit extrem geringem Stromverbrauch müssen Sensorknoten je nach Anwendung kurze Latenzzeiten erreichen ohne die Batterielebensdauer zu beeinträchtigen. Die drahtlose Kommunikation bringt dabei eine ziemliche Belastung mit sich, da der Funktransceiver sowohl während der Sende- als auch der Empfangsphase relativ viel Strom benötigt. Einige marktfähige Funktransceiver benötigen durchschnittlich ca. 10 mA im Empfangsmodus sowie 30 mA im Sendemodus. Deshalb wird heutzutage das sogenannte Duty-Cycling mit bestimmten Sende-, Empfangs- und langen Schlafzeitintervallen eingeführt. Während der Schlafphase ist der Empfänger nicht ansprechbar. Was wiederum zu einer massiven Erhöhung der Latenzzeit führen kann. In vielen Anwendungen und insbesondere im Rahmen der Digitalisierung von Prozessen wird mittlerweile die Fähigkeit On-Demand mit sehr kurzen Latenzzeiten zu kommunizieren verlangt. Diese Anforderung steht in einem Wiederspruch zum genannten Duty-cycle Betrieb. Um dieses Dilemma zu lösen wird im Rahmen dieser Doktorarbeit ein Funkempfänger mit extrem geringen Stromverbrauch untersucht und entwickelt. Mit Hilfe des extrem niedrigen Stromverbrauches kann der Funkempfänger ständig empfangsbereit sein. Er wird zum Hauptempfänger mit dem hohen Stromverbrauch zugeschaltet, so dass nur nach Aufforderung der Hauptempfänger aktiv sein wird. Dieser Empfänger wird Wake-up Empfänger (WuRx) genannt. Seine wesentliche Aufgabe besteht darin, als einziger Teil des Gesamtknotens aktiv zu sein, während der Rest in den Modus mit dem niedrigsten Stromverbrauch versetzt wird. Sobald ein Anforderungssignal empfangen wird, weckt er den Haupt-Prozessor und andere Peripheriegeräte über eine eingehende Kommunikation. Somit ist der Aufweckempfänger essenziell für die Zuverlässigkeit der drahtlosen Kommunikation. Sein Stromverbrauch sollte im µA Bereich sein. Seine Empfangsbereitschaft hängt entscheidend von seiner Empfindlichkeit sowie Bitrate ab. Eine Verbesserung der Empfindlichkeit und Erhöhung der Bitrate würden zwangsläufig zu einer Erhöhung des Stromverbrauches führen. Im Rahmen dieser Doktorarbeit werden unterschiedliche Architekturen von Aufweckempfängern untersucht und umgesetzt. Zusammenhänge zwischen Empfindlichkeit, Bitrate und Stromverbrauch wurden analysiert und mögliche Grenzen gezeigt. Ein wesentliches Augenmerk war dabei, Off-the-Shelf Komponenten zu verwenden. Im Rahmen dieser Doktorabeit wurden in Abhängigkeit von der zu erreichenden Reichweite und Häufigkeit der Kommunikation zwei wesentliche Architekturen mit geeigneten Empfindlichkeiten und extrem geringem Stromverbrauch entwickelt. Für kurze Reichweiten wurde eine passive Hochfrequenzarchitektur (PRF Architektur) basierend auf einer passiven Erkennung von OOK-modulierten (On-Off-Keying) Signalen mittels Hüllkurvenbildung entwickelt. Die erreichte Empfindlichkeit von ca. -64 dBm stellt eine wesentliche Verbesserung gegenüber dem Stand der Technik und Forschung mit einer Empfindlichkeit von ca. -52 dBm dar. Die Empfindlichkeit kann in Bezug auf verschiedene Parameter variieren, einschließlich des insgesamt erzeugten Rauschens, der Schaltungstechnologie und der Topologie. Zwei Varianten der PRF WuRxs wurden realisiert, wobei der Basisbandverstärker die Hauptänderung darstellt. Die erste Version verwendet einen Hochleistungsverstärker mit reduziertem durchschnittlichen Energieverbrauch dank einer neuartigen Leistungssteuerung. Die zweite Variante konzentriert sich auf die Verwendung eines Basisbandverstärkers mit extrem geringer Leistung, da erwartet wird, dass er sich in einem kontinuierlichen aktiven Zustand befindet. Diese Arbeit bringt auch die notwendige Analyse des passiven Front-Ends mit der Absicht, die allgemeine WuRx-Empfindlichkeit zu verbessern. Nachweise der Wirksamkeit sind in Sensorknotenmodulen eingebettet und verfügen über -61 dBm und -64 dBm Empfindlichkeit für die erste bzw. die zweite Variante bei einer Paketfehlerrate (PER) von 1 %, während beim Abhören von Paketen eine ähnliche Leistung von 7.2 µW gefordert wird. Während der Paketdecodierung erfordert die erste Variante eine Leistung von 150 µW, die stark durch den Basisbandverstärker verursacht wird. Die erreichte Latenz beträgt weniger als 30 ms und die Bitrate beträgt 4 kbit/s mit einer Manchester-Codierung. Für Anwendungen mit großer Reichweite wird ein WuRx mit höherer Empfindlichkeit vorgeschlagen. Dieser basiert auf einer TunedRF (TRF) -Architektur. Dabei werden sehr schwache Funksignale durch einen rauscharmen Verstärker (LNA) erkannt und verstärkt. Der WuRx erreicht eine bessere Empfindlichkeit von ca. –90 dBm. Dabei wurde das Augenmerk auf die höchste Verstärkung verbunden mit dem niedrigsten Vorspannungsstrom gelegt. Der LNA wird dann im nicht-linearen Bereich betrieben. Dieser Betriebsmodus beeinflusst nur im geringeren Maße die Signalintegrität der OOK-modulierten Signale. Der gesamte Leistungsverbrauch des TRF WuRx beträgt 1.38 mW. Um den Gesamtleistungsverbrauch im µW Bereich zu reduzieren, wird im Rahmen dieser Arbeit das sogenannte Power-Gating-Protokoll eingeführt. Dabei wird das Funkkanal zyklisch abgetastet. Der WuRx kann innerhalb von wenigen Mikrosekunden das Vorhandensein eines Pakets erkennen und direkt nach der Paketdecodierung in den Ruhezustand zurückkehren. Durch diesen Ansatz konnte der durchschnittliche Stromverbrauch bei einer Paketerkennungslatenz von ca. 32 ms innerhalb einer Abtastrate von 2 s auf 2.8 µW reduziert werden. Die vorgeschlagenen Lösungen können eine Mindestlänge von 16-Bit-Mustern decodieren und im lizenzfreien ISM-Band 868 MHz arbeiten.:1 Introduction 1.1 Motivation 1.2 Wake-up Receiver Design Requirements 1.2.1 Energy Consumption 1.2.2 Network Coverage and Robustness 1.2.3 Wake-up Packet Addressing 1.2.4 WuPt Detection Latency 1.2.5 Hosting System, Form-factor and Fabrication Technology 1.3 Thesis Organisation 2 Wireless Sensor Networks 2.1 Radio Communication 2.1.1 Electromagnetic Spectrum 2.1.2 Link Budget Analysis 2.2 Asynchronous Radio Receiver Duty-cycle Control 2.2.1 B-MAC and X-MAC Protocols 2.2.2 Energy and Latency Analysis 2.3 Power Supply Requirements 2.3.1 Low Self-discharge Battery 2.3.2 Energy Harvester 2.4 Summary 3 State-of-the-Art of Wake-up Receivers 3.1 Wake-up Receiver Architectural Analysis 3.1.1 Passive RF Detector 3.1.2 Classical Radio Architectures 3.2 Wake-up Receiver Back-end Stages 3.2.1 Baseband Amplifiers 3.2.2 Analog to Digital Conversion 3.2.3 Wake-up Packet Decoder 3.3 Power Consumption Reduction at Circuit Level 3.3.1 Power Gating 3.3.2 Interference Rejection and Filtering 3.4 Summary 4 Proposal of Novel Wake-up Receivers 4.1 Ultra-low Power On-demand Communication in Wireless Sensor Networks: Challenges and Requirements 4.2 Passive RF Wake-up Receiver 4.3 Power-gated Tuned-RF Wake-up Receiver 5 Low-power RF Front-end 5.1 Narrow-band Low-noise Amplifier (LNA) 5.1.1 Topology 5.1.2 Voltage Gain 5.1.3 Stability 5.1.4 Noise Figure 5.1.5 Linearity 5.2 Envelope Detector 5.2.1 Theory of Square-law Detection and Sensitivity Analysis 5.2.2 Single-Diode Envelope Detector 5.2.3 Voltage Multiplier Envelope Detector 5.3 Hardware Assessment 5.3.1 LNA 5.3.2 Envelope Detector 5.4 Summary 6 Passive RF Wake-up Receiver 6.1 Circuit Implementation 6.1.1 Address Decoder 6.1.2 Envelope Detector 6.1.3 Power-gated Baseband Amplifier 6.1.4 Ultra Low-power Baseband Amplifier 6.2 Experimental Results 6.2.1 Wireless Sensor Node 6.2.2 Measurements 6.3 Summary 7 Power-gated Tuned-RF Wake-up Receiver 7.1 Power-gating Protocol 7.2 Circuit Design 7.2.1 Radio Front-end 7.2.2 Data Slicer 7.2.3 Digital Baseband 7.3 Performance Evaluation 7.4 Summary 8 Conclusion 8.1 Performance Summary 8.2 Future Perspective 8.3 Applications A Two-tone Simulation Setup B Diode Models and Simulation Setup C Preamble Detection C Code Implementation Bibliography Publications

Die Weiterentwicklung klassischer, elektronischer Identifikationstechnologien leistet einen wichtigen Beitrag zum technischen Fortschritt in Industrie, Logistik und Gesundheitswesen. Die vorliegende Dissertationsschrift beschreibt die Entwicklung eines Dual-Feed-Antennendesigns für passive UHF-RFID-Transponder auf kritischen Oberflächen. Die zu Grunde liegende Antennenstruktur besteht aus einem Microstrip-Patch unter Verwendung eines verlustarmen Substratmaterials. Dieser erfährt eine Optimierung hinsichtlich seiner Lesereichweite, insbesondere auf kritischen Oberflächen. Ein Zwei-Port-Konzept mit gekoppeltem Feed-Line-Anpassnetzwerk reduziert die Anzahl benötigter, diskreter Komponenten und ermöglicht eine kostengünstige Herstellung mittels klassischer Ätzverfahren. Verschiedene Ansätze zur Modellierung und zur analytischen Berechnung der Antennenparameter werden dargestellt. Des Weiteren erfolgt eine Verifikation der Antennenstruktur anhand eines Konzepts für einen passiven Energy-Harvesting-RFID-Transponder, der zur Temperaturüberwachung in den genannten Branchen eingesetzt werden kann. Dieses Konzept schließt ein effizientes Energiemanagement mittels eines Ultra-Low-Power-Mikrocontrollers sowie Ansätze zur Energiegewinnung und -speicherung mit ein und stellt die Wahl wichtiger Systemparameter und Bauelemente anhand anwendungsspezifischer Abschätzungen dar.