As the speed of operation of VLSI devices has increased, delay fault testing has become a more important factor in VLSI testing. Due to the large number of gates in a VLSI circuit, the gate level test generation methodologies may become infeasible for delay test generation. In this work, a new behavioral delay fault model that aims at simplifying the delay test generation problem for digital circuits is presented. The model is defined using VHDL. It is shown that each defined behavioral level delay fault can be mapped to a gate level equivalent fault and/or physical failure. A systematic way of representing a behavioral model in terms of a data flow graph is presented. A behavioral level input-output path is defined and a strategy to generate tests for delay faults along a behavioral path is presented. It is then shown that tests developed from the behavioral model can test a gate level equivalent circuit for path delay faults. / Master of Science

In this thesis, several techniques for the test generation of VHDL behavioral models are proposed. An algorithm called HBTG, Hierarchical Behavioral Test Generator, is developed and implemented to systematically generate tests for VHDL behavioral models. HBTG accepts the Process Model Graph and the precomputed tests for the individual processes of the model from which it constructs a test sequence that exercises the model hierarchically. The construction of the test sequence is automatic if the tests for the individual processes of the model are provided. The test sequence derived can be used for the simulation of the model. By comparing the simulation outputs with the data sheet or the design specifications of the corresponding circuit, a user can tell if the functionality of the model is as expected or any functional faults exist. Simulation results and conclusions are given. Some suggestions for further improvements of the program are discussed. / Master of Science

This thesis describes the development of BACKANN, a tool for the back annotation of timing delays into VHDL models. BACKANN uses the Process Model Graph and the VHDL behavioral model generated by the Modeler's Assistant as the base for backannotation. BACKANN determines the delay values that are required for the signal assignments in the behavioral model. It generates a gate-level design of the model using the Synopsys Design Compiler. It extracts the values for the delays required from the gate-level design. It then back-annotates these values into the VHDL behavioral model. BACKANN is thus a design automation tool that helps the development of VHDL behavioral models with realistic timing and thus quickens the design cycle. / Master of Science

This thesis describes the development of the Process Test Generation (PTG) software for the testing of single-process VHDL behavioral models. The PTG software, along with Hierarchical Behavioral Test Generator (HBTG) and Modeler's Assistant, forms a part of the Automatic Test Generation System being developed at Virginia Tech. The PTG software transforms the VHDL description of a circuit, given by Modeler's Assistant, into a Control Flow Graph (CFG) that describes the control and data flow information in the behavioral model. The process test generation algorithm, called the PTG algorithm, uses the CFG to generate stimulus/response test sets that test all the functions of the VHDL model. The algorithm creates events on signals, propagates these events and uses simulation to obtain responses. Various features present in the software like the generation of the Control Flow Graph, the PTG algorithm, and the construction of paths through the CFG to propagate and justify events, are discussed. The test sets generated by PTG can be used for the hierarchical test generation by HBTG, which was developed earlier. Another program, called Test Bench Generator (TBG), is presented in this thesis. It is used to convert the test sequence generated by HBTG into a VHDL Test Bench that can be used for simulation. / Master of Science

Ziel der Arbeit ist die anschauliche Demonstration der Leistungsfähigkeit von Hardware- Systemen zur Regelung instabiler Systeme am Beispiel des Inversen Pendels. Dabei handelt es sich um das Balancieren eines Stabes, einem Standard-Problem der Regelungstechnik. Es wird die Konzeption und Implementierung einer Hardware-Regelung in einem FPGA-Prototypenboard zur Realisierung dieser Aufgabe beschrieben. Die Regelung basiert mit LQR-Entwurf und Kalman-Filter auf klassischen Methoden der Regelungstechnik. Zur Demonstration der Regelung wurde ein mechanischer Aufbau vorgenommen, an dem die Funktionsfähigkeit des Inversen Pendels praktisch gezeigt wurde.:1 Einleitung 11 1.1 Motivation.................................... 11 1.2 Analyse der Aufgabenstellung ......................... 11 1.3 Gliederung der Arbeit ............................. 12 2 Grundlagen 13 2.1 Referenzanwendung Inverses Pendel...................... 13 2.2 Aufbau des Regelsystems............................ 15 2.3 Verfahren zum Reglerentwurf ......................... 19 2.4 Verfahren zur Zustandsschätzung ....................... 22 2.5 Sensorik..................................... 26 2.6 Antrieb ..................................... 28 3 Inverse Pendel im Vergleich 33 3.1 Bauformen.................................... 33 3.2 Realisierungsbeispiele.............................. 34 3.3 Fazit der Recherche............................... 39 4 Elektromechanischer Aufbau 41 4.1 Mechanik .................................... 42 4.2 Sensorik..................................... 42 4.3 Antrieb ..................................... 44 4.4 FPGA-Board .................................. 47 5 Modellbildung 48 5.1 Herleitung der Systemgleichungen....................... 48 5.2 Anpassung an den Schrittmotor ........................ 51 5.3 Linearisiertes Modell im Zustandsraum.................... 51 5.4 Analyse der Modelleigenschaften........................ 52 6 Reglerentwurf 56 6.1 Einstellung des LQ-Reglers........................... 56 6.2 Einstellung des Kalman-Filters ........................ 57 6.3 Aufschwing- und Fangalgorithmus....................... 58 6.4 Simulation.................................... 60 6.5 Konsequenzen für die Realisierung....................... 63 7 Implementierung 65 7.1 Besonderheiten des Hardware-Entwurfs.................... 65 7.2 Systempartitionierung und Entwurfsstrategie . . . . . . . . . . . . . . . . . 66 7.3 Teilkomponenten ................................ 67 7.4 Modifizierung des Kalman-Filters ....................... 72 7.5 Probleme .................................... 78 8 Schluss 80 8.1 Zusammenfassung................................ 80 8.2 Ergebnisse.................................... 80 8.3 Ausblick..................................... 82 Literaturverzeichnis 84 A Details zum Projekt 87 A.1 Kurzdokumentation .............................. 87 A.2 Datei- und Verzeichnisstruktur......................... 88 A.3 Simulationsresultate .............................. 89

Η παρούσα ειδική ερευνητική εργασία εκπονήθηκε στα πλαίσια του Διατμηματικού Προγράμματος Μεταπτυχιακών Σπουδών στην “Ηλεκτρονική και Επεξεργασία της Πληροφορίας”, στο Τμήμα Φυσικής του Πανεπιστημίου Πατρών. Αντικείμενο της παρούσας εργασίας είναι η “Υλοποίηση σε FPGA του περιγραφέα HOG για ανίχνευση ανθρώπων σε εικόνες και βίντεο”. Το πρώτο κεφάλαιο αποτελεί μια εισαγωγή στις βασικότερες έννοιες που χρησιμοποιούνται στην παρούσα εργασία. Περιγράφεται επίσης η αναπτυξιακή πλακέτα που χρησιμοποιήθηκε καθώς και τα επί μέρους στοιχεία που τη συνθέτουν. Τέλος γίνεται μια συνοπτική αναφορά σε εργασίες με παρόμοιο αντικείμενο, οι οποίες με επηρέασαν στο σχεδιασμό και την υλοποίηση του συστήματός μου. Στο δεύτερο κεφάλαιο αναλύεται ο περιγραφέας Ιστογραμμάτων Προσανατολισμού της Βάθμωσης ή όπως είναι ευρύτερα γνωστός Histograms of Oriented Gradient Descriptor. Παρουσιάζονται τα βήματα όπως περιγράφονται στην εργασία των Dalal&Triggs[4] και οι βέλτιστες τιμές των παραμέτρων του περιγραφέα. Στο τρίτο κεφάλαιο ακολουθώντας τα βήματα του δευτέρου κεφαλαίου, παρουσιάζεται η διαδικασία υλοποίησης του περιγραφέα στο Matlab. Εκτός της υλοποίησης έγινε και μια προεργασία για τη μεταφορά του σε γλώσσα περιγραφής υλικού. Η προεργασία αυτή περιλαμβάνει απλοποιήσεις και τροποποιήσεις με σκοπό να μειωθεί το υπολογιστικό κόστος. Τέλος παρουσιάζονται τα αποτελέσματα δοκιμών της απόδοσης του περιγραφέα για τις διάφορες απλοποιήσεις. Στο τέταρτο κεφάλαιο γίνεται μια μικρή αναφορά στους ταξινομητές. Περιγράφονται οι ταξινομητές που δοκιμάστηκαν στην παρούσα εργασία ως προς συγκεκριμένα χαρακτηριστικά τους καθώς και την υπολογιστική τους πολυπλοκότητα για την συγκεκριμένη εφαρμογή. Το πέμπτο και τελευταίο κεφάλαιο περιλαμβάνει την περιγραφή της υλοποίησης σε VHDL. Αναλύονται τα επί μέρους κυκλώματα και όπου κρίθηκε αναγκαίο χρησιμοποιήθηκαν σχήματα ή πίνακες. Σε κάποιες περιπτώσεις δίνονται και οι κυματομορφές των κυκλωμάτων. / This thesis took place within the frame work of the Interdeparmental Master’s Program in “Electronics and Information Processing”, at the Department of Physics of University of Patras. The objective of this work is the implementation in FPGA of the HOG descriptor for the detection of people, images and videos. The first chapter is an introduction about the basic concepts, which are used across the manuscript. (Additional descriptions concern the development board which was used as well as the individual parts that compose it.) In the end, there is a brief reference to past projects focusing on similar objectives, which influenced the design and the implementation of my system. The second chapter concerns the presentation and discussion of the Histograms of Oriented Gradient descriptor. The steps of the procedure and the best parameter values of the descriptor are presented in a similar way as they are described in the paper of Dalal and Triggs. In the third chapter, following the steps of the previous one, the focus shifts to the descriptor’s implementation procedure in Matlab. Besides the implementation, there is a preparation for the transference of the descriptor in a Hardware Description Language. This preparation includes simplifications and modifications aiming at the reduction of the computational cost. Finally, we see the tests’ results of the descriptor’s performance concerning the various simplifications. The fourth chapter is a partial reference to the classifiers. The description is about the classifiers that were used in the present work with respect to their features and their computational complexity of this particular application. The fifth and final chapter refers to the description of the implementation in VHDL. There is an analysis of the partial circuits and, when necessary, shapes and tables were used. In some cases, the waveforms of the circuits are being presented.

Afin de contribuer à étendre le champ d'applications des microsystèmes à des nouvelles applications à haute valeur ajoutée mais faible série, il apparait nécessaire d'estimer et d'analyser la fiabilité d'un microsystème en prenant en compte les conditions d'utilisation. C'est pour répondre à cette problématique que les travaux de cette thèse ont été réalisés en vue de mettre en place une méthodologie d'étude de la fiabilité des microsystèmes par le biais de la modélisation. En effet, en réalisant un prototype virtuel complet d'un microsystème, on peut non seulement prédire son comportement dans n'importe quelles conditions environnementales d'utilisation mais aussi l'optimiser avant de lancer sa fabrication. Pour démontrer la faisabilité de cette méthode, les travaux ont été menés sur les actionneurs électrothermiques. Pour cela, nous avons (1) mis en place un modèle analytique du comportement idéal de la structure en utilisant la méthode des éléments finis mais surtout le langage VHDL-AMS, (2) fabriqué et caractérisé des véhicules de tests pour valider ce modèle, (3) réalisé des tests de vieillissement pour mettre en évidence les mécanismes de défaillance et enfin (4) avons mis en place des modèles empiriques de ce vieillissement pour compléter la description analytique.

This thesis describes the design guidelines from two medical teams, electrocardiogram and pulse oximetry using embedded logic circuitry such as FPGA and microcontrollers, digital filters used to filter the signals obtained from analog converters to digital, graphic obtaining the data is displayed in a graphic display GLCD, and has an interface to send data to a PC through a port USB 2 at full speed. The digital filters used are FIR filters, these filters are chosen to be linear and time invariant, developed with 40 coefficients FIR filters, these filters were implemented in the FPGA, use a FPGA that has implemented only 20 multipliers For the implementation we used the VHDL language and algorithmic state machines in order to control the 20 boxes and get the 40 products. Filtered data in the stage of the FPGA, are taken to a microcontroller that is responsible for managing the data, can lead to a graphic display GLCD, and so we can see the signal and obtained values or you can send the data to a PC right through USB port and software right through it can see the graphics on the PC.

This master thesis will cover the prestudy, hardware selection, design and implementation of a PCI Express bridge in the M.2 form factor. The thesis subject was proposed by WISI Norden who wished to extend the functionality of their hardware using an M.2 module. The bridge fits an M-Key M.2 slot and has the dimensions 80x22 mm. It is able to communicate at speeds up to 8 Gb/s over PCI Express and 200 Mbit/s on any of the 20 LVDS/CMOS pins. The prestudy determined that an FPGA should be used and a Xilinx Artix-7 device was chosen. A PCB was designed that hosts the FPGA as well as any power, debugging and other required systems. Associated proof-of-concept software was designed to verify that the bridge operated as expected. The software proves that the bridge works but requires improvement before the bridge can be used to translate sophisticated protocols. The bridge works, with minor hardware modifications, as expected. It fulfills all design requirements set in the master thesis and the FPGA firmware uses a well-established protocol, making further development easier.

Atividades de pesquisa enfocando a síntese de sistemas dedicados ou de aplicação específica têm sido bastante intensa, motivada, entre outras causas pela diversidade de aplicações desta classe de sistemas, usados seja em eletrodomésticos, seja em processamento tridimensional, navegação e guiagem, entre outros. Este trabalho trata da implementação de processadores para sistemas dedicados a partir de um conjunto de instruções específicas para uma aplicação. Este conjunto de instruções é a especificação inicial e se deseja dispor de um hardware que o suporte. A fim de auxiliar o projetista nesta situação, neste trabalho é proposta uma abordagem de projeto baseada na visão de um processador constituído de duas partes: o processador de instruções, responsável pela coordenação das operações e o processador de dados onde os dados são transformados. Neste trabalho a função do processador de instruções é desempenhada por um software enquanto que o processador de dados é implementado usando uma ferramenta de síntese para componentes programáveis.