Controlling an exoskeleton glove with a highly efficient human-machine interface (HMI), while accurately applying force to each joint remains a hot topic. This paper proposes a fast, secure, accurate, and portable solution to control an exoskeleton glove. This state of the art solution includes both hardware and software components. The exoskeleton glove uses a modified serial elastic actuator (SEA) to achieve accurate force sensing. A portable electronic system is designed based on the SEA to allow force measurement, force application, slip detection, cloud computing, and a power supply to provide over 2 hours of continuous usage. A voice-control-based HMI referred to as the integrated trigger-word configurable voice activation and speaker verification system (CVASV), is integrated into a robotic exoskeleton glove to perform high-level control. The CVASV HMI is designed for embedded systems with limited computing power to perform voice-activation and voice-verification simultaneously. The system uses MobileNet as the feature extractor to reduce computational cost. The HMI is tuned to allow better performance in grasping daily objects. This study focuses on applying the CVASV HMI to the exoskeleton glove to perform a stable grasp with force-control and slip-detection using SEA based exoskeleton glove. This research found that using MobileNet as the speaker verification neural network can increase the speed of processing while maintaining similar verification accuracy. / Master of Science / The robotic exoskeleton glove used in this research is designed to help patients with hand disabilities. This thesis proposes a voice-activated grasping system to control the exoskeleton glove. Here, the user can use a self-defined keyword to activate the exoskeleton and use voice to control the exoskeleton. The voice command system can distinguish between different users' voices, thereby improving the safety of the glove control. A smartphone is used to process the voice commands and send them to an onboard computer on the exoskeleton glove. The exoskeleton glove then accurately applies force to each fingertip using a force feedback actuator.This study focused on designing a state of the art human machine interface to control an exoskeleton glove and perform an accurate and stable grasp.

As Field Programmable Gate Arrays (FPGAs) continue to become integral parts of embedded systems, it is imperative to consider their security. While much of the research in this field is oriented toward the protection of the intellectual property contained in the FPGA's configuration, the protection of the design's integrity from malicious attack against the configuration is critical to the operation of the system. Methods for attacking the configuration are semi-invasive attacks, such as fault injection, and data tampering of incoming partial bitstreams. This thesis introduces methods for securing the integrity of an FPGA's configuration. The design and implementation is discussed for a system that consists of three parts. The first subsystem monitors the running configuration. The second subsystem authenticates partial bistreams that may be used for repairing the configuration from malicious alterations during run-time. The third subsystem indicates if the system itself succumbs to a malicious attack. The system is implemented on-chip, allowing the FPGA to effectively secure itself from attack. / Master of Science

Embedded systems are becoming nearly ubiquitous, found in a plurality of devices ranging from everyday cars and dishwashers to sophisticated spy satellites and remote sensing equipment. As the applications for embedded systems increase in number and diversity and continue to pervade our lives, a need arises to secure these systems. Whether the need arises from a desire to protect personal, proprietary, sensitive, or classified information, the security of the embedded system seeks to maintain the confidentiality and integrity of data contained within the system. Research into securing embedded systems is in its nascent stages. The generally accepted methodology of securing embedded systems involves techniques that either modify an embedded system's processor or entail custom ASIC hardware. This thesis presents a novel embedded system architecture for secure software processing that does not involve processor modification, but rather processor augmentation to ensure the confidentiality and integrity of information contained within the embedded system. Specifically, configurable logic placed at the processor periphery provides just-in-time cryptographic transformation of instructions, data, and I/O of a running embedded application. In addition to presenting the embedded secure software platform, this thesis provides a characterization of the data protection architecture of the platform. / Master of Science

The problems caused by commercial drones in air traffic, airports, and vital and military installations have increased the demand for drone detection and tracking systems. An acoustic beamforming system that tracks audio sources using 256 microphones in real-time was extended to detect and track drones. This thesis studied software-defined, multi-channel, real-time filtering solutions to improve the systems' drone detection and tracking capabilities. The sound frequencies of drone sound and disturbance noise were analyzed to create a suitable filter. Methods for implementing this filter on all channels while still operating in real-time were studied. SIMD intrinsics were used to create a few candidate algorithms, and a GPU algorithm was created as well. These algorithms were compared to each other based on execution time metrics, and the system was also analyzed for performance degradation and placement of the filtering algorithms. The results of the isolated execution time of the filtering algorithms showed the best SIMD algorithm to be operating at 0.41 milliseconds and the GPU algorithm at 0.12 milliseconds when filtering 256 samples from all 256 channels. The real-time constraint was around 5.2 milliseconds, meaning both solutions operated well below the limit. The results of the system's drone detection and tracking capabilities, when placed outdoors in a windy environment, showed the system clearly finding the drone 48% of the time without any filtering and 89% of the time with filtering. The signal-to-noise ratio was also improved by 21dB by using this filter. The results show that a software-defined multi-channel, real-time filter operating on a large data stream is a viable solution to real-time DSP applications. When specializing a beamforming application in tracking a desired frequency, filtering was revealed to be a good solution.

Driving while drowsy is a major cause behind road accidents, and exposes the driver to a much higher crash risk compared to driving while alert. Therefore, the use of assistive systems that monitor a driver’s level of vigilance and alert the fatigue driver can be significant in the prevention of accidents. This thesis introduces three different methods towards the detection of drivers’ drowsiness based on yawning measurement. All three approaches involve several steps, including the real time detection of the driver’s face, mouth and yawning. The last approach, which is the most accurate, is based on the Viola-Jones theory for face and mouth detection and the back projection theory for measuring both the rate and the amount of changes in the mouth for yawning detection. Test results demonstrate that the proposed system can efficiently measure the aforementioned parameters and detect the yawning state as a sign of a driver’s drowsiness.

Mémoire numérisé par la Division de la gestion de documents et des archives de l'Université de Montréal.

Dans le domaine des soins de santé, l'imagerie médicale a rapidement progressé et est aujourd'hui largement utilisés pour le diagnostic médical et le traitement du patient. La santé mobile devient une tendance émergente qui fournit des soins de santé et de diagnostic à distance. de plus, à l'aide des télécommunications, les données médicale incluant l'imagerie médicale et les informations du patient peuvent être facilement et rapidement partagées entre les hôpitaux et les services de soins de santé. En raison de la grande capacité de stockage et de la bande passante de transmission limitée, une technique de compression efficace est nécessaire. En tant que technique de compression d'image certifiée médicale, WAAVES fournit des taux de compression élevé, tout en assurant une qualité d'image exceptionnelle pour le diagnostic médical. Le défi consiste à transmettre à distance l'image médicale de l'appareil mobile au centre de soins de santé via un réseau à faible bande passante. Nos objectifs sont de proposer une solution de compression d'image intégrée à une vitesse de compression de 10 Mo/s, tout en maintenant la qualité de compression. Nous examinons d'abord l'algorithme WAAVES et évaluons sa complexité logicielle, basée sur un profilage précis du logiciel qui indique un complexité de l'algorithme WAAVES très élevée et très difficile à optimiser de contraintes très sévères en terme de surface, de temps d'exécution ou de consommation d'énergie. L'un des principaux défis est que les modules Adaptative Scanning et Hierarchical Enumerative Coding de WAAVES prennent plus de 90% du temps d'exécution. Par conséquent, nous avons exploité plusieurs possibilités d'optimisation de l'algorithme WAAVES pour simplifier sa mise en œuvre matérielle. Nous avons proposé des méthodologies de mise en œuvre possible de WAAVES, en premier lieu une mise en œuvre logiciel sur plateforme DSP. En suite, nous avons réalisé notre implémentation matérielle de WAAVES. Comme les FPGAs sont largement utilisés pour le prototypage ou la mise en œuvre de systèmes sur puce pour les applications de traitement du signal, leur capacités de parallélisme massif et la mémoire sur puce abondante permet une mise en œuvre efficace qui est souvent supérieure aux CPUs et DSPs. Nous avons conçu WAAVES Encoder SoC basé sur un FPGA de Stratix IV de chez Altera, les deux grands blocs coûteux en temps: Adaptative Scanning et Hierarchical Enumerative Coding sont implementés comme des accélérateurs matériels. Nous avons réalisé ces accélérateurs avec deux niveaux d'optimisations différents et les avons intégrés dans notre Encodeur SoC. La mise en œuvre du matérielle fonctionnant à 100MHz fournit des accélérations significatives par rapport aux implémentations logicielles, y compris les implémentations sur ARM Cortex A9, DSP et CPU et peut atteindre une vitesse de codage de 10 Mo/s, ce qui répond bien aux objectifs de notre thèse. / In the field of healthcare, developments in medical imaging are progressing very fast. New technologies have been widely used for the support of patient medical diagnosis and treatment. The mobile healthcare becomes an emerging trend, which provides remote healthcare and diagnostics. By using telecommunication networks and information technology, the medical records including medical imaging and patient's information can be easily and rapidly shared between hospitals and healthcare services. Due to the large storage size and limited transmission bandwidth, an efficient compression technique is necessary. As a medical certificate image compression technique, WAAVES provides high compression ratio while ensuring outstanding image quality for medical diagnosis. The challenge is to remotely transmit the medical image through the mobile device to the healthcare center over a low bandwidth network. Our goal is to propose a high-speed embedded image compression solution, which can provide a compression speed of 10MB/s while maintaining the equivalent compression quality as its software version. We first analyzed the WAAVES encoding algorithm and evaluated its software complexity, based on a precise software profiling, we revealed that the complex algorithm in WAAVES makes it difficult to be optimized for certain implementations under very hard constrains, including area, timing and power consumption. One of the key challenges is that the Adaptive Scanning block and Hierarchical Enumerative Coding block in WAAVES take more than 90% of the total execution time. Therefore, we exploited several potentialities of optimizations of the WAAVES algorithm to simplify the hardware implementation. We proposed the methodologies of the possible implementations of WAAVES, which started from the evaluation of software implementation on DSP platforms, following this evaluation we carried out our hardware implementation of WAAVES. Since FPGAs are widely used as prototyping or actual SoC implementation for signal processing applications, their massive parallelism and abundant on-chip memory allow efficient implementation that often rivals CPUs and DSPs. We designed our WAAVES Encoder SoC based on an Altera's Stratix IV FPGA, the two major time consuming blocks: Adaptive Scanning and Hierarchical Enumerative Coding are designed as IP accelerators. We realized the IPs with two different optimization levels and integrated them into our Encoder SoC. The Hardware implementation running at 100MHz provides significant speedup compared to the other software implementation including ARM Cortex A9, DSP and CPU and can achieve a coding speed of 10MB/s that fulfills the goals of our thesis.

Real-time lane detection or localization is a crucial problem in modern Advanced Driver Assistance Systems (ADAS), especially in Automated Driving System. This thesis estimates the possibility to implement a lane detection system in the available low-power embedded hardware. Various state-of-the-art Lane Detection algorithms are assessed based on a number of proposed criteria. From the result of the evaluation, three different algorithms are constructed and implemented in the hardware using OpenCV library. The lane detection stage is done with different methods: using Hough Transform for line detection or randomly sampling hypotheses which are straight lines or cubic splines over the pre-processed binary image. Weights of the hypotheses are then calculated based on their positions in the image. The hypothesis which has highest weight or best position will be chosen to represent lane marking. To increase the performance of the system, tracking stage is introduced with the help of Particle Filter or Kalman Filter. The systems are then tested with several different datasets to evaluate the speed, performance and ability to work in real-time. In addition, the system interfaces with CAN bus using a CAN interface, so that the output data can be sent as messages via the CAN bus to other systems.

Le calcul intensif joue un rôle moteur de premier plan pour de nombreux domaines scientifiques. La croissance en puissance crête des supercalculateurs a évolué du téraflops au pétaflops en l'espace d'une décennie. Toutefois, la consommation d'énergie associée extrêmement élevée ainsi que le coût associé ont motivé des recherches vers des technologies plus efficaces énergétiquement comme l'utilisation de processeurs issus du domaine des systèmes embarqués à faible puissance.Selon les prévisions, les systèmes multicœurs émergents seront constitués de centaines de cœurs d'ici la fin de la décennie. Cette évolution nécessite des solutions efficaces pour l'exploration de l'espace de conception et le débogage. Les simulateurs industriels et académiques disponibles à ce jour diffèrent en termes de compromis entre vitesse de simulation et précision. Leur adoption est généralement définie par le niveau d'exploration souhaité. Les simulateurs quasi cycle-précis sont populaires et attrayants pour l'exploration architecturale. Alors que la vitesse de simulation est trivialement observée, le niveau de précision de ces simulateurs reste souvent flou. En outre, bien que permettant une évaluation flexible et détaillée de l'architecture, les simulateurs quasi cycle-précis entraînent des vitesses de simulation lentes ce qui limite leur champ d'application pour des systèmes avec des centaines de cœurs. Cela exige des approches alternatives capables de fournir des simulations rapides tout en préservant une précision élevée ce qui est cruciale pour l'exploration architecturale.Dans cette thèse, des modèles d'architectures multicœurs complexes ont été développés et évalués en utilisant des systèmes de simulation quasi cycle-précis pour l'exploration de la performance et de la puissance. Sur cette base, une approche hybride orientée traces d'exécution a été proposée pour permettre une exploration rapide, flexible et précise des architectures multicœurs à grande échelle. Sur la base de l'environnement de simulation proposé, plusieurs configurations de systèmes manycoeurs ont été construites et évaluées en évaluant le passage à l'échelle des performances. Enfin, des configurations alternatives d'architectures multicœurs hétérogènes ont été proposées et ont montré des améliorations significatives en termes d'efficacité énergétique. / Since the computational needs precipitously grow each year, HPC technology becomes a driving force for numerous scientific and consumer areas. The most powerful supercomputer has been progressing from TFLOPS to PFLOPS throughout the last ten years. However, the extremely high power consumption and therefore the high cost pushed researchers to explore more energy-efficient technologies, such as the use of low-power embedded SoCs.The evolution of emerging manycore systems, forecasted to feature hundreds of cores by the end of the decade calls for efficient solutions for the design space exploration and debugging. Available industrial and academic simulators differ in terms of simulation speed/accuracy trade-offs. Cycle-approximate simulators are popular and attractive for architectural exploration. Even though enabling flexible and detailed architecture evaluation, cycle-approximate simulators entail slow simulation speeds, thereby limiting their scope of applicability for systems with hundreds of cores. This calls for alternative approaches capable of providing high simulation speed while preserving accuracy that is crucial to architectural exploration.In this thesis, we evaluate cycle-approximate simulation techniques for fast and accurate exploration of multi- and manycore architectures. Expecting to significantly reduce simulation time still preserving the accuracy at the cycle-approximate level, we propose a hybrid trace-oriented approach to enable flexible manycore architecture simulation. We design a set of simulation techniques to overcome the main weaknesses of the trace-oriented approach. The trace synchronization technique aims to manage control and data dependencies arising from the abstraction of processor cores. The trace replication technique is proposed to simulate manycore architectures using a finite set of pre-collected traces. The computation phase scaling technique is designed to enable flexible switching between multiple processor models without considering microarchitectural difference but taking into account the computation speed ratio. Based on the proposed simulation environment, we explore several manycore architectures in terms of performance and energy-efficiency trade-offs.

Embedded systems are present in many fields of application where failure may be critical. Such systems often possess characteristics that hampers the testing activity, as large amount of produced data and temporal requirements which must be specified and evaluated. There are tools that support the development of models for analysis and simulation still in the design stage. After being evaluated, a model may be used as basis to the implementation. In this case, it is important to ensure that the model is consistent with the specification. Otherwise, a divergence will be propagated to the final code. Therefore, the model must be tested prior to the codification. Simulink is a standard development and simulation tool for models of embedded systems. Its wide application in the industry has promoted the creation of free-software alternatives, as XCos. In the literature, there are researches which seek to improve the testing activity for Simulink-like models. The proposed solutions usually focus on test case selection strategies. However, little efforts have been directed to the oracle problem, that is, the difficulty in evaluating if an execution agrees with the specification. The objective of this doctorate proposal is to provide an oracle generation approach for Simulink-like models which addresses the characteristics previously summarized. Specifically, it is proposed a process, methods, procedures and a tool that enable the partially-automated generation of oracles for such models. As a main contribution, it is expected an improvement in the evaluation process of embedded systems in terms of quality, cost and time / Sistemas embarcados estão presentes em diversas áreas de aplicação em que falhas podem ser críticas. Tais sistemas frequentemente possuem características que tornam a fase de teste particularmente desafiadora, como a produção de grande quantidade de dados e requisitos temporais que precisam ser validados de acordo com a especificação. Existem ferramentas que auxiliam no desenvolvimento de modelos para análise e simulação do comportamento de sistemas embarcados ainda na fase de design. Após ser avaliado, o modelo pode ser usado como base para a implementação. Neste caso, deve-se buscar garantir que um modelo esteja de acordo com a especificação. Do contrário, tal divergência será propagada para a implementação. Portanto, e importante que o modelo seja testado antes da fase de implementação. Simulink e uma ferramenta-padrão de desenvolvimento e simulação de modelos de sistemas embarcados. Sua ampla aplicação na indústria incentivou a criação de alternativas de software livres como XCos. Na literatura, existem pesquisas que visam a aprimorar a atividade de teste de modelos Simulink-like. As soluções propostas geralmente focam em estratégias de seleção de casos de teste. Mas pouco esforço tem sido direcionado ao problema do oráculo, isto e, na dificuldade em avaliar se a execução está de acordo com a especificação. O objetivo desta proposta de doutorado é prover uma abordagem de geração de oráculos de teste para modelos simulink-like que contemple as características previamente resumidas. Especificamente, é proposto um processo, métodos, procedimentos e uma ferramenta que viabilizem a geração parcialmente automatizada de oráculos de teste para modelos Simulink-like. Como contribuição principal, é esperada a melhora da qualidade, custo e tempo do processo de validação de sistemas embarcados suportados por modelagem em Simulink e ferramentas similares