L’électronique souple utilisée dans les technologies RFID et NFC est aujourd’hui en plein essor et la demande croît exponentiellement chaque année. De nombreuses applications sont possibles comme les antennes RFID et les conducteurs transparents. Pour répondre à cette demande, il est nécessaire de proposer une technologie de fabrication à bas coût. Aujourd’hui les antennes sont fabriquées en R2R (Roll to Roll) par des méthodes soustractives à des coûts trop élevé et générant des déchets. Les méthodes d’impressions, qui sont additives, permettent aujourd’hui de réaliser des objets à la demande. L’objectif de cette thèse est de développer une technologie de rupture par rapport à l'existant. Les développements actuels se faisant majoritairement sur des nanoparticules d’argent, la stratégie de la thèse a été de développer un primaire métallisable (encre catalytique) pour la métallisation par voie chimique (electroless Cuivre). Dans cette étude nous avons abordés les différentes étapes qui ont permis de sélectionner le polymère adéquat pour la métallisation par voie chimique, à basse température, d'optimiser son greffage ainsi que son incorporation dans une formulation complète d’encre catalytique. Différentes preuves de concepts ont été obtenues grâce à la technologie développée par voie jet d’encre. La métallisation electroless permet d’obtenir une résistivité de 1.8 µΩ.cm et une excellente adhésion sur des substrats souples peu onéreux de faible point de transition vitreuse comme le PET et le PVC. La température du procédé de métallisation n’excède pas 50 °C. / The flexible electronics used in RFID and RFID and NFC technologies is now a booming market and demand is growing exponentially each year. Many applications are possible, such as RFID antennas and transparent conductors. To meet this demand, it is necessary to offer a low-cost manufacturing technology. Today antennas are manufactured in R2R (Roll to Roll) by subtractive methods and at high cost and generating waste. The methods of printing, which are additive, allow today to realize objects on demand. The aim of this thesis is to develop a breakthrough technology compared to the existing one. The current developments are predominantly done thanks to silver nanoparticles, the strategy of thethesis was to develop a metallizable primer (catalytic ink) for metallization by chemical means (electroless copper). In this study we will see the different steps that allowed us to select the appropriate polymer for chemical metallization, at low temperature and optimize its grafting as well as its incorporation in a complete formulation of catalytic ink. Different proofs of concepts have been obtained thanks to the technology developed by inkjet. The metallization electroless makes it possible to obtain a resistivity of 1.8 μΩ.cm and a very good adhesion on the inexpensive flexible substrates and weak point of glass transition polymer such as PET and PVC. The temperature of the metallization process does not exceed 50 °C.

Für derzeitige, industriell hergestellte Solarmodule werden Leistungsgarantien von 20 bis 25 Jahren gegeben. Das hat hohen Ansprüchen bezüglich ihrer Zuverlässigkeit, welche sich über ihre Effizienzabnahme pro Jahr definiert, zur Folge. Die Einführung neuer Technologien, wie z.B. die der PERC- (passivated emitter and rear cell) als Ersatz für die bislang dominierende BSF-Technologie (back surface field) hat eine umfangreiche Änderung der Metallisierung der Solarzellen nach sich gezogen, wodurch neue Degradationseffekte auftreten können. In der vorliegenden Arbeit werden die einzelnen Komponenten der Solarzellenmetallisierung und –verschaltung in Bezug auf ihren Beitrag zur Degradation untersucht. Die dafür notwendige beschleunigte Alterung erfolgte mittels Temperaturwechselbelastung zwischen -40 °C und +85 °C. Unterstützt durch die numerische Simulation konnte die Degradation der Rückseitenmetallisierung und Zellverschaltung im Detail charakterisiert und Lösungen zur Reduktion der Leistungsabnahme abgeleitet werden. Erstmals wurde dabei der Einfluss der AgAl-Legierung und des Druckkontaktwiderstandes auf den Serienwiderstand der Solarmodule untersucht.

In numerous Gram-negative and Gram-positive bacteria as well as in Archaea SL proteins form the outermost layer of the cell envelope. SL (glyco)monomers self-assemble with oblique (p2), tetragonal (p4), or hexagonal (p3, p6) symmetries [12]. SL subunits interact with each other and with the underlying cell surface by relatively weak non-covalent forces such as hydrogen-bonds, ionic bonds, salt-bridges or hydrophobic interactions. This makes them easy to isolate by applying chaotropic agents like urea and guanidine hydrochloride (GuHCl), chelating chemicals, or by changing the pH of the environment [10]. Upon dialysis in an ambient buffer monomers recrystallize into regular arrays that possess the forms of flat sheets, open ended cylinders, or spheres on solid substrates, at air-water intefaces and on lipid films, making them appealing for nanobiotechnological applications [3, 18]. The aim of this study was to investigate the structure, thermal stability, in vivo self-assembly process, recrystallization and metallization of three different recombinant SL proteins (SslA-eGFP, mSbsC-eGFP and S13240-eGFP) expressed in yeast S. cerevisiae BY4741 which could be further used in nanobiotechnological applications. In order to fulfill this aim, I investigated the in vivo expression of SL proteins (SslA, SbsC, S13240) tagged with eGFP (SL-eGFP) in the yeast S. cerevisiae BY4141. First, I characterized the heterologous expression of SL fusion constructs with growth and fluorescence measurements combined with Western blot analyses. Fluorescence microscopy investigations of overnight grown cultures showed that SslA-eGFP fusion protein was expressed as fluorescent patches, mSbsC-eGFP as tubular networks, and S13240-eGFP as hollow-like fibrillar network structures, while eGFP did not show any distinct structure Thermal stability of in vivo expressed SL-eGFP fusion proteins were investigated by fluorescence microscopy and immunodetection. In vivo self-assembly kinetics during mitosis and meiosis was the second main issue. In parallel, association of in vivo mSbsC-eGFP structures with the cellular components was of interest. A network of tubular structures in the cytosol of the transformed yeast cells that did not colocalize with microtubules or the actin cytoskeleton was observed. Time-resolved analysis of the formation of these structures during vegetative growth and sporulation was investigated by live fluorescence microscopy. While in meiosis ascospores seemed to receive assembled structures from the diploid cells, during mitosis surface layer structures were formed de novo in the buds. Surface layer assembly always started with the appearance of a dot-like structure in the cytoplasm, suggesting a single nucleation point. In order to get these in vivo SL assemblies stably outside the cells (in situ), cell distruption experiments were conducted. The tubular structures formed by the protein in vivo were retained upon bursting the cells by osmotic shock; however their average length was decreased. During dialysis, monomers obtained by treatment with chaotropic agents recrystallized again to form tube-like structures. This process was strictly dependent on calcium ions, with an optimal concentration of 10 mM. Further increase of the Ca2+ concentration resulted in multiple non-productive nucleation points. It was further shown that the lengths of the S-layer assemblies increased with time and could be controlled by pH. After 48 hours the average length at pH 9.0 was 4.13 µm compared to 2.69 µm at pH 5.5. Successful chemical deposition of platinum indicates the potential of recrystallized mSbsC-eGFP structures for nanobiotechnological applications. For example, such metalized protein nanotubes could be used in conductive nanocircuit technologies as nanowires.

Die Entwicklung der Mikroelektronik wird durch eine fortschreitende Miniaturisierung der Bauelemente geprägt. Infolge einer Reduzierung der Querschnittflächen von Leitbahnstrukturen erhöht sich die elektrische Leistungsdichte und das Metallisierungssystem bestimmt zunehmend die Übertragungsgeschwindigkeiten. Kupfer repräsentiert hierbei das verbreitetste Leitbahnmaterial und wird vorwiegend mittels elektrochemischer Abscheidung in vergrabene Damaszen-Strukturen eingebracht. Die vorliegende Dissertation beschreibt Möglichkeiten für eine Optimierung von Kupferleitbahnen für höchstintegrierte Schaltkreise. Von besonderem Interesse sind hierbei die Gefügequalität und der Reinheitsgrad. Es erfolgen umfangreiche werkstoffanalytische und elektrochemische Untersuchungen zur Charakterisierung von Depositionsmechanismen, des Einbaus von Fremdstoffen, des Mikrogefüges nach der Abscheidung und der Mikrogefügeumwandlung. In einem abschließenden Forschungsschwerpunkt werden Kupfer-Damaszen-Teststrukturen mit unterschiedlichen Gehalten nichtmetallischer Verunreinigungen hergestellt und entsprechenden Lebensdauerexperimenten unterzogen. Hierdurch gelingt eine Evaluierung des Einflusses jener Verunreinigungen auf die Elektromigrationsbeständigkeit von Kupferleitbahnen. Die Arbeit umfasst daher das gesamte Spektrum von der Grundlagenforschung bis zur Applikation von elektrochemisch abgeschiedenen Kupferdünnschichtmetallisierungen.

Carbon fibre reinforced composites are known for their high specific strength-to-weight ratio and are of great interest to the aerospace industry. Incorporating these materials into the fuselage, like in Boeing's 787 "Dreamliner", offers considerable weight reduction which increases flying efficiency, and reduces the cost of flying. In flight, aircraft are often subject to lightning strikes which, in the case of composites, can result in localized melting given the high resistive nature of the material. Aerospace carbon fibre composites often incorporate a metallic mesh or foil within the composite layers to dissipate the electrical charge through the large aircraft. The damage to the aircraft is minimized but not always eliminated. This research aims to elaborate a practical technique to deposit thin layers of conductive material on the surface of aerospace grade composites. Using Cold Gas Dynamic Spray (CGDS), such coatings could be used to repair damaged components. An experimental research approach was used to develop metallic coated composites. Using the CGDS equipment of Centerline (SST-P), specific parameters (such as gas temperature and stagnation pressure) were determined for each type of metallic coating (tin-based & copper-based). The use of bond coats was explored in order to attain the desired coatings. Once optimized, these coatings were evaluated with respect to their corrosive, adhesive, and electrical properties following industry standards.

Since its inception as the Tungsten Workshop in 1984, AMC has served as the leading conference for the interconnect and contact metallization communities, and has remained at the leading edge of the development of tungsten, aluminum, and copper/low-K interconnects. As the semiconductor industry evolves, exciting new challenges in metallization are emerging, particularly in the areas of contacts to advanced devices, local interconnect solutions for highly-scaled devices, advanced memory device metallization, and 3D/packaging technology. While the conference content has evolved, the unique workshop environment of AMC fosters open discussion to create opportunities for cross-pollination between academia and industry. Submissions are covering materials, process, integration and reliability challenges spanning a wide range of topics in metallization for interconnect/contact applications, especially in the areas of: - Contacts to advanced devices (FinFET, Nanowire, III/V, and 2D materials) - Highly-scaled local and global interconnects - Beyond Cu interconnect - Novel metallization schemes and advanced dielectrics - Interconnect and device reliability - Advanced memory (NAND/DRAM, 3D NAND, STT and RRAM) - 3D and packaging (monolithic 3D, TSV, EMI) - Novel and emerging interconnects Executive Committee: Sang Hoon Ahn (Samsung Electronics Co., Ltd.) Paul R. Besser (Lam Research) Robert S. Blewer (Blewer Scientific Consultants, LLC) Daniel Edelstein (IBM) John Ekerdt (The University of Texas at Austin) Greg Herdt (Micron) Chris Hobbs (Sematech) Francesca Iacopi (Griffith University) Chia-Hong Jan (Intel Corporation) Rajiv Joshi (IBM) Heinrich Koerner (Infineon Technologies) Mehul Naik (Applied Materials Inc.) Fabrice Nemouchi (CEA LETI MINATEC) Takayuki Ohba (Tokyo Institute of Technology) Noel Russell (TEL Technology Center, America) Stefan E. Schulz (Chemnitz University of Technology) Yosi Shacham-Diamand (Tel-Aviv University) Roey Shaviv (Applied Materials Inc.) Zsolt Tokei (IMEC)

This work examines the selective deposition of metallic and semiconductor materials onto DNA templates for the fabrication of nanodevices. DNA origami provides a simple and robust method for folding DNA into a variety of shapes and patterns and makes it possible to create the complex templates needed for nanodevices, such as nanoelectronic circuits, plasmonics, and nanosensors. Metallization of DNA origami templates is essential for the fabrication of such nanodevices. In addition, selective deposition of semiconductor materials onto the DNA template is of importance for making many nanodevices such as nanocircuits. Metallization of DNA origami presents several challenges beyond those associated with the metallization of other DNA templates such as λ-DNA. All of these challenges were addressed in this study. DNA origami templates were seeded with Ag and then plated with Au via electroless deposition. Selective continuous metal deposition was achieved, with an average metallized height as small as 32 nm. The structure of T-shaped DNA origami was also retained after metallization. Following the metallization of complete origami, site-specific metallization of branched DNA origami was also demonstrated. To achieve this, staple strands at select locations on origami were replaced with staple strands modified with binding sites at the end. These binding sites then attached to thiolated DNA coated Au nanoparticles through base pairing. The continuous Au nanowires formed at designated sites on DNA origami after Au plating had an average width of 33 nm, with the smallest ones ~20 nm wide. The continuity of nanowires was verified by conductivity tests- the only tests of this nature of which I am aware. Moreover, predesigned sites on "circuit-shaped" DNA origami were successfully metallized. The selective deposition of a variety of materials onto DNA templates for the formation of continuous DNA-templated nanowires was also demonstrated. Specifically, an electroless Ni plating solution was developed to enable the fabrication of uniform and continuous DNA-templated Ni nanowires. Tests showed that these DNA-templated Ni nanowires were conductive. Moreover, continuous DNA-templated Bi2Te3 and/or Te nanowires have been fabricated through galvanic displacement of DNA-templated Ni and Cu nanowires. Altogether, these results represent important progress toward the realization of DNA-templated nanofabrication.

Miniaturizing circuit size and increasing power density are the latest trends in modern power electronics development. In order to meet the requirements of higher frequency and higher power density in power electronics applications, planar interconnections are utilized to achieve a higher integration level. Power switching devices, passive power components, and EMI (Electromagnetic Interference) filters can all be integrated into planar power modules by using planar metallization, which is a technology involving electrical, mechanical, material, and thermal issues. By processing high dielectric materials, magnetic materials, or silicon chips using compatible manufacturing procedures, and by carefully designing structures and interconnections, we can realize the conventional discrete inductors, capacitors, and switch circuits with planar modules. Compared with conventional discrete components, the integrated planar modules have several advantages including lower profiles, better form factors, and less labor-intensive processing steps. In addition, planar interconnections reduce the wire bond inductive and resistive parasitic parameters, especially for high frequency applications. However, planar integration technology is a packaging approach with a large contact area between different materials. This may result in unknown failure mechanisms in power applications. Extensive research has already been done to study the performance, processing, and reliability of the planar interconnects in thin film structures. The thickness of the thin films used in integrated circuits (IC) or microelectronics applications ranges from the magnitude of nanometers to that of micrometers. In this work, we are interested in adopting planar interconnections to Integrated Power Electronics Modules (IPEM). In Integrated Power Electronics Modules (IPEMs), copper traces, especially bus traces, need to conduct current ranging from a few amps to tens of amps. One of the major differences between IC and IPEM is that the metal layer in IPEMs (normally >75µm) is much thicker than that of the thin films in IC (normally <1µm). The other major difference, which is also a feature of IPEM, is that the planar metallization is deposited on different brittle substrates. In active IPEM, switching devices are in a bare die form with no encapsulation. The copper deposition is on top of the silicon chips and the insulation polyimide layer. One of the key elements for passive IPEM and the EMI IPEM is the integrated inductor-capacitor (LC) module, which realizes equivalent inductors and capacitors in one single module. The deposition processes for silicon substrates and ceramic substrates are compatible and both the silicon and ceramic materials are brittle. Under high current and high temperature conditions, these copper depositions on brittle materials will cause detrimental failure spots. Over the last few years, the design, manufacture, optimization, and testing of the IPEMs has been developed and well documented. Up to this time , the research on failure mechanisms of conventional integrated power modules has led to the understanding of failures centered on wire bond or solder layer. However, investigation on the reliability and failure modes of IPEM is lacking, particularly that which uses metallization on brittle substrates for high current operations. In this study, we conduct experiments to measure and calculate the residual stresses induced during the process. We also, theoretically model and simulate the thermo-mechanical stresses caused by the mismatch of thermal expansion coefficients between different materials in the integrated power modules. In order to verify the simulation results, the integrated power modules are manufactured and subjected to the lifetime tests, in which both power cycling and temperature cycling tests are carried out. The failure mode analysis indicates that there are different failure modes for copper films under tensile or compressive stresses. The failure detection process verifies that delamination and silicon cracks happen to copper films due to compressive and tensile stresses respectively. This study confirms that the high stresses between the metallization and the silicon are the failure drivers in integrated power electronics modules.. We also discuss the driving forces behind several different failure modes. Further understanding of thesefailure mechanisms enables the failure modes to be engineered for safer electrical operation of IPEM modules and helps to enhance the reliability of system-level operation. It is also the basis to improve the design and to optimize the process parameters so that IPEM modules can have a high resistance to recognized failures. / Ph. D.

Silber-Glas-Dispersionen werden in der Herstellung von Solarzellen zur Ausbildung des Vorderseitenkontaktes großtechnisch seit vielen Jahren eingesetzt. Nichtsdestotrotz ist der Kontaktbildungsmechanismus bis jetzt nicht vollständig verstanden. In dieser Arbeit wurden Lösungs-, Transport- und Ausscheidungsprozesse von silberhaltigen Glasschmelzen in Silber-Glas-Dispersionen während der thermischen Kontaktierung von multikristallinem Silicium untersucht. Hierfür wurden systematisch Änderungen in der Zusammensetzung der Silber-Glas-Dispersionen sowie der hierfür verwendeten Gläser durch geführt, um Einzeleffekte zu separieren. Die Gläser wurden mit Silber zu Modelldispersionen verarbeitet und auf Siliciumwafer zu Herstellung von Solarzellen mittels Siebdruck abgeschieden und eingebrannt. Sowohl die Einzelkomponenten als auch die hergestellten Dispersionen wurden hinsichtlich ihrer thermisch aktivierten, linearen Schwindung untersucht. Die hergestellten Solarzellen wurden elektrisch sowie mittels FESEM in ihrer Mikrostruktur charakterisiert. Es konnten Zusammenhänge zwischen diesen Untersuchungen hinsichtlich der Silberlösung im Glas unter Oxidation, dem Silbertransport im Glas mittels Diffusion oder Konvektion sowie der Silberausscheidung unter Reduktion an der Waferoberfläche hergestellt und Einzeleffekte für den Silbertransport während des Einbrandes von Solarzellen identifiziert werden.

Les travaux présentés dans cette thèse se focalisent sur l'étude de l’effet de dégradations des composants de puissance, plus particulièrement au niveau de l’environnement proche des puces (métallisations, connexions, brasures puces/DCB), sur le comportement électrique et thermique des puces ainsi que de leur assemblage. Pour ce faire nous avons cherché à étudier la répartition des courants et des températures à la surface de la puce à l’aide d’un modèle électrothermique 2D distribué. Nous avons aussi évalué l’effet de la dégradation des brasures dans le volume de l’assemblage, à l’aide cette fois d’un modèle thermique relié à la constitution de l’assemblage. La première partie de cette thèse consiste à mettre en place un modèle électrothermique distribué de puce MOSFET, qui tient compte à la fois du caractère distribué de la dissipation de la puissance et du couplage électrothermique en régime transitoire. Ce modèle électrothermique s’appuie sur un modèle électrique aux variables d’états et un modèle thermique par éléments finis couplé au modèle électrique. Les modèles électriques et thermiques ont été développés respectivement sous Matlab et sous CAST3M, et le couplage des deux modèles a été fait sous Simulink. Dans une deuxième partie, pour la validation des résultats des températures et pour l’analyse de l’effet du vieillissement et des dégradations (sur la distribution et la dynamique de température de la surface supérieure de la puce), une méthodologie de mesure rapide de température et un banc expérimental pour thermographie infrarouge ont été mis en place. Les difficultés rencontrées lors des mesures thermiques IR sous variation rapide de la température nous ont poussé à envisager d’autres méthodes d’analyse thermique. Enfin, nous avons cherché à évaluer la réponse impulsionnelle du composant testé en estimant, par des simulations thermiques, la fonction de transfert dans le domaine fréquentiel à l’aide du logiciel COMSOL Multiphysics. Nous avons également étudié la pertinence de modèles RC équivalents (réseau RC de Cauer). Ces modèles ont ensuite été utilisés pour rendre compte de différents modes de dégradation notamment cette fois au niveau des couches de brasures entre puce et DCB et entre DCB et semelle. Mots clef : Modules de puissance à semi-conducteur, Vieillissement, Métallisation, Modélisation électrothermique, Court-circuit, Distribution de courant et de température, Problème inverse, Caméra IR, Réseaux de Cauer. / The work presented in this thesis focus on the study of the effect of degradation of power components, especially at the near environment of chips (metallization, connections, solder chips / DCB), on the electrical and thermal behavior of the chips and their assembly. As a consequence, we studied the distribution of currents and temperatures on the chip surface with a 2D electrothermal distributed model. We also evaluated the effect of solder degradation in the volume of the assembly. Firstly, we developed an electrothermal distributed model of the MOSFET chip, which takes into account both the distributed power dissipation and the electrothermal coupling transient. This electrothermal model is based on an electrical model of state variables and thermal finite element model coupled to the electric model. Electrical and thermal models were developed respectively in Matlab and CAST3M whereas the two models coupling was done in Simulink . In the second part, to validate the results of temperatures and to analyze the effect of ageing and degradation on the distribution and dynamics of temperature of the upper surface of the chip, methodology rapid temperature measurement and an experimental bench for infrared thermography were established. The difficulties encountered in IR thermal measurements with rapid temperature change led us to consider other thermal analysis methods. Eventually, we assessed the impulse response of the tested component by estimating with thermal simulations, the transfer function in the frequency domain using the COMSOL Multiphysics software. Moreover we evaluated the relevance of RC equivalent models (RC Cauer network). These models were then used to account for different modes of degradation this time especially on the solder layer between the chip and DCB and between the DCB and sole. Keywords: Power Modules semiconductor, Ageing, Metallization, electrothermal modeling, Short Circuit, Power and temperature distribution, inverse problem, IR Camera, Cauer networks.