A novel hybrid pulse-width modulation (PWM) update method is proposed to eliminate the effect of the one-step control time delay Td one without losing the full duty cycle range. Without the Td one to cause linear phase shifts that limit the control bandwidth and affect closed-loop stability, a very high quality digital current control can be achieved, such as a high closed current loop bandwidth, strong robustness against disturbances, ability to reach a very high fundamental frequency compared to switching frequency, etc. In a conventional digital control implementation, a sampling period (Tsamp) is allocated for the execution of samplings and computations, and the update of PWM outputs is delayed until the beginning of the following sampling period. This delayed PWM update method is the cause of the Td one. Instead of the delayed PWM update, if the PWM outputs are updated immediately after algorithm computations, then the effect of the Td one can be eliminated; however, the computation time delay Td comp from the current sampling instant through algorithm computations to the PWM update instant causes a reduced duty cycle range. Each of these two conventional PWM update methods has some shortcomings. A hybrid PWM update method is proposed to circumvent the aforementioned shortcomings and to incorporate only the advantages. The proposed method improves the performance by updating the PWM outputs multiple times during a Tsamp, whereas the PWM outputs are updated only one time during a Tsamp in the conventional methods. In spite of the simplicity of the proposed method, the performance improvements in stability, robustness and response characteristics are significant. On the other hand, the proposed method can be easily applied to many PWM based digital controls because of its simplicity. Additional to the hybrid PWM update method, a hybrid control method is proposed to optimize the sequence of control operations. It maximizes the current loops' robustness and minimizes the delay from the sampling of outer control loops' variables, such as voltage and speed, to the duty cycle update instant. The minimum delay enables the maximization of the outer control loops' bandwidth. Additionally, a corrective neutral offset voltage injection method is proposed to correct small PWM output deviations that may occur with the hybrid PWM update method. Utilizing a three-phase voltage source inverter with a permanent magnet synchronous machine as the platform, a deadbeat current control and a high speed ac drive experiments have been conducted to demonstrate the feasibility and validity. Notable results include a closed current loop response of one Tsamp with the deadbeat control and a 500 Hz current fundamental frequency with 1 kHz switching frequency in the high speed ac drive. / Ph. D. / A novel hybrid pulse-width modulation (PWM) update method is proposed to improve the performance of power electronics applications. PWM is a modulation technique that is typically used in power electronics to encode a control signal. A delayed PWM update method and an immediate PWM update method are two conventional PWM update methods, and each of these conventional methods has shortcomings. The delayed PWM update method, as the name implies, delays the update of PWM outputs until the beginning of next cycle. This delayed update ensures that PWM signals have the full range; however, it causes an update delay in control loops, which degrades the control loops’ response speed. On the other hand, the immediate PWM update method, as the name implies, the update of PWM outputs is executed as soon as the control signals are available to be updated. This immediate update eliminates the update delay, but it loses the full range of PWM signals. The hybrid PWM update method is proposed to combine the delayed and immediate PWM update methods, in which the combination can eliminate the update delay without the loss of the full signal range. The proposed method is quite simple; however, the performance improvements in stability, robustness, and response characteristics are significant. On the other hand, the proposed method can be easily applied to many PWM based digital controls because of its simplicity. The proposed method is implemented on a three-phase voltage source inverter with a permanent magnet synchronous machine, and the feasibility and validity are demonstrated with a deadbeat current control algorithm and a high speed ac drive experiment. In the experiments, a very high quality digital current control is achieved, such as a high closed current loop bandwidth, strong robustness against disturbances, ability to reach a very high fundamental frequency compared to switching frequency, etc.

In high-power electric drives, multilevel inverters are generally deployed to address issues such as electromagnetic interference, switch voltage stress and harmonic distortion. The switching frequency of the inverter is always kept low, of the order of 1KHz or even less to reduce switching losses and synchronous pulse width modulation (PWM) is used to avoid the problem of sub-harmonics and beat frequencies. This is particularly important if the switching frequency is very low. The synchronous PWM is getting popularity as its realization is very easy with digital controllers compared to analog controllers. Neutral-point-clamped (NPC) inverters, cascaded H-bridge, and flying-capacitor multilevel inverters are some of the popular schemes used for high-power applications. Hybrids of these multilevel inverters have also been proposed recently to take advantage of the basic configurations. Multilevel inverters can also be realized by feeding the induction motor from both ends (open-end winding) using conventional inverter structures. For controlling the output voltage of these inverters, various PWM techniques are used. Chapter-1 of this thesis provides an over view of the various multilevel inverter schemes preceded by a discussion on basic two-level VSI topology. The inverters used in motor drive applications have to be operated in over-modulation range in order to extract the maximum fundamental output voltage that is possible from the dc-link. Operation in this high modulation range is required to meet temporary overloads or to have maximum power operation in the high speed range (flux weakened region). This, however, introduces a substantial amount of low order harmonics in the Motor phase voltages. Due to these low-order harmonic frequencies, the dynamic performance of the drive is lost and the current control schemes are severely affected especially due to 5th and 7th harmonic components. Further, due to these low-order harmonics and non-linear PWM operation in over-modulation region, frequent over-current fault conditions occur and reliability of the drive is jeopardized. The twelve sided-polygonal space vector diagram (dodecagonal space vectors) can be used to overcome the problem of low order 5th and 7th harmonics and to give more range for linear modulation while keeping the switching frequency at a minimum compared to conventional hexagonal space vector based inverters. Thus, the dodecagonal space-vector switching can be viewed as an engineering compromise between low switching frequency and quality load current waveform. Most of the previous works of dodecagonal space-vector generation schemes are based on NPC inverters. However, sophisticated charge control schemes are required in NPC inverters to deal with the neutral-point voltage fluctuation and the neutral-point voltage shifting issues. The losses in the clamping diodes are another major concern. In the second chapter, a multilevel dodecagonal space-vector generation scheme based on flying capacitor topology, utilizing an open end winding induction motor is presented. The neutral point charge-balancing problem reported in the previous works is not present in this scheme, the clamping diodes are eliminated and the number of power supplies required has been reduced. The capacitors have inherent charge balancing capability, and the charge control is done once in every switching cycle, which gives tight voltage control for the capacitors. For the speed control of induction motors, the space-vector PWM scheme is more advantageous than the sine-triangle PWM as it gives a more linear range of operation and improved harmonic performance. One major disadvantage with the conventional space-vector PWM is that the trigonometric operations demand formidable computational efforts and look-up tables. Carrier based, common-mode injected PWM schemes have been proposed to simplify the PWM process. However, the freedom of selecting the PWM switching sequences is limited here. Another way of obtaining SVPWM is using the reference voltage samples and the nearest vector information to switch appropriate devices for proper time intervals, realizing the reference vector in an average sense. In-formation regarding the sector and nearest vectors can be easily obtained by comparing the instantaneous amplitudes of the reference voltages. This PWM approach is pro-posed for the speed control of the motor in this thesis. The trigonometric operations and the requirement of large look-up tables in the conventional SVPWM are avoided in this method. It has the additional advantage that the switching sequences can be decided at will, which is helpful in reducing further, the harmonic distortion in certain frequency ranges. In this way, this method tries to combine the advantages of vector based methods (conventional SVPWM) and scalar methods (carrier-based methods). The open-end winding schemes allowed the required phase voltage levels to be generated quite easily by feeding from both ends of the windings. Thus, most of the multilevel inverters based on dodecagonal space-vector structures relied on induction motors with open-end windings. The main disadvantage of open-end winding induction motor is that six wires are to be run from the inverter to the motor, which may be unacceptable in certain applications. Apart from the inconvenience of laying six wires, the voltage reflections in the wires can lead to over voltages at the motor terminals, causing insulation failures. Where as the topology presented in chapter-2 of this thesis uses open-end winding motor with flying-capacitor inverters for the generation of dodecagonal space-vectors, the topology presented in chapter-3 utilizes a cascade connection of flying-capacitors and floating H-bridge cells to generate the same set of voltage space-vectors, thus allowing any standard induction motor as the load. Of the methods used for the speed control of induction motors, namely sine-triangle PWM and space vector PWM, the latter that provides extra modulation range is naturally preferred. It is a well-understood fact that the way in which the PWM switching sequences are applied has a significant influence on the harmonic performance of the drive. However, this topic has not been addressed properly for dodecagonal voltage space-vector based multilevel inverter drives. In chapter-4 of the thesis, this aspect is taken into ac-count and the notion of “harmonic flux trajectories” and “stator flux ripple” are used to analyze the harmonic performance of the various PWM switching schemes. Although the PWM method used in this study is similar to that in chapter-2, the modification in the PWM switching sequence in the PWM algorithm yields significant improvements in harmonic performance. The proposed topologies and PWM schemes are extensively simulated and experimentally verified. The control scheme was implemented using a DSP processor running at a clock frequency 150MHz and a four-pole, 3.7kW, 50Hz, 415V three-phase induction motor was used as the load. Since the PWM ports are limited in a DSP, a field-programmable gate array (FPGA) was used to decode the PWM signals from the DSP to generate timing information required for PWM sequencing for all the power devices. The same FPGA was used to generate the dead-time signals for the power devices also.

In DC to AC power conversion, voltage source inverters (VSI) based current controllers are usually preferred for today’s high performance AC drive which requires excellent dynamic and steady state performances at different transient and load conditions, with the additional advantages like inherent short circuit and over current protection. Out of different types of current controllers, hysteresis controllers are widely used due to their simplicity and ability to meet the requirements for a high performance AC drives. But the conventional hysteresis controllers suffers from wide variation of PWM switching frequency, overshoot in current errors, sub-harmonic components in the current waveform and non-optimum switching at different operating point of the drive system. To mitigate these problems, particularly to control the switching frequency variation, which is the root cause of all other problems, several methodologies like ramp comparison based controller, predictive current controller, etc. were proposed in the literature. But amplitude and phase offset error in the ramp comparison based controllers and complexities involved in the predictive controllers have limited the use of these controllers. Moreover, these type of controllers, which uses three separate and independently controlled tolerance band (sinusoidal type or adaptive) to control the 3-phase currents, shows limited dynamic responses and they are not simple to implement. To tackle the problem of controlling 3-phase currents simultaneously, space vector based hysteresis current controller is very effective as it combines the current errors of all the three phases as a single entity called current error space vector. It has a single controller’s logic with a hysteresis boundary for controlling this current error space vector. Several papers on space vector based hysteresis controllers for 2-level inverter with constant switching frequency have been published, but the application of the constant switching frequency based hysteresis current controllers for multi¬level inverter fed drive system, has not been addressed properly. Use of multi-level inverter in modern high performance drive for medium and high voltage levels is more prominent because of multi-level’s inherent advantages like good power quality, good electromagnetic compatibility (EMC), better DC link voltage utilization, reduced device voltage rating, so on. Even though some of the earlier works describe three-level space vector based hysteresis current controller techniques, they are specific to the particular level of inverters and does not demonstrate constant switching frequency of operation. This thesis proposes a novel approach where nearly constant switching frequency based hysteresis controller can be implemented for any general n-level inverter and it is also independent of inverter topology. In this work, varying parabolic boundary is used as the hysteresis current error boundary for controlling the current in a multi-level space vector structure. The computation of the parabolic boundary is accomplished offline and all the necessary boundary parameters at different operating points are stored in the look-up tables. The varying parabolic boundary for the multi-level space vector structure depends on the sampled reference phase voltage values which are estimated from stator current error information and then using the equivalent circuit model of induction motors. Here, a mapping technique is adopted to bring down all the three phase references to the inner- most carrier region, which results in mapping any outer triangular structure where tip of the voltage space vector is located, to one of the sectors of the inner most hexagon of the multi-level space vector structure. In this way, the required mapped sector information is easily found out to fix the correct orientation of the parabolic boundary in the space vector plane. This mapping technique simplifies the controller’s logic similar to that of a 2-level inverter. For online identification of the inverter switching voltage vectors constructing the present outer triangle of the multi-level space vector structure, the proposed controller utilizes the sampled phase voltage references. This identification technique is novel and also generic for any n-level inverter structure. This controller is having all the advantages of a space vector based hysteresis current controller and that of a multi-level inverter apart from having a nearly constant switching frequency spectrum similar to that of a voltage controlled space vector PWM (VC-SVPWM). Using the proposed controller, simulation study of a five-level inverter fed induction motor (IM) drive scheme, was carried out using Matlab-Simulink. Simulation study showed that the switching frequency variations in a fundamental cycle and over the entire speed range of the linear modulation region, is similar to that of a VC-SVPWM based multi-level VSI. The proposed hysteresis controller is experimentally verified on a 7.5 kW IM vector control drive fed with a five-level VSI. The proposed current error space vector based hysteresis controller providing nearly constant switching frequency is implemented on a TI TMS320LF2812 DSP and Xilinx XC3S200FT256 FPGA based platform. The three-phase reference currents are generated depending on the frequency command and the controller is tested with the drive for the entire operating speed range of the machine in forward and reverse directions. Steady state and quick transient results of the proposed drive are presented in this thesis. This thesis also proposes another type of hysteresis controller, firstly for 2-level inverter and then for general n-level multi-level inverter, which eliminates the parabolic boundary and replaces it with a boundary which is computed online and does not use any look up table for boundary selection. The current error boundary for the proposed hysteresis controller is computed online in a very simple way, using the information of estimated fundamental stator voltages along α and β axes of space vector plane. The method adopted for the proposed controller to compute the boundary does not involve any complicated computations and it selects the optimal vector for switching when current error space vector crosses the boundary. This way adjacent voltage vector switching similar to VC-SVPWM can be ensured. For 2-level inverter, it precisely determines the sector, in which reference voltage vector is present. In multi-level inverter, this controller also finds out the mapped sector information using the same mapping techniques as explained in the first part of this thesis. In both 2-level and multi-level inverter, the proposed controller does not use any look up table for finding individual voltage vector switching times from the estimated voltage references. These switching times are used for the computation of hysteresis boundary for individual vectors. Thus the hysteresis boundary for individual vectors is exactly calculated and the boundary is similar to that of VC-SVPWM scheme for the respective levels of inverter. In the present scheme, the phase voltage harmonic spectrum is very close to that of a constant switching frequency VC-SVPWM inverter. In this thesis, at first, the proposed on line boundary computation scheme is implemented for a 2-level inverter based controller for the initial study, so that it can be executed as fast as 10 µs in a DSP platform, which is required for accurate current control. Then the same algorithm of 2-level inverter is extended for multi-level inverter with the additional logic for online identification of nearest switching voltage vectors (also used in the parabolic boundary case) for the present sampling interval. Previously mentioned mapping technique for multi-level inverter, is also implemented here to bring down the phase voltage references to the inner-most carrier region to realize the multi-level current control strategy equivalent to that of a 2-level inverter PWM current control. Simulation study to verify the steady state as well as transient performance of the proposed controller for both 2-level as well as five-level VSI fed IM drive is carried out using Simulink tool box of MATLAB Simulation Software. The proposed hysteresis controllers are experimentally verified on a 7.5 kW IM vector control drive fed with a two-level VSI and five-level VSI separately. The proposed current error space vector based hysteresis controller providing nearly constant switching frequency profile for phase voltage is implemented on the TI TMS320LF2812 DSP and Xilinx XC3S200FT256 FPGA based platform. The three-phase reference currents are generated depending on the frequency command and the proposed hysteresis controllers are tested with drive for the entire operating speed range of the machine in forward and reverse directions. Steady state and transient results of the proposed drive are also presented for different operating conditions, through the simulation study followed by experimental verifications. Even though the simulation and experimental verifications are done on a 5-level inverter to explain the proposed hysteresis controller, it can be easily implemented for any general n-level inverter, as described in this thesis.

Use of multilevel inverters are inevitable in medium and high voltage drives. This is due to the fact that the multilevel inverters can produce voltages in smaller steps which will reduce the harmonic content and result in more sinusoidal voltages and currents as compared to voltages and currents from two-level inverters. Due to the device limitations, use of two-level inverters is not possible in medium and high voltage drive applications. Though multiple devices can be connected both in series and parallel to achieve two-level operation, the output voltages still suffer from high harmonic content. Multilevel inverters have multiple DC voltage levels with switches that enable one of the voltage steps to be applied to the load. Due to decrease in step size during each switching instant, output voltages and currents of the multilevel inverters have considerably less harmonic content. As the number of levels increase, the switching step reduces thereby the harmonic content also reduces drastically. Due to their advantages, multilevel inverters have gained lot of acceptance in the industry even at lower voltages. The three main configurations that have gained popularity are the neutral point clamped converter, the flying capacitor converter and the cascaded H-bridge converter. Each converter has its own set of advantages and disadvantages. Based on the requirements of various applications, it is possible to fabricate hybrid multilevel topologies that are combinations of the three basic topologies. Researchers around the world have proposed several such converters for diverse applications so as to suit particular requirements like modularity, ease of control, improved reliability, fault tolerant capability etc. The present thesis explores multilevel converters with single DC link to be used for motor drive and grid connected applications. A novel five-level inverter topology formed by cascading a floating capacitor H-bridge module to a regular three-level flying capacitor inverter has been explored in chapter 2. The three-level flying capacitor inverter can generate pole voltages of 0, VDC /2 and VDC . By cascading it with another floating capacitor H-bridge of voltage magnitude VDC /4, pole voltages of 0, VDC /4, VDC/2, 3VDC /4 and VDC . Each of these pole voltage levels can have one or more switching combinations. However each switching combination has a unique effect on the state of the two capacitor voltages. By switching through redundant switching combinations for the same pole voltage, the two capacitors present in each phase can be balanced. The proposed topology also has an advantage that if one of the devices in the H-bridge fails, the topology can still be operated as a regular three-level flying capacitor inverter that can supply full load at rated power by bypassing the faulty H-bridge. This fault tolerant operation of the converter will enable it to be used in applications like traction and marine drives where high reliability is needed. The proposed converter needs a single DC link. All the required voltage levels can be generated from the single DC link. This enables back to back grid connected operation possible where multiple converters can interact with a single DC link. Various pole voltage switching combination and its effect on individual capacitor has been studied. A control algorithm to balance the capacitor voltages by switching through multiple redundancies for the same pole voltage has been developed. The proposed configuration has been implemented in hardware using IGBT H-bridge modules and the control circuitry is realized using DSP and FPGA. The performance of the drive is verified for various frequencies and modulation indices during steady state by running a three phase induction motor at no load. The stability of the drive during transients has been studied by accelerating the machine suddenly at no load and analyzing the performance of the drive. The capacitor voltages are made to deviate from their intended values and the capacitor balancing algorithm has been verified for its ability to bring the capacitor voltages back to their intended values. The experimental results have been presented and discussed in detail in the chapter 2. In the third chapter a common-mode voltage eliminated three-level inverter using a single DC link has been proposed. The power schematic is similar to the one presented in chapter 2. In this chapter the space vector polygon formed by the three phases of the proposed topology has been presented. The common-mode voltage generated by different pole voltage combinations for same space vector location and the redundant switching state combinations has been studied. The pole voltage combinations with zero common mode voltage have been studied. The switching state redundancies for the the pole voltage have been studied. The space vector polygon formed with the pole voltage combinations has been analyzed. A drive is made with the proposed common-mode voltage eliminated inverter. The performance of the drive is tested for various modulation indices and frequencies by running a three phase squirrel cage induction motor at no load. The transient performance is verified by accelerating the motor suddenly and checking the common-mode voltage along with the capacitor voltages. The results have been presented and discussed in detail in chapter 3. This converter has advantages like use of single DC supply, ability to operate as a regular three level converter in case of failure of one of the H-bridges. The work presented in fourth chapter proposes a novel three phase 17-level inverter configuration which utilizes a single DC supply. The rest of voltages are generated using three floating capacitor H-bridges. The redundant switching combinations for generating various pole voltages and their effect on the capacitors have been studied and suitable capacitor balancing algorithm has been developed. The proposed topology has been realized in hardware and the performance of the drive during steady state has been studied by running an induction motor at various modulation indices and frequencies. The transient response of the drive has been observed by accelerating the motor suddenly under no load. The results have been presented in detail in chapter four. This configuration also needs a single DC link. The advantages of this configuration is in case of failure of any devices in the H-bridge, the drive can be operated at reduced number of levels while supplying full load current. This feature helps the drive to be used in fault tolerant applications like marine and traction drives where reliability of the drive is of prime importance. All the topologies that have been presented in the previous chapters have mentioned about the usage of the proposed genre of topologies use single DC link and hence will enable back to back grid tied inverter connection. In the fifth chapter this has has been verified experimentally. The three phase squirrel cage induction motor is driven by using the seventeen-level inverter drive proposed in chapter four. A five-level active front-end is realized by the converter topology proposed in chapter two. The converter is run and the performance of the drive is studied at various modulation indices and speeds of the motor. Various aspects like re-generation operation, acceleration and other aspects of the drive have been studied experimentally and the results are presented in detail. For experimental setup, Semikron SKM75GB12T4 IGBT modules have been used to realize the power topology. These IGBTs are driven by M56972L drivers. The control circuit is realized using TMS320F2812 DSP along with Xilinx Spartan 3 FPGA (XC3S200) has been used. The voltages and currents are sensed using LEM LV-20P and LA 55-P hall effect based sensors.

For medium and high-voltage drive applications, multilevel inverters are very popular. It is due to their superior performance compared to 2-level inverters such as reduced harmonic content in the output voltage and current, lower common mode voltage and dv=dt, and lesser voltage stress on power switches. The popular circuit topologies for multilevel inverters are neutral point clamped, cascaded H-bridge and flying capacitor based circuits. There exist different combinations of these basic topologies to realize multilevel inverters with modularity, better fault tolerance, and reliability. Due to these advantages, multilevel converters are getting good acceptance from the industry, and researchers all over the world are continuously trying to improve the performance of these converters. To meet such demands, three multilevel inverter topologies are proposed in this thesis. These topologies can be used for high-power induction motor drives, and the concepts presented are also applicable for synchronous motor drives, grid-connected inverters, etc. To get nearly sinusoidal phase current waveforms, the switching frequency of the conventional inverter has to be increased. It will lead to higher switching losses and electromagnetic interference. The problem with lower switching frequency is the intro- duction of low order harmonics in phase currents and undesirable torque ripple in the motor. The 5th and 7th harmonics are dominant for hexagonal voltage space-vector based low frequency switching, and it is possible to eliminate these harmonics by dodecagonal switching. Further improvement in the waveform quality is possible by octadecagonal voltage space-vectors. In this case, the complete elimination of 11th and 13th harmonic is possible for the entire modulation range. The concepts of dodecagonal and octadecagonal voltage space-vectors are used in the proposed inverter topologies. The first topology proposed in this thesis consists of cascaded connection of two H-bridge cells. The two cells are fed from unequal DC voltage sources having a ratio of 1 : 0:366, and this inverter can produce six concentric dodecagonal voltage space- vectors. This ratio of voltages can be obtained easily from a combination of star-delta transformers, since 1 : 0:366 = ( p 3 + 1) : 1. The cascaded connection of two H-bridge cells can generate nine asymmetric pole voltage levels, and the combined three-phase inverter can produce 729 voltage space-vectors (9 9 9). From this large number of combinations, only certain voltage space-vectors are selected, which forms dodecagonal pattern. In the case of conventional multilevel inverters, the voltage space-vector diagram consists of equilateral triangles of equal size, but for the proposed inverter, the triangular regions are isosceles and are having different sizes. By properly placing the voltage space-vectors in a sampling period, it is possible to achieve lower switching frequency for the individual cells, with substantial improvement in the harmonic spectrum of the output voltage. During the experimental veri cation, the motor is operated at di erent speeds using open loop v=f control method. The samples taken are always synchronised with the start of the sector to get synchronised PWM. The number of samples per sector is decreased with increase in the fundamental frequency to limit the switching frequency. Even though many topologies are available in literature, the most preferred topology for drives application such as traction drives is the 3-level NPC structure. This implies that the industry is still looking for viable alternatives to construct multilevel inverter topologies based on available power circuits. The second work focuses on the development of a multilevel inverter for variable speed medium-voltage drive application with dodecagonal voltage space-vectors, using lesser number of switches and power sources compared to earlier implementations. It can generate three concentric 12-sided polygonal voltage space-vectors and it is based on commonly available 2-level and 3-level inverters. A simple PWM timing computation method based on the hexagonal space-vector PWM is developed. The sampled values of the three-phase reference voltages are initially converted to the timings of a two-level inverter. These timings are mapped to the dodecagonal timings using a change of basis transformation. The voltage space- vector diagram of the proposed drive consists of sixty isosceles triangular regions, and the dodecagonal timings calculated are converted to the timings of the inner triangles. A searching algorithm is used to identify the triangular region in which the reference vector is located. A front-end recti er that may be easily implemented using standard star-delta transformers is also developed, to provide near-unity power factor. To test the performance of the inverter drive, an open-loop v=f control is used on a three-phase induction motor under no-load condition. The harmonic spectra of the phase voltages were computed in order to analyse the harmonic distortion of the waveforms. The carrier frequency was kept around 1.2 KHz for the entire range of operation. If the switching frequency is decreased, the conventional hexagonal space-vector based switching introduce signifi cant 5th, 7th, 11th and 13th harmonics in the phase currents. Out of these dominant harmonics, the 5th and 7th harmonics can be completely suppressed using dodecagonal voltage space-vector based switching as observed in the first and second work. It is also possible to remove the 11th and the 13th harmonics by using voltage space-vectors with 18 sides. The last topology is based on multilevel octadecagonal (18-sided polygon) voltage space-vectors, and it has better harmonic performance than the previously mentioned topologies. Here, a multilevel inverter system capable of producing three octadecagonal voltage space-vectors is proposed for the fi rst time, along with a simple timing calculation method. The conventional three-level inverters are only required to construct the proposed drive. Four asymmetric power supply voltages with 0:3054Vdc, 0:3473Vdc, 0:2266Vdc and 0:1207Vdc are required for the operation of the drive, and it is the main drawback of the circuit. Generally front-end isolation transformer is essential for high-power drives and these asymmetric voltages can be easily obtained from the multiple windings of the isolation transformer. The total harmonic distortion of the phase current is improved due to the 18-sided voltage space-vector switching. The ratio of the radius of the largest polygon and its inscribing circle is cos10 = 0:985. This ratio in the case of hexagonal voltage space-vector modulation is cos30 = 0:866, which means that the range of the linear modulation for the proposed scheme is signifi cantly higher. The drive is designed for open-end winding induction motors and it has better fault tolerance. It any of the inverter fails, it can be easily bypassed and the drive will be still functional with reduced speed. Open loop v=f control and rotor flux oriented vector control schemes were used during the experimental verifi cation. TMS320F2812 DSP platform was used to execute the control code for the proposed drive schemes. For the entire range of operation, the carrier was synchronized with the fundamental. For the synchronization, the sampling period is varied dynamically so that the number of samples in a triangular region is fi xed, keeping the switching frequency around 1.2 KHz. The average execution time for the v=f code was found to be 20 S, where as for vector control it took nearly 100 S. The PWM terminals and I/O lines of the DSP is used to output the timings and the triangle number respectively. To convert the triangle number and the timings to IGBT gate drive logic, an FPGA (XC3S200) was used. A constant dead-time of 1.5 S is also implemented inside the FPGA. Opto-isolated gate drivers with desaturation protection (M57962L) were used to drive the IGBTs. Hall-effect sensors were used to measure the phase currents and DC bus voltages. An incremental shaft position encoder with 2500 pulse per revolution is also connected to the motor shaft, to measure the angular velocity. 1200 V, 75 A IGBT half-bridge module is used to realize the switches. The concepts were initially simulated and experimentally verifi ed using laboratory prototypes at low power. While these concepts maybe easily extended to higher power levels by using suitably rated devices, the control techniques presented shall still remain applicable.

For medium and high-voltage drive applications, multilevel inverters are very popular. It is due to their superior performance compared to 2-level inverters such as reduced harmonic content in the output voltage and current, lower common mode voltage and dv=dt, and lesser voltage stress on power switches. The popular circuit topologies for multilevel inverters are neutral point clamped, cascaded H-bridge and flying capacitor based circuits. There exist different combinations of these basic topologies to realize multilevel inverters with modularity, better fault tolerance, and reliability. Due to these advantages, multilevel converters are getting good acceptance from the industry, and researchers all over the world are continuously trying to improve the performance of these converters. To meet such demands, three multilevel inverter topologies are proposed in this thesis. These topologies can be used for high-power induction motor drives, and the concepts presented are also applicable for synchronous motor drives, grid-connected inverters, etc. To get nearly sinusoidal phase current waveforms, the switching frequency of the conventional inverter has to be increased. It will lead to higher switching losses and electromagnetic interference. The problem with lower switching frequency is the intro- duction of low order harmonics in phase currents and undesirable torque ripple in the motor. The 5th and 7th harmonics are dominant for hexagonal voltage space-vector based low frequency switching, and it is possible to eliminate these harmonics by dodecagonal switching. Further improvement in the waveform quality is possible by octadecagonal voltage space-vectors. In this case, the complete elimination of 11th and 13th harmonic is possible for the entire modulation range. The concepts of dodecagonal and octadecagonal voltage space-vectors are used in the proposed inverter topologies. The first topology proposed in this thesis consists of cascaded connection of two H-bridge cells. The two cells are fed from unequal DC voltage sources having a ratio of 1 : 0:366, and this inverter can produce six concentric dodecagonal voltage space- vectors. This ratio of voltages can be obtained easily from a combination of star-delta transformers, since 1 : 0:366 = ( p 3 + 1) : 1. The cascaded connection of two H-bridge cells can generate nine asymmetric pole voltage levels, and the combined three-phase inverter can produce 729 voltage space-vectors (9 9 9). From this large number of combinations, only certain voltage space-vectors are selected, which forms dodecagonal pattern. In the case of conventional multilevel inverters, the voltage space-vector diagram consists of equilateral triangles of equal size, but for the proposed inverter, the triangular regions are isosceles and are having different sizes. By properly placing the voltage space-vectors in a sampling period, it is possible to achieve lower switching frequency for the individual cells, with substantial improvement in the harmonic spectrum of the output voltage. During the experimental veri cation, the motor is operated at di erent speeds using open loop v=f control method. The samples taken are always synchronised with the start of the sector to get synchronised PWM. The number of samples per sector is decreased with increase in the fundamental frequency to limit the switching frequency. Even though many topologies are available in literature, the most preferred topology for drives application such as traction drives is the 3-level NPC structure. This implies that the industry is still looking for viable alternatives to construct multilevel inverter topologies based on available power circuits. The second work focuses on the development of a multilevel inverter for variable speed medium-voltage drive application with dodecagonal voltage space-vectors, using lesser number of switches and power sources compared to earlier implementations. It can generate three concentric 12-sided polygonal voltage space-vectors and it is based on commonly available 2-level and 3-level inverters. A simple PWM timing computation method based on the hexagonal space-vector PWM is developed. The sampled values of the three-phase reference voltages are initially converted to the timings of a two-level inverter. These timings are mapped to the dodecagonal timings using a change of basis transformation. The voltage space- vector diagram of the proposed drive consists of sixty isosceles triangular regions, and the dodecagonal timings calculated are converted to the timings of the inner triangles. A searching algorithm is used to identify the triangular region in which the reference vector is located. A front-end recti er that may be easily implemented using standard star-delta transformers is also developed, to provide near-unity power factor. To test the performance of the inverter drive, an open-loop v=f control is used on a three-phase induction motor under no-load condition. The harmonic spectra of the phase voltages were computed in order to analyse the harmonic distortion of the waveforms. The carrier frequency was kept around 1.2 KHz for the entire range of operation. If the switching frequency is decreased, the conventional hexagonal space-vector based switching introduce signifi cant 5th, 7th, 11th and 13th harmonics in the phase currents. Out of these dominant harmonics, the 5th and 7th harmonics can be completely suppressed using dodecagonal voltage space-vector based switching as observed in the first and second work. It is also possible to remove the 11th and the 13th harmonics by using voltage space-vectors with 18 sides. The last topology is based on multilevel octadecagonal (18-sided polygon) voltage space-vectors, and it has better harmonic performance than the previously mentioned topologies. Here, a multilevel inverter system capable of producing three octadecagonal voltage space-vectors is proposed for the fi rst time, along with a simple timing calculation method. The conventional three-level inverters are only required to construct the proposed drive. Four asymmetric power supply voltages with 0:3054Vdc, 0:3473Vdc, 0:2266Vdc and 0:1207Vdc are required for the operation of the drive, and it is the main drawback of the circuit. Generally front-end isolation transformer is essential for high-power drives and these asymmetric voltages can be easily obtained from the multiple windings of the isolation transformer. The total harmonic distortion of the phase current is improved due to the 18-sided voltage space-vector switching. The ratio of the radius of the largest polygon and its inscribing circle is cos10 = 0:985. This ratio in the case of hexagonal voltage space-vector modulation is cos30 = 0:866, which means that the range of the linear modulation for the proposed scheme is signifi cantly higher. The drive is designed for open-end winding induction motors and it has better fault tolerance. It any of the inverter fails, it can be easily bypassed and the drive will be still functional with reduced speed. Open loop v=f control and rotor flux oriented vector control schemes were used during the experimental verifi cation. TMS320F2812 DSP platform was used to execute the control code for the proposed drive schemes. For the entire range of operation, the carrier was synchronized with the fundamental. For the synchronization, the sampling period is varied dynamically so that the number of samples in a triangular region is fi xed, keeping the switching frequency around 1.2 KHz. The average execution time for the v=f code was found to be 20 S, where as for vector control it took nearly 100 S. The PWM terminals and I/O lines of the DSP is used to output the timings and the triangle number respectively. To convert the triangle number and the timings to IGBT gate drive logic, an FPGA (XC3S200) was used. A constant dead-time of 1.5 S is also implemented inside the FPGA. Opto-isolated gate drivers with desaturation protection (M57962L) were used to drive the IGBTs. Hall-effect sensors were used to measure the phase currents and DC bus voltages. An incremental shaft position encoder with 2500 pulse per revolution is also connected to the motor shaft, to measure the angular velocity. 1200 V, 75 A IGBT half-bridge module is used to realize the switches. The concepts were initially simulated and experimentally verifi ed using laboratory prototypes at low power. While these concepts maybe easily extended to higher power levels by using suitably rated devices, the control techniques presented shall still remain applicable.

Thesis (PhD (Electrical and Electronic Engineering))--University of Stellenbosch, 2011. / ENGLISH ABSTRACT: The focus of this thesis is on the optimal design, control and evaluation of 3-phase permanent magnet radial flux synchronous machines with non-overlapping, concentrated-coil, double layer stator windings for EV hub drive applications. A simple analytical method is developed that can be used as a first design tool. The method uses and predicts the MMF harmonic content for a certain pole-slot combination as well as the harmonic content for the air gap permeance function. These harmonics are then used to calculate the torque and torque ripple of machines with large stator slot openings and surface mounted permanent magnets. A different approach to calculate the iron, stator copper eddy current and magnet losses is presented. This method specifically looks at the machine during field weakening operation when the flux paths are changing in the machine. Flux density information throughout the machine is extracted from a series of static FE solutions, to calculate the losses and to combine this with an empirical formula. Some machine topology choices are compared for use as hub drives in small electric ve- hicles. The parameters that influence the machine design are discussed and evaluated after a multidimensional design optimization is done and an efficient control algorithm is imple- mented. The algorithm works through the entire operating speed range and make use of, automatically generated, 2D look up tables to determine the correct current reference. A stator lamination design is proposed, that combines the use of rectangular preformed coils and semi-closed stator slots. Two prototype machines, one with a good winding factor and the other with a low winding factor, are built and compared. The manufacturing and testing of the two prototype machines are described and shown in detail. / AFRIKAANSE OPSOMMING: Die fokus van hierdie tesis is op die optimale ontwerp, beheer en evaluasie van 3-fase per- manent magneet radiale vloed sinchroon masjiene met nie-oorvleuelende, gekonsentreerde, dubbel laag stator wikkelinge vir EV hub motor toepassings. ’n Eenvoudige analitiese metode is ontwikkel wat as ’n eerste ontwerp gereedskap stuk gebruik kan word. Die metode gebruik en voorspel die MMF se frekwensie inhoud vir ’n sekere pool-gleuf kombinasie sowel as die frekwensie inhoud vir die lug spleet permeansie funksie. Hierdie frekwensie inhoud word dan gebruik om die draaimoment en draaimoment riffel van masjiene met groot stator gleuf openinge en oppervlak magnete te voorspel. ’n Ander benadering om yster, stator koper werwel stroom en magneet verliese te bepaal word voorgestel. Hierdie metode kyk spesifiek na masjiene onder veld verswakking beheer wanneer die vloed paaie verander vanaf die normale. Die vloeddigtheid, regdeur die masjien, word verkry deur om van ’n reeks statiese eindige element oplossings gebruik te maak en dit te kombineer met ’n empiriese verliesberekening. Die parameters wat die masjienontwerp beïnvloed, word bespreek en geëvalueer na ’n mul- tidimensionele ontwerp optimering gedoen is en ’n effektiewe beheer algoritme geïmplimen- teer is. Die algoritme werk vir enige spoed en is gebaseer op die outomaties gegenereerde 2D opsoek tabelle wat die korrekte stroomverwysing gee. ’n Stator laminasie ontwerp word voorgestel wat die gebruik van vooraf vervaardigde spoele en gedeeltelik toe stator gleuwe moontlik maak. Twee prototipe masjiene, een met ’n goeie windingsfaktor en een met ’n swakker windingsfaktor is gebou en vergelyk. Die ver- vaardiging en toetsing van die twee prototipe masjiene word in detail beskryf en gewys.

Este trabalho apresenta uma alternativa ao controle vetorial de motores de indução, sem a utilização de sensores para realimentação da velocidade mecânica do motor. Ao longo do tempo, diversas técnicas de controle vetorial têm sido propostas na literatura. Dentre elas está a técnica de controle por orientação de campo (FOC), muito utilizada na indústria e presente também neste trabalho. A principal desvantagem do FOC é a sua grande sensibilidade às variações paramétricas da máquina, as quais podem invalidar o modelo e as ações de controle. Nesse sentido, uma estimativa correta dos parâmetros da máquina, torna-se fundamental para o acionamento. Este trabalho propõe o desenvolvimento e implementação de um estimador baseado em um sistema de inferência neuro-fuzzy adaptativo (ANFIS) para o controle de velocidade do motor de indução trifásico em um acionamento sem sensores. Pelo fato do acionamento em malha fechada admitir diversas velocidades de regime estacionário para o motor, uma nova metodologia de treinamento por partição de frequência é proposta. Ainda, faz-se a validação do sistema utilizando a orientação de campo magnético no referencial de campo de entreferro da máquina. Simulações para avaliação do desempenho do estimador mediante o acionamento vetorial do motor foram realizadas utilizando o programa Matlab/Simulink. Para a validação prática do modelo, uma bancada de testes foi implementada; o acionamento do motor foi realizado por um inversor de frequência do tipo fonte de tensão (VSI) e o controle vetorial, incluindo o estimador neuro-fuzzy, foi realizado pelo pacote de tempo real do programa Matlab/Simulink, juntamente com uma placa de aquisição de dados da National Instruments. / This work presents an alternative sensorless vector control of induction motors. Several techniques for induction motor control have been proposed in the literature. Among these is the field oriented control (FOC), strongly used in industries and also in this work. The main drawback of the FOC technique is its sensibility to deviations of the parameters of the machine, which can deteriorate the control actions. Therefore, an accurate determination of the machines parameters is mandatory to the drive system. This work proposes the development of an adaptive neuro-fuzzy inference system (ANFIS) estimator to control the angular speed of a three-phase induction motor in a sensorless drive. In a closed loop configuration, several speed commands can be imposed to the motor. Thus, a new frequency partition training of ANFIS is proposed. Moreover, the ANFIS speed estimator is validated in a magnetizing flux oriented control scheme. Simulations to evaluate the performance of the estimator considering the vector drive system were done by the Matlab/Simulink. To determine the benefits of the proposed model a practical system was implemented using a voltage source inverter (VSI) and the vector control including the ANFIS estimator, carried out by the Real Time Toolbox from Matlab/Simulink and a data acquisition card from National Instruments.

Este trabalho apresenta uma alternativa ao controle vetorial de motores de indução, sem a utilização de sensores para realimentação da velocidade mecânica do motor. Ao longo do tempo, diversas técnicas de controle vetorial têm sido propostas na literatura. Dentre elas está a técnica de controle por orientação de campo (FOC), muito utilizada na indústria e presente também neste trabalho. A principal desvantagem do FOC é a sua grande sensibilidade às variações paramétricas da máquina, as quais podem invalidar o modelo e as ações de controle. Nesse sentido, uma estimativa correta dos parâmetros da máquina, torna-se fundamental para o acionamento. Este trabalho propõe o desenvolvimento e implementação de um estimador baseado em um sistema de inferência neuro-fuzzy adaptativo (ANFIS) para o controle de velocidade do motor de indução trifásico em um acionamento sem sensores. Pelo fato do acionamento em malha fechada admitir diversas velocidades de regime estacionário para o motor, uma nova metodologia de treinamento por partição de frequência é proposta. Ainda, faz-se a validação do sistema utilizando a orientação de campo magnético no referencial de campo de entreferro da máquina. Simulações para avaliação do desempenho do estimador mediante o acionamento vetorial do motor foram realizadas utilizando o programa Matlab/Simulink. Para a validação prática do modelo, uma bancada de testes foi implementada; o acionamento do motor foi realizado por um inversor de frequência do tipo fonte de tensão (VSI) e o controle vetorial, incluindo o estimador neuro-fuzzy, foi realizado pelo pacote de tempo real do programa Matlab/Simulink, juntamente com uma placa de aquisição de dados da National Instruments. / This work presents an alternative sensorless vector control of induction motors. Several techniques for induction motor control have been proposed in the literature. Among these is the field oriented control (FOC), strongly used in industries and also in this work. The main drawback of the FOC technique is its sensibility to deviations of the parameters of the machine, which can deteriorate the control actions. Therefore, an accurate determination of the machines parameters is mandatory to the drive system. This work proposes the development of an adaptive neuro-fuzzy inference system (ANFIS) estimator to control the angular speed of a three-phase induction motor in a sensorless drive. In a closed loop configuration, several speed commands can be imposed to the motor. Thus, a new frequency partition training of ANFIS is proposed. Moreover, the ANFIS speed estimator is validated in a magnetizing flux oriented control scheme. Simulations to evaluate the performance of the estimator considering the vector drive system were done by the Matlab/Simulink. To determine the benefits of the proposed model a practical system was implemented using a voltage source inverter (VSI) and the vector control including the ANFIS estimator, carried out by the Real Time Toolbox from Matlab/Simulink and a data acquisition card from National Instruments.

La thèse étudie tout d’abord la relation entre les harmoniques à fentes du rotor (RSHs) et la vitesse du rotor instantanée. Pour suivre directement l'RSH, les exigences du système sont pleinement prises en compte.Dans un deuxième temps, les travaux de thèse ont permis de développer un système sans capteur en fonction de boucle à verrouillage de phase (PLL): La largeur de bande centrale est réglée en ligne sur la base des valeurs de référence, des fréquences d'alimentation et de glissement prévues au convertisseur PWM, la PLL est réglée pour suivre le rotor de la machine à RSH sans la nécessité de toute injection de signal à haute fréquence, ni en rotation, ni de pulsation. Ce système d'estimation de vitesse, qui est approprié pour le contrôleur scalaire, avait été intégré avec le lecteur scalaire, conduisant à un simple calcul peu exigeant, à faible coût de l’entraînement de la machine à induction sans capteur à faible coût. Les résultats expérimentaux montrent que le système est en mesure de suivre la vitesse de la machine dans une plage de vitesse très étendue.Enfin, un système sans capteur amélioré basé sur l'analyse de composant mineur (MCA) neurones est décrit. Selon la théorie de Pisarenko, il a été vérifié que le MC qui se trouve dans le sous-espace de bruit est orthogonale au sous-espace de signal, par conséquent, les fré-quences de signal contenues dans l'entrée peuvent être calculées à partir d'un polynôme formé par la MC. Classiquement, ce qui nécessitera la décomposition propre encombrants, néan-moins, la méthode de neurones proposée dans cette thèse peut récupérer le MC de façon ré-cursive avec moins de calculs et des performances améliorées d'erreur (la solution est sur un total de moins sens carré). En outre, l'estimateur de vitesse est appliquée à l'entraînement scalaire avec vérification expérimentale, l'ensemble du système se comporte bien, et la méthode MCA renforcée par réseaux neuronaux a fourni un bon potentiel dans l'application des harmoniques récupérer. / The thesis first studies the relation between the rotor slot harmonics (RSHs) and the instan-taneous rotor speed. To directly track the RSH, the requirements of the system are fully ad-dressed.Second, the thesis presents a sensorless scheme based on phase-locked loop (PLL): The centre bandwidth is tuned on-line on the basis of the reference values of the supply and slip frequencies provided to the PWM converter, the PLL is tuned to track the machine rotor slot-ting harmonic without the need of any high frequency signal injection, neither rotating nor pulsating. This speed estimation scheme, which is suitable for the scalar controller, had been integrated with the scalar drive, leading to a simple, computationally not demanding, low cost sensorless IM drives. The experiment results show that the system is able to track the machine speed in a very wide speed range.Finally, an improved sensorless scheme based on minor component analysis (MCA) neu-rons is described. According to the Pisarenko’s theory, it has been verified that the MC which lies in the noise subspace is orthogonal to the signal subspace, thus, the signal frequencies contained in the input can be computed from a polynomial formed by the MC. Conventional-ly, this will require the bulky eigen-decomposition, nevertheless, the neural method proposed in this thesis can retrieve the MC recursively with less computation and improved error per-formance (the solution is of total least square meaning). Moreover, the speed estimator is ap-plied to the scalar drive with experimental verification, the overall system is well behaved, and the MCA method enhanced by neural networks has provided a good potential in the ap-plication of harmonics retrieve.