We present observational and numerical evidence supporting the theory of impulsive heating of the solar corona. We have run numerical simulations solving the hydrodynamic equations for plasma confined to a magnetic flux tube, for the two distinct cases of steady and impulsive heating. We find that steady heating cannot explain the observed amount of low-temperature plasma in active regions on the sun. The results for impulsive heating closely match those of the observations. The ratio of heating time to cooling time predominantly determines the observed temperature distribution of the plasma. We have also identified an observational bias in calculating intensities of spectral lines in previous studies, which causes an under-estimation of low-temperature plasma. We predict Doppler shifts in the observed line emission that are in agreement with observations, and which may serve as a diagnostic of the strength of heating. We conclude that impulsive heating of active region coronal loops is more likely than steady heating.

Recent advances in voltage-controlled oscillator (VCO) design and the trend of CMOS processing indicate that the oscillator control is quickly becoming one of the forefront problems in high-frequency and low-phase-noise phase-locked loop (PLL) design. This control centric study explores the limitations and challenges in high-performance analog charge-pump PLLs when they are extended to multiple gigahertz applications. Several problems with performance enhancement and precise oscillator control using analog circuits in low-voltage submicron CMOS processes, coupled with the fact that analog (or semi-digital) oscillators having various advantages over their digitally controlled counterparts, prompted the proposal of the digitally-controlled phase-locked loop. This research, then, investigates a class of otherwise analog PLLs that use a digital control path for driving a current-controlled oscillator. For this purpose, a novel method for control digitization is described where trains of pulses code the phase/frequency comparison information rather than the duration of the pulses: Pulse-Stream Coded Phase-Locked Loop (psc-PLL). This work addresses issues significant to the design of future PLLs through a comparative study of the proposed digital control path topology and improved cutting-edge charge-pump PLLs.

High-speed serial data links are quickly gaining in popularity and replacing the conventional parallel data links in recent years when the data rate of communication exceeds one gigabits per second. Compared with parallel data links, serial data links are able to achieve higher data rate and longer transfer distance. This dissertation is focused on the design of CMOS integrated phase-locked loops (PLLs) and relevant building blocks used in multi-gigabits serial data link transceivers. Firstly, binary phase-locked loops (BPLLs, i.e., PLLs based on binary phase detectors) are modeled and analyzed. The steady-state behavior of BPLLs is derived with combined discrete-time and continuous-time analysis. The jitter performance characteristics of BPLLs are analyzed. Secondly, a 10 Gbps clock and data recovery (CDR) chip for SONET OC- 192, the mainstream standard for optical serial data links, is presented. The CDR is based on a novel referenceless dual-loop half-rate architecture. It includes a binary phase-locked loop based on a quad-level phase detector and a linear frequency-locked loop based on a linear frequency detector. The proposed architecture enables the CDR to achieve large locking range and small jitter generation at the same time. The prototype is implemented in 0.18 μm CMOS technology and consumes 250 mW under 1.8 V supply. The jitter generation is 0.5 ps-rms and 4.8 ps-pp. The jitter peaking and jitter tolerance performance exceeds the specifications defined by SONET OC-192 standard. Thirdly, a fully-differential divide-by-eight injection-locked frequency divider with low power dissipation is presented. The frequency divider consists of a four-stage ring of CML (current mode logic) latches. It has a maximum operating frequency of 18 GHz. The ratio of locking range over center frequency is up to 50%. The prototype chip is implemented in 0.18 μm CMOS technology and consumes 3.6 mW under 1.8 V supply. Lastly, the design and optimization techniques of fully differential charge pumps are discussed. Techniques are proposed to minimize the nonidealities associated with a fully differential charge pump, including differential mismatch, output current variation, low-speed glitches and high-speed glitches. The performance improvement brought by the techniques is verified with simulations of schematics designed in 0.35 μm CMOS technology.

In this dissertation, the development of the first 60 GHz-standard compatible fully integrated 4-channel phase-locked loop (PLL) frequency synthesizer has been presented. The frequency synthesizer features third-order single loop architecture with completely integrated passive loop filter that does not require any additional external passive component. Two possible realizations of fully integrated clock and data recovery (CDR) circuits suitable for 60 GHz-standard compliant base band signal processing have been presented for the first time as well. The two CDRs have been optimized for either high data rate (3.456 Gb/s) or very low power consumption (5 mW) and they both work with a single 1 V supply. The frequency synthesizer is intended to generate a variable LO frequency in a fixed-IF heterodyne transceiver architecture. In such configuration the channel selection is implemented by changing the LO frequency by the required frequency step. This method avoids quadrature 50 GHz up/down-conversion thereby lowering the LO mixer design complexity and simplifying the LO distribution network. The measurement results show the PLL locking correctly on each of the four channels while consuming 60 mW from a 1 V power supply. The worst case phase noise is measured to be -80.1 dBc/Hz at 1 MHz offset from the highest frequency carrier (56.16 GHz). The output spectrum shows a reference spur attenuation of -32 dBc. The high data rate CDR features a maximum operating data rate in excess of 3.456 Gb/s while consuming 30 mW of power. The low power CDR consumes only 5 mW and operates at a maximum data rate of 1.728 Gb/s. Over a 1.5 m 60 GHz wireless link, both CDRs allow 95% reduction of the pulse shaping generated input peak-to-peak jitter from 450 ps down to 50 ps.

Instruction scheduling and Software pipelining are important compilation techniques which reorder instructions in a program to exploit instruction level parallelism. They are essential for enhancing instruction level parallelism in architectures such as very Long Instruction Word and tiled processors. This thesis addresses two important problems in the context of these instruction reordering techniques. The first problem is for general purpose applications and architectures, while the second is for media and graphics applications for tiled and multi-core architectures. The first problem deals with software pipelining which is an instruction scheduling technique that overlaps instructions from multiple iterations. Software pipelining increases the register pressure and hence it may be required to introduce spill instructions. In this thesis, we model the problem of register allocation with optimal spill code generation and scheduling in software pipelined loops as a 0-1 integer linear program. By minimizing the amount of spill code produced, the formulation ensures that the initiation interval (II) between successive iterations of the loop is not increased unnecessarily. Experimental results show that our formulation performs better than the existing heuristics by preventing an increase in the II and also generating less spill code on average among loops extracted from Perfect Club and SPEC benchmarks. The second major contribution of the thesis deals with the code size aware scheduling of stream programs. Large scale synchronous dataflow graphs (SDF’s) and StreamIt have emerged as powerful programming models for high performance streaming applications. In these models, a program is represented as a dataflow graph where each node represents an autonomous filter and the edges represent the channels through which the nodes communicate. In constructing static schedules for programs in these models, it is important to optimize the execution time buffer requirements of the data channel and the space required to store the encoded schedule. Earlier approaches have either given priority to one of the requirements or proposed ad-hoc methods for generating schedules with good trade-offs. In this thesis, we propose a genetic algorithm framework based on non-dominated sorting for generating serial schedules which have good trade-off between code size and buffer requirement. We extend the framework to generate software pipelined schedules for tiled architectures. From our experiments, we observe that the genetic algorithm framework generates schedules with good trade-off and performs better than the earlier approaches.

This study examines the impact of academic and personal life on graduate student persistence and transformation. Of particular interest are the relationships, emotions, and life management skills required throughout the graduate experience and how socialization, emotional intelligence, and advising aid students through their academic program. With an average of seven to eight years required to complete a doctoral program, life happens. Students enter and leave relationships, children are born, family members have emergencies, health issues arise, and emotional growth takes place. Therefore, students transform not only academically, but in many ways. These are intertwined as evidenced by the data-derived system representation. The importance of understanding the interconnected links in graduate experience spans academic, social, economic, and societal spheres. Each year hundreds of thousands of students enter graduate school. However, for doctoral students, there is an enormous gap between acceptance and completion. After seven years, approximately 50 percent complete their program and after ten years the rate climbs to only 57 percent (Council of Graduate Schools, 2010). This study offers a systemic representation and a four-stage model of graduate student development, incorporating student-identified factors: Faculty Impact, Life Management, Relationships, Playing the Game, Growth/Transformation, Emotions, and Reward/Purpose. Stage I: Orientation and Socialization Stage II: Adjustment and Transition Stage III: Navigation and Transformation Stage IV: Completion and Advancement The results, presented as a systems-based model, along with analysis, may be used to support faculty, advisors, and administrators in creating better advising, orientation, evaluation, and support systems. Departmental policies may be improved to identify at-risk students, provide mentorship opportunities, or obtain continual feedback to understand the underlying factors that may stop students from progressing. This research might also help identify students during the application/admission process. The methodological framework used to create the system produced in this study is Interactive Qualitative Analysis (Northcutt & McCoy, 2004), a methodology that provides the quantitative rigor of algorithmically generated data analysis, combined with the qualitative descriptiveness of interviews, in order to provide insights into the drivers of graduate school persistence. This methodology uses a systematic, protocol-driven research procedure to construct a unified, descriptive diagram to illustrate the phenomenon. / text

Oxides form a class of material which covers almost all the spectra of functionalities : dielectricity, semiconductivity, metallicity superconductivity, non-linear optics, acoustics, piezoelectricity, ferroelectricity, ferromagnetism...In this thesis, crystalline oxides have beenintegrated on the workhorse of the semiconductor industry, the silicon, by Molecular Beam Epitaxy (MBE).The first great interest of the epitaxial growth of crystalline oxides on silicon consists in the application of "high-k" dielectric for future sub-22nm CMOS technology. Gadoliniumoxide was explored in detail as a promising candidate of the alternative of SiO2. The pseudomorphic epitaxial growth of Gd2O3 on Si (111) was realized by identifying the optimal growth conditions. The Gd2O3 films show good dielectric properties and particularly an EOTof 0.73nm with a leakage current consistent with the requirements of ITRS for the sub-22nmnodes. In addition, the dielectric behavior of Gd2O3 thin films was further improved by performing PDA treatments. The second research interest on crystalline oxide/Si platform results from its potential application for the "More than Moore" and "Heterogeneous integration" technologies. TheSrTiO3/Si (001) was intensively studied as a paradigm of the integration of oxides on semiconductors. The crystallinity, interface and surface qualities and relaxation process of the STO films on silicon grown at the optimal conditions were investigated and analyzed. Several optimized growth processes were carried out and compared. Finally a "substrate-like" STO thin film was obtained on the silicon substrate with good crystallinity and atomic flat surface. Based on the Gd2O3/Si and SrTiO3/Si templates, diverse functionalities were integrated on the silicon substrate, such as ferro-(piezo-)electricity (BaTiO3, PZT and PMN-PT),ferromagnetism (LSMO) and optoelectronics (Ge). These functional materials epitaxially grown on Si can be widely used for storage memories, lasers and solar cells, etc.

Our society is increasingly demanding situation-aware smarter software (SASS) systems, whose goals change over time and depend on context situations. A system with such properties must sense their dynamic environment and respond to changes quickly, accurately, and reliably, that is, to be context-aware and self-adaptive. The problem addressed in this dissertation is the dynamic management of context information, with the goal of improving the relevance of SASS systems' context-aware capabilities with respect to changes in their requirements and execution environment. Therefore, this dissertation focuses on the investigation of dynamic context management and self-adaptivity to: (i) improve context-awareness and exploit context information to enhance quality of user experience in SASS systems, and (ii) improve the dynamic capabilities of self-adaptivity in SASS systems. Context-awareness and self-adaptivity pose signi cant challenges for the engineering of SASS systems. Regarding context-awareness, the rst challenge addressed in this dissertation is the impossibility of fully specifying environmental entities and the corresponding monitoring requirements at design-time. The second challenge arises from the continuous evolution of monitoring requirements due to changes in the system caused by self-adaptation. As a result, context monitoring strategies must be modeled and managed in such a way that they support the addition and deletion of context types and monitoring conditions at runtime. For this, the user must be integrated into the dynamic context management process. Concerning self-adaptivity, the third challenge is to control the dynamicity of adaptation goals, adaptation mechanisms, and monitoring infrastructures, and the way they a ect each other in the adaptation process. This is to preserve the eff ectiveness of context monitoring requirements and thus self-adaptation. The fourth challenge, related also to self-adaptivity,concerns the assessment of adaptation mechanisms at runtime to prevent undesirable system states as a result of self-adaptation. Given these challenges, to improve context-awareness we made three contributions. First, we proposed the personal context sphere concept to empower users to control the life cycle of personal context information in user-centric SASS systems. Second, we proposed the SmarterContext ontology to model context information and its monitoring requirements supporting changes in these models at runtime. Third, we proposed an effi cient context processing engine to discover implicit contextual facts from context information speci fied in changing context models. To improve self-adaptivity we made three contributions. First, we proposed a framework for the identi cation of adaptation properties and goals, which is useful to evaluate self-adaptivity and to derive monitoring requirements mapped to adaptation goals. Second, we proposed a reference model for designing highly dynamic self-adaptive systems, for which the continuous pertinence between monitoring mechanisms and both changing system goals and context situations is a major concern. Third, we proposed a model with explicit validation and veri cation (V&V) tasks for self-adaptive software, where dynamic context monitoring plays a major role. The seventh contribution of this dissertation, the implementation of Smarter-Context infrastructure, addresses both context-awareness and self-adaptivity. To evaluate our contributions, qualitatively and quantitatively, we conducted several comprehensive literature reviews, a case study on user-centric situation-aware online shopping, and a case study on dynamic governance of service-oriented applications. / Graduate

Translinear circuits are circuits in which the exponential relationship between the output current and input voltage of a circuit element is exploited to realize various algebraic or differential equations. This thesis is concerned with a subclass of translinear circuits, in which the basic translinear element, called a multiple-input translinear element (MITE), has an output current that is exponentially related to a weighted sum of its input voltages. MITE networks can be used for the implementation of the same class of functions as traditional translinear circuits. The implementation of algebraic or (algebraic) differential equations using MITEs can be reduced to the implementation of the product-of-power-law (POPL) relationships, in which an output is given by the product of inputs raised to different powers. Hence, the synthesis of POPL relationships, and their optimization with respect to the relevant cost functions, is very important in the theory of MITE networks. In this thesis, different constraints on the topology of POPL networks that result in desirable system behavior are explored and different methods of synthesis, subject to these constraints, are developed. The constraints are usually conditions on certain matrices of the network, which characterize the weights in the relevant MITEs. Some of these constraints are related to the uniqueness of the operating point of the network and the stability of the network. Conditions that satisfy these constraints are developed in this work. The cost functions to be minimized are the number of MITEs and the number of input gates in each MITE. A complete solution to POPL network synthesis is presented here that minimizes the number of MITEs first and then minimizes the number of input gates to each MITE. A procedure for synthesizing POPL relationships optimally when the number of gates is minimal, i.e., 2, has also been developed here for the single--output case. A MITE structure that produces the maximum number of functions with minimal reconfigurability is developed for use in MITE field--programmable analog arrays. The extension of these constraints to the synthesis of linear filters is also explored, the constraint here being that the filter network should have a unique operating point in the presence of nonidealities. Synthesis examples presented here include nonlinear functions like the arctangent and the gaussian function which find application in analog implementations of particle filters. Synthesis of dynamical systems is presented here using the examples of a Lorenz system and a sinusoidal oscillator. The procedures developed here provide a structured way to automate the synthesis of nonlinear algebraic functions and differential equations using MITEs.

Software components expose Application Programming Interfaces (APIs) as a means to access their functionality, and facilitate reuse. Developers use APIs supplied by programming languages to access the core data structures and algorithms that are part of the language framework. They use the APIs of third-party libraries for specialized tasks. Thus, APIs play a central role in mediating a developer's interaction with software, and the interaction between different software components. However, APIs are often large, complex and hard to navigate. They may have hundreds of classes and methods, with incomplete or obsolete documentation. They may encapsulate concurrency behaviour that the developer is unaware of. Finding the right functionality in a large API, using APIs correctly, and maintaining software that uses a constantly evolving API are challenges that every developer runs into. In this thesis, we design automated techniques to address two problems pertaining to APIs (1) Concurrency analysis of APIs, and (2) API mining. Speci cally, we consider the concurrency analysis of asynchronous APIs, and mining of math APIs to infer the functional behaviour of API methods. The problem of concurrency bugs such as race conditions and deadlocks has been well studied for multi-threaded programs. However, developers have been eschewing a pure multi-threaded programming model in favour of asynchronous programming models supported by asynchronous APIs. Asynchronous programs and multi-threaded programs have different semantics, due to which existing techniques to analyze the latter cannot detect bugs present in programs that use asynchronous APIs. This thesis addresses the problem of concurrency analysis of programs that use asynchronous APIs in an end-to-end fashion. We give operational semantics for important classes of asynchronous and event-driven systems. The semantics are designed by carefully studying real software and serve to clarify subtleties in scheduling. We use the semantics to inform the design of novel algorithms to find races and deadlocks. We implement the algorithms in tools, and show their effectiveness by finding serious bugs in popular open-source software. To begin with, we consider APIs for asynchronous event-driven systems supporting pro-grammatic event loops. Here, event handlers can spin event loops programmatically in addition to the runtime's default event loop. This concurrency idiom is supported by important classes of APIs including GUI, web browser, and OS APIs. Programs that use these APIs are prone to interference between a handler that is spinning an event loop and another handler that runs inside the loop. We present the first happens-before based race detection technique for such programs. Next, we consider the asynchronous programming model of modern languages like C]. In spite of providing primitives for the disciplined use of asynchrony, C] programs can deadlock because of incorrect use of blocking APIs along with non-blocking (asynchronous) APIs. We present the rst deadlock detection technique for asynchronous C] programs. We formulate necessary conditions for deadlock using a novel program representation that represents procedures and continuations, control ow between them and the threads on which they may be scheduled. We design a static analysis to construct the pro-gram representation and use it to identify deadlocks. Our ideas have resulted in research tools with practical impact. Sparse Racer, our tool to detect races, found 13 previously unknown use-after-free bugs in KDE Linux applications. Dead Wait, our deadlock detector, found 43 previously unknown deadlocks in asynchronous C] libraries. Developers have fixed 43 of these races and deadlocks, indicating that our techniques are useful in practice to detect bugs that developers consider worth fixing. Using large APIs effectively entails finding the right functionality and calling the methods that implement it correctly, possibly composing many API elements. Automatically infer-ring the information required to do this is a challenge that has attracted the attention of the research community. In response, the community has introduced many techniques to mine APIs and produce information ranging from usage examples and patterns, to protocols governing the API method calling sequences. We show how to mine unit tests to match API methods to their functional behaviour, for the specific but important class of math APIs. Math APIs are at the heart of many application domains ranging from machine learning to scientific computations, and are supplied by many competing libraries. In contrast to obtaining usage examples or identifying correct call sequences, the challenge in this domain is to infer API methods required to perform a particular mathematical computation, and to compose them correctly. We let developers specify mathematical computations naturally, as a math expression in the notation of interpreted languages (such as Matlab). Our unit test mining technique maps subexpressions to math API methods such that the method's functional behaviour matches the subexpression's executable semantics, as defined by the interpreter. We apply our technique, called MathFinder, to math API discovery and migration, and validate it in a user study. Developers who used MathFinder nished their programming tasks twice as fast as their counterparts who used the usual techniques like web and code search, and IDE code completion. We also demonstrate the use of MathFinder to assist in the migration of Weka, a popular machine learning library, to a different linear algebra library.