Rašto darbe nagrinėjama laiko ir erdvės kaita socialiniame, filosofiniame, psichologiniame kontekste bei žmogaus patyrimas juose. Aptariamos žmogaus juslės, jų įtaka žmogaus asmenybės formavimuisi, gebėjimui pažinti aplinkinį pasaulį bei poveikis individo emocinei būsenai. Darbo tikslas - atrasti galimą prisiminimų ryšį tarp žmonių, kurie užaugo skirtingose aplinkose, ir tai panaudoti, kaip dirgiklį sukeliant atsakomąją reakciją. / The paper analyses time and space turnover in a social, philosophical, psychological contexts, also including human experience in these surroundings. The paper discuss about human’s power of sensitivity, it’s influence to evolution of human identity. Furthermore, the paper represents human’s ability to discover environment using his senses and reveals these senses has an effect on human’s emotional condition. The aim of the paper is to reveal probable memory relationship between people, who grow up in different environment, using their individual memories as stimulus to get responsive reaction.

Darbą sudaro teorinė ir praktinė dalys. Teorinėje dalyje nagrinėjama prisiminimų reikšmė žmogui ir atminties savoka. Analizuojama žmogaus atminties ir prisiminimų reikšmė filosofijoje ir šiuolaikiniuose moksliniuose ir menotyriniuose kontekstuose. Nagrinėjamas prisiminimų vaizdavimas fotografijoje bei dailėje. Analizuojami ir lyginami šiuolaikiniai lietuvių menininkai, kurie savo fotografijuose, remiasi prisiminimų tematika (Aleksandras Ostašenkovas, Alvydas Lukys, Regina Šulskytė, Ugnius Gelguda). Praktinėje darbo dalyje pateikiamas fotografijų triptikas pavadinimu „Mano vaikystės tvenkinys“. Šiuose fotografijose siekiama perteikti asmeninius prisiminimus iš vaikystės. Fotografijų pagalba norima pavaizduoti asmeninį prisiminimą - savitą kelionę į praeitį, atsigręžimą į vaikystėje patirtus asmeninius išgyvenimus ir atsiminimus. Konkreti vieta (šiuo atvėju tvenkinys) - tai prisiminimus kelianti nostalgiška erdvė, kurioje būnant atminties verpiatuose iškyla ir ryškūs ir migloti vaikystės prisiminimai. / The work consist of theory analysis and visual practical parts. The theoretical part deals with humans memories and the concept of memory. There are analyzed the human memory and the meaning of memories in ancient antiquity and in contemporary scientific and philosophical context. Also, the memory representations in art and cinema. There are analyzed and compared contemporary Lithuanian artists, whose photographies are based on the topic of memory (Aleksandras Ostasenkovas, Alvydas Lukys, Regina Sulskyte, Ugnius Gelguda). The visual practical part are the series of photographies called “My childhood pond”. These photographies presents the personal memories from the childhood. Also, the visual part represents the unique journey to the past by thoughts and shows the personal experiences from the childhood. The specific location (in this case the pond) is giving rise to nostalgic mood, there being restore sometimes bright, sometimes blur memories.

The primary aim of this dissertation is to address an important issue of individual susceptibility to false memories. Specifically, what is the role inhibitory control (IC) in children’s and adult’s propensity to producing false memories? Inhibitory control within the context of the current study is defined on the basis of performance on selective attention tasks. Inhibitory control is discussed within this dissertation as it is reflected in two selective attention tasks, Stroop and Negative Priming. While the false memory effect, as reflected in the Deese/Roediger and McDermott paradigm (Roediger & McDermott, 1995), is one of the most widely studied memory phenomenon, the current study is important as it provides some insights into the relation between attention and memory. An interesting finding in the DRM false memory effect is that participants often report having a clear false memory of having seen or heard the non-presented critical lure item (CL item). Such memory illusions have been informative on how memory works. The current study adds to this body of research by providing converging evidence of how individual differences in the sensitivity to the false memory effect may occur, and how this sensitivity may reflect the same IC mechanisms involved in selective attention tasks. The basic notion examined within this dissertation is that when recognition memory is tested in the DRM paradigm, individuals have to select information that was studied and simultaneously inhibit highly activated yet non-presented information in memory, in order to correctly reject the CL item. If the notion that individual differences in sensitivity to the false memory effect is indeed related to a basic IC mechanism, then a relationship should be found between measures of IC in selective attention tasks and rates of false memories in the DRM test. The current study incorporates three experiments. Experiments 1 and 2 are broken down into parts ‘a’ and ‘b’, with each part varying in respect to the IC measure. In part a, participants were assigned to an inhibitory control group (IC group) on the basis of Stroop interference. In part b, participants are assigned to IC groups on the basis of a combined measure of inhibitory control that is, Stroop and Negative Priming. The third experiment assigned participants on the basis of a combined measure of IC, and then considered the relation between the duration of IC over a number of DRM word-lists presented simultaneously prior to the recognition test. Experiment 3 also compared the robust effect of IC on the propensity to produce false memories across all three experiments. The results of this study can be summarized as follows. In each experiment there was clear evidence of a relation between IC estimates and proportion of false memories. As predicted, individuals assigned to a Less IC group produced a higher proportion of false memories than those assigned to the More IC group. Inhibitory control differences did not modulate differences in correct or incorrect recognition in general (hits and false alarms to unrelated distractors). This second finding is important because it suggests a specific effect of IC in false memories, rather than a general breakdown in memory processes. The IC effect in false memories occurred in children (8-year olds and 10-year olds) as well as adults. Furthermore, the IC effect appeared to be additive with age; i.e., all groups produced a similar pattern across all three experiments. Last, the combined estimate of IC was found to be a more sensitive measure of false memories than a single index of IC; however, this was found in relation to adults but not for children. A number of additional manipulations and measures of interest were also included. Experiment 2 found clear evidence of an effect of IC on remember responses, not only were Less IC individuals more likely to produce false alarms to critical lure items, they were also more likely to distinctly respond they “remembered” the CL item as opposed to only “knowing” the CL had been presented. Examination of reaction times (RTs) to false alarms as a function of IC group found the Less IC group were faster to make false alarm responses to CL items, whereas the More IC group were slower to make false responses CL items. As predicted the relation between IC and the false memory effect was modulated by the random versus blocked presentation manipulation in Experiment 3. Specifically, decreased rates of false memories were found in the random presentation format compared to the blocked format. Interestingly however, a small effect of IC group in false memories was found even in the random condition. From this study it can be concluded that individual susceptibility to the false memory effect is in part modulated by inhibitory control. Individuals who demonstrate less effective IC show a greater propensity to false memories than those who demonstrate more effective IC. The IC effect of false memories was found to be robust, with converging evidence found across all three experiments. In relation to the development of inhibitory control, consistent with the research of Pritchard and Neumann (2004, 2009), and Lechuga and colleagues (2006), the results of this study suggest IC is fully developed in young children. However, their ability to accurately encode, retain and retrieve information would appear to develop at a different rate than IC. Specifically, it may be that while younger children are able to utilize IC in memory processes, they have yet to fully develop a richly interconnected semantic network. On the other hand, older children and adults would appear to have a more fully developed semantic network. This series of experiments presents a novel demonstration of the relation between inhibitory control and false memories. As such, this study has the potential to provide new insight into a cognitive mechanism that may be responsible for both developmental trends and for individual differences in the regulation of false memories. Moreover, if the mechanism responsible for mediating false memories is causally linked to performance on selective attention tasks in the systematic way that is proposed, it may be possible in the future to utilize IC measures to assist in identifying individuals who have an exaggerated propensity to form false memories, as well as those more prone to resist them.

No description available.

Thesis (M.S.)--California Polytechnic State University, 2008. / Major professor: Fei Wang, Ph.D. "Presented to the faculty of California Polytechnic State University, San Luis Obispo." "In partial fulfillment of the requirements for the degree [of] Master of Science in Electrical Engineering." "May 2008." Includes bibliographical references (leaves 53-56). Also available online. Also available on microfiche ( sheet).

Thesis (Ph.D.)--Hong Kong University of Science and Technology, 2005. / Includes bibliographical references. Also available in electronic version.

<p>I represented a person’s stories and memories of childhood through the material called glass, and found a method to approach personal stories.</p><p>To do this, the medium to express my conception that is express of the personal experience and extreme situation on glass was based. The most significant point of study was realizing the nature of emotions and meanings within a person’s life. As well as special instruments and to analyze whether it is an appropriate expression.</p><p>Accordingly with this, I collected individual stories from Zili and tried to comprehensively understand the cause behind. For that I approached different cases of psychology theory to compare. After I analyzed the colour and object that relate to memories or the person. Expression of artefact I created from foundational theory through my perspective. I represented in magnification of memories as an expression on glass artefacts for respect of peoples diversity life.</p><p>This led me to make more concrete context in practical work and theoretical tool as well.</p>

Η πρόοδος της τεχνολογίας CMOS δίνει τη δυνατότητα σχεδιασμού φθηνών, πολυπύρηνων, κοινής μνήμης, ενσωματωμένων επεξεργαστών. Ωστόσο, η υποστήριξη της συνάφειας της κρυφής μνήμης με κάποια μέθοδο που παρουσιάζει καλή κλιμάκωση απαιτεί σημαντική προσπάθεια. Τα πρωτόκολλα υποκλοπής παρέχουν μία λύση εύκολη στο σχεδιασμό, όμως είναι απαιτητικά σε εύρος ζώνης και κατανάλωση. Επιπλέον, η κλιμάκωσή τους είναι περιορισμένη όταν χρησιμοποιούνται σε αρτηρίες. Τα πρωτόκολλα που κάνουν χρήση ευρετηρίου, ειδικά τα κατανεμημένα, επιφέρουν μικρότερη επιβάρυνση στο δίκτυο. Απαιτούν όμως ελεγκτές ευρετηρίων οι οποίοι είναι δύσκολοι στο σχεδιασμό και καταναλώνουν πολύτιμη μνήμη, επιφάνεια και κατανάλωση εντός του ολοκληρωμένου, κάνοντάς τη λύση αυτή ακατάλληλη για ενσωματωμένα πολυπύρηνα συστήματα. Στην εργασία αυτή, παρουσιάζουμε ένα μηχανισμό διατήρησης της συνάφειας ο οποίος παρουσιάζει καλή κλιμάκωση, και βασίζεται σε απλά πρωτόκολλα υποκλοπής, πάνω όμως σε ένα ιεραρχικό δίκτυο σημείο προς σημείο. Για να μειωθούν δραματικά τα μηνύματα που στέλνονται με ευρεία εκπομπή, προτείνουμε τα Χρονολογικά Φίλτρα, μια λύση βασισμένη στα φίλτρα Bloom. Σε αντίθεση με προηγούμενες προσεγγίσεις, τα Χρονολογικά Φίλτρα (Temporal Filters - TF) είναι εφοδιασμένα με ένα μοναδικό χαρακτηριστικό: την ικανότητα να σβήνουν τα περιεχόμενά τους σε συγχρονισμό - αλλά χωρίς να επικοινωνούν - με τις κρυφές μνήμες. Τα Χρονολογικά Φίλτρα και οι κρυφές μνήμες σβήνουν τα περιεχόμενά τους βασισμένα στις ενέργειες που γίνονται για τη διατήρηση της συνάφειας, παρέχοντας ασφαλές φιλτράρισμα ορισμένων μηνυμάτων του πρωτοκόλλου συνάφειας. Με τον τρόπο αυτό, ξεπερνάμε το πρόβλημα της αφαίρεσης στοιχείων των φίλτρων Bloom, χωρίς τη χρήση επιπλέον μετρητών, μηνυμάτων ή σημάτων, όπως έχουν προταθεί σε προηγούμενες εργασίες. Όλα τα παραπάνω γίνονται χωρίς καμία τροποποίηση των πρωτοκόλλων συνάφειας της κρυφής μνήμης. Ως αποτέλεσμα, η λύση που προτείνεται στην εργασία αυτή, χρησιμοποιεί μικρές δομές που μπορούν να ενσωματωθούν εύκολα στους μεταγωγείς του μέσου διασύνδεσης. Για την αποτίμηση των μηχανισμών που προτείνουμε, χρησιμοποιήθηκε το περιβάλλον προσομοίωσης GEMS - για να μοντελοποιηθούν πολυπύρηνοι επεξεργαστές εντός ολοκληρωμένου με 8 και 16 πυρήνες, με ιδιωτικές κρυφές μνήμες πρώτου και δευτέρου επιπέδου - και η σουίτα μετροπρογραμμάτων SPLASH-2. Τα Χρονολογικά Φίλτρα αποδείχτηκαν ικανά να μειώσουν έως και κατά 74.7\% (κατά μέσο όρο) τα μηνύματα στο μέσο διασύνδεσης. Επιπλέον, τα Χρονολογικά Φίλτρα προσφέρουν τη δυνατότητα μείωσης της στατικής κατανάλωσης, καθώς χρησιμοποιείται η τεχνική Decay στις κρυφές μνήμες. / Advances in CMOS technology are enabling the design of inexpensive, multicore, shared-memory, embedded processors. However, supporting cache coherence in a scalable fashion in these architectures requires considerable effort. Snoop protocols provide an easy-to-design solution but they are greedy bandwidth and power consumers. In addition, their scalability is limited over a broadcast bus. Scalable directory protocols, especially distributed ones, remedy the bandwidth overhead but require hard-to-design directory controllers that consume precious on-chip storage, area, and power, rendering the solution unattractive for embedded multicores. In this work we advocate a scalable coherence solution based on simple broadcast snooping protocols but over a scalable hierarchical point-to-point network. To dramatically cut down on broadcasts we propose Temporal Filtering, a solution based on Bloom filters - a storage-efficient memory structure. In contrast to previous approaches, Temporal Filters (TFs) are equipped with a unique characteristic: the ability to self-clean their contents in concert - but without communicating - with caches. Both TFs and caches decay their contents based on coherence activity, guaranteeing the correctness of coherence filtering. In this way, we overcome the problem of entry removal in the Bloom filters without the need of extra counters, messages, or even extra signals as in previous work and, more importantly, without requiring changes in the underlying cache snoop protocols. As a result, our solution utilizes frugal single-bit structures that can be easily integrated into network switches. For our evaluation we use GEMS to model a 8- and 16-core CMP with private L1/L2 caches of various sizes, and the SPLASH-2 suite. TFs are proven able to reduce the 74.7\% (arithmetic average) of the network messages. In addition, TFs offer also leakage saving opportunities since cache decay is also applied in private caches.

Στην παρούσα διπλωματική εργασία, γίνεται η περιγραφή των χαρακτηριστικών των VLIW επεξεργαστών, συγκριτικά με άλλους επεξεργαστές, και στη συνέχεια αναλύεται ο τρόπος με τον οποίο υλοποιήθηκε ένα σύστημα, βασισμένο στη VLIW αρχιτεκτονική. Επιπλέον, παρουσιάζονται τα χαρακτηριστικά των Scratch-pad μνημών, συγκρίνοντάς τα με αυτά των Cache, ενώ υλοποιούνται Scratch-pad μνήμες, στις οποίες θα γίνεται η αποθήκευση των εντολών και των δεδομένων προγραμμάτων που θα εκτελεί ο επεξεργαστής VLIW. Τέλος, αναπτύχθηκε μια εφαρμογή επεξεργασίας εικόνας, με σκοπό να γίνει ο έλεγχος της συμπεριφοράς του συστήματος. / This project describes the characteristics of VLIW processors, compared to other types of processors, and analyses the way in which a system, based on the VLIW architecture, was created. In addition, Scratch-pad memories are compared to Cache memories and added to the system, in order to store the instructions and data of programs being executed by the VLIW processor. Finally, an image processing algorithm was developed with a view to simulate the system's behavior.

Le but de cette thèse était de caractériser et d’aider au développement des premières mémoires résistives verticales (VRRAM) fabriquées au LETI. Parmi les mémoires émergentes, les mémoires résistives (ReRAM) semblent prometteuses en termes de miniaturisation, de vitesse de commutation, de coût et de simplicité d’intégration. Comme pour les mémoires FLASH, qui ont déjà atteint leur limite physique en terme de miniaturisation, les mémoires résistives ont déjà été étudiées dans une géométrie verticale pour proposer des solutions qui maximisent la densité. Au début de ce travail on a étudié des échantillons 1R pour avoir une compréhension générale du fonctionnement et faire un balayage des matériaux et des épaisseurs. Une fois identifiées les configurations optimales, les mémoires ont été intégrées dans des structures 1T-1R pour pouvoir les étudier d’une manière plus industrielle. Les mémoires 1R ont été intégrées dans des structures MESA et celles 1T-1R ont été intégrées dans des structures MESA et VIA. Dans les deux cas le point mémoire se trouve dans les flancs de la structure ; il était particulièrement compliqué de déposer l’électrode supérieure. Les dispositifs ont été caractérisés électriquement afin d’obtenir les informations suivantes : résistance initiale, tension de formation, set et reset, temps de commutation, états de haute et basse résistivité, endurance et temps de rétention. Ces informations ont permis d’évaluer les VRRAM comme un possible candidat de mémoire non-volatile. Les dispositifs ont démontré une endurance de 107 cycles pour un courant de SET de 300µA, plus de 105s de temps de rétention pour un courant de SET de 100µA à 200 C et un temps de commutation de 20ns. Le courant de SET a été réduit jusqu’à 7µA, les mémoires montrant alors une capacité de commutation. Pour des courants si faibles les tests de data rétention ont démontré que le filament conducteur (CF) n’est pas stable. Les résultats expérimentaux étaient en accord avec ceux obtenus sur une technologie planaire en démontrant que la géométrie verticale n’a pas d’effet majeur sur le fonctionnement des mémoires. Ensuite des mémoires à 2 niveaux ont été fabriquées. Ces dispositifs étaient importants pour faire des tests qui donnaient des informations utiles pour une future intégration à haute densité. Les structures à 2 niveaux ont été comparées en termes de tensions de commutation et de résistance pour vérifier la reproductibilité de la technologie sur les flancs de la structure verticale. Des tests de « disturb » ont été également effectués pour vérifier que le cyclage sur un niveau n’influence pas le niveau non sélectionné. Une autre partie de la thèse était dédiée à l’étude physique du comportement du CF pendant le cyclage. Cette étude a montré qu’il y a une corrélation parmi les résistances pendant le cyclage. Pour expliquer ce phénomène des modèles analytique et physique ont été développés. Les deux modèles sont basés sur l’hypothèse que pendant le cyclage il y a un paramètre qui dépend des valeurs aux cycles précédents. Pour le modèle analytique le paramètre était la résistance même, alors que pour le modèle physique le paramètre était le gap du CF (LGAP). Les deux modèles montrent un bon accord avec les données expérimentales en indiquant que la morphologie du CF à un cycle donné dépend de la morphologie des cycles précédents. Une autre partie du travail était dédiée à l’étude pour les applications haute densité : en partant des résultats électriques sur les dispositifs à 2 niveaux et en supposant avoir un sélecteur intégré, on a calculé la taille maximum des matrices qu’on peut obtenir en fonction des différents paramètres d’intégration. Enfin on a travaillé sur les applications neuromorphiques où un pilier de VRRAM a été proposé comme émulateur de synapse. Les VRRAM peuvent émuler les synapses de 2 manières, soit en utilisant la probabilité intrinsèque des ReRAM ou en programmant chaque cellule du pilier avec un circuit extérieur. / The scope of the thesis was to characterize and help further development of the first LETI-fabricated vertical resistive RAM (VRRAM). Among emerging memories Resistive RAMs (ReRAM) seems promising in terms of scalability, switching speed, fabrication costs and ease of production. As in the case of FLASH devices, which are attaining their physical limits in terms of scalability, resistive memories are already being studied in vertical geometry in order to propose solutions that maximize memory density. This work proceeded as follows: at first 1 Resistor (1R) devices were characterized to gain a general understanding of the memory cells functioning and to perform the first screening in terms of stack composition and thicknesses. Once the best configurations were identified 1 Transistor- 1 Resistor (1T-1R) devices were integrated in order to assess memory performances in an industrial-like fashion. 1R devices were integrated in a MESA structure while 1T-1R devices were integrated in both MESA and VIA architectures. In both architectures the memory cell is found on the sidewall of the structure; particularly challenging was the deposition of the top electrode. Devices were electrically characterized to extract the following information: initial resistance, forming, set and reset voltages, switching times, high and low resistance states (HRS and LRS) resistances, endurance characteristics and data retention times. This set of measurements allowed to extensively study the capability of VRRAM as a non-volatile memory candidate. It was shown that HfO2-based VRRAM have 107 endurance capability for a set current (ISET) of 300 [µA], more than 105 [s] data retention for a SET current of 100 [µA] at 200 [˚C] backing temperature and down to 20 [ns] switching time. ISET was also reduced down to 7 [µA] and memory cell showed switching capability although the conductive filament (CF) resulted unstable after data retention tests. Experimental results obtained were in accordance with previous studies conducted on planar devices showing that vertical geometry did not have a significant effect on memory behavior. Finally 2-level memory devices were fabricated. These samples were really useful to perform important tests for future high density integration: the 2 level devices were compared in terms of switching voltages and resistances to verify the reproducibility of the integration along the sidewall of the structure. Disturb tests were carried out to be sure that write/erase operations on one level did not influence the state of the un-selected level. Another part of the thesis was dedicated to the physical investigation of the conducting filament behavior during cycling. This study showed that a correlation exists among resistances while cycling. In order to explain these measurements both analytical and physical models were proposed. Both rely on the assumption that there is a parameter during cycling that is related to its previous values; in the case of the analytical model this parameter is simply the resistance while in the physical model the parameter is the CF gap (LGAP). Both models show good fit with experimental data suggesting therefore that at any given cycle the morphology of the conductive filament is dependent on the morphology during the previous cycles. Another part of the thesis was also dedicated to a study on high density applications:starting from the electrical results obtained on 2-level VRRAM and supposing to work with an integrated selector the maximum array size attainable was calculated as a function of various parameters such as the node half pitch, the plane thicknesses and the number of integrated levels. Finally neuromorphic applications were investigated and a VRRAM pillar was proposed as a synapse emulator. VRRAMs can act as synapses in two ways: using the intrinsic probability of the ReRAM technology or programming each VRRAM cell in the pillar with a probability given from an external circuit.