There is an increased interest in the Conductive Bridge Random Access Memory (CBRAM) and Resistive Random Access Memory (RRAM) because of their excellent scaling potential, low power consumption, high switching speed, good retention and endurance properties. Although, various mechanisms have been proposed to explain the switching behavior in CBRAM devices, i.e. metal ion migration and subsequent formation and rupture of conductive filament, formation of conductive path via oxygen ion transport etc, there are still many aspects of these mechanisms that are little understood or are being disputed. This work probes the details of the switching mechanisms on a new level and asks questions like: 1) How is the formation of nanofilament affected by various degrees of Cu diffusion stopping power of the inert electrode? To answer this question, resistive switches with very thin Cu layers covering the Pt electrode were fabricated and analyzed. 2) How does a limited source of active ions impact the formation and rupture of nanofilaments? To answer this question, new samples with limited Cu supply were fabricated and analyzed. 3) What is the mechanism of nanofilament formation in Pt/TaOx/Pt resistive switches where the active copper electrode is removed and replaced by inert Pt electrode. 4) What are the most suitable conditions (material structure of the device and operation conditions) to set and reset multi nanofilaments? This work summarizes the current status of analysis of the data obtained while attempting to explain interesting phenomena like volatile switching and multiple filament formation experienced by modifying the switch structures. / Master of Science

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Dans la prochaine ère de l'informatique distribuée, les ordinateurs inspirés par le cerveau qui effectuent des opérations localement plutôt que dans des serveurs distants seraient un avantage majeur en réduisant les coûts énergétiques et réduisant l'impact environnemental. Une nouvelle génération de nanodispositifs de mémoire non-volatile est un candidat de premier plan pour réaliser cette vision neuromorphique. À l'aide de travaux théoriques et expérimentaux, nous avons exploré les problèmes critiques qui se posent lors de la réalisation physique des architectures de réseaux de neurones artificiels modernes (ANN) en utilisant des dispositifs de mémoire émergents (nanodispositifs « memristifs »). Dans notre travail expérimental, nos dispositifs organiques (polymeriques) se sont adaptés avec succès et automatiquement en tant que portes logiques reconfigurables en coopérant avec un neurone digital et programmable (FGPA). Dans nos travaux théoriques, nous aussi avons considéré les multicouches memristives ANNs. Nous avons développé et simulé des variantes de projection aléatoire (un système NoProp) et de rétropropagation (un système perceptron multicouche) qui utilisent deux crossbars. Ces systèmes d'apprentissage locaux ont montré des dépendances critiques sur les contraintes physiques des nanodispositifs. Enfin, nous avons examiné comment les conceptions ANNs “feed-forward” peuvent être modi-fiées pour exploiter les effets temporels. Nous avons amélioré la bio-inspiration et la performance du système NoProp, par exemple, avec des effets de plasticité dans la première couche. Ces effets ont été obtenus en utilisant un nanodispositif à ionisation d'argent avec un comportement de transition de plasticité intrinsèque. / In the next era of distributed computing, brain-based computers that perform operations locally rather than in remote servers would be a major benefit in reducing global energy costs. A new generation of emerging nonvolatile memory devices is a leading candidate for achieving this neuromorphic vision. Using theoretical and experimental work, we have explored critical issues that arise when physically realizing modern artificial neural network (ANN) architectures using emerging memory devices (“memristors”). In our experimental work, we showed organic nanosynapses adapting automatically as logic gates via a companion digital neuron and programmable logic cell (FGPA). In our theoretical work, we also considered multilayer memristive ANNs. We have developed and simulated random projection (NoProp) and backpropagation (Multilayer Perceptron) variants that use two crossbars. These local learning systems showed critical dependencies on the physical constraints of nanodevices. Finally, we examined how feed-forward ANN designs can be modified to exploit temporal effects. We focused in particular on improving bio-inspiration and performance of the NoProp system, for example, we improved the performance with plasticity effects in the first layer. These effects were obtained using a silver ionic nanodevice with intrinsic plasticity transition behavior.

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Memristive devices are popular among neuromorphic engineers for their ability to emulate forms of spike-driven synaptic plasticity by applying specific voltage and current waveforms at their two terminals. In this paper, we investigate spike-timing dependent plasticity (STDP) with a single pairing of one presynaptic voltage spike and one postsynaptic voltage spike in a BiFeO3 memristive device. In most memristive materials the learning window is primarily a function of the material characteristics and not of the applied waveform. In contrast, we show that the analog resistive switching of the developed artificial synapses allows to adjust the learning time constant of the STDP function from 25ms to 125μs via the duration of applied voltage spikes. Also, as the induced weight change may degrade, we investigate the remanence of the resistance change for several hours after analog resistive switching, thus emulating the processes expected in biological synapses. As the power consumption is a major constraint in neuromorphic circuits, we show methods to reduce the consumed energy per setting pulse to only 4.5 pJ in the developed artificial synapses.

Memristive devices are popular among neuromorphic engineers for their ability to emulate forms of spike-driven synaptic plasticity by applying specific voltage and current waveforms at their two terminals. In this paper, we investigate spike-timing dependent plasticity (STDP) with a single pairing of one presynaptic voltage spike and one postsynaptic voltage spike in a BiFeO3 memristive device. In most memristive materials the learning window is primarily a function of the material characteristics and not of the applied waveform. In contrast, we show that the analog resistive switching of the developed artificial synapses allows to adjust the learning time constant of the STDP function from 25ms to 125μs via the duration of applied voltage spikes. Also, as the induced weight change may degrade, we investigate the remanence of the resistance change for several hours after analog resistive switching, thus emulating the processes expected in biological synapses. As the power consumption is a major constraint in neuromorphic circuits, we show methods to reduce the consumed energy per setting pulse to only 4.5 pJ in the developed artificial synapses.

No description available.

As silicon meets its performance limits, new materials and methods for advancing computing and electronics as a whole are being intensely researched, as described in Chapter 1. Memristors are a fusion of these two research areas, with new materials being pursued concurrently to development of novel architectures to take advantage of these new devices. A background of memristors and an overview of different memristive developments in the field are reviewed in Chapter 2. Chapter 3 delves into the physical mechanisms of analog memristors. To investigate and understand the operation of analog memristors, a finite element method model has been developed. More specifically, the devices simulated include a simple memristor simulation where the lithium ions (dopants) are confined to the device, but allowed to move in response to a voltage applied across the device. To model a more physical memristor, charge carrier mobility dependence on dopant levels was added to the device, resulting in a simulated device that operates similarly to the first simulation. Thereafter, the effect of varying geometries was modeled, and it was determined that both the speed and the resistance change of the device were improved by increasing the ratio of the top and bottom metal contact lengths in a restrictive flow geometry. Finally, the effect of dopant removal was investigated. It was determined that if the greatest change in resistance is required, then the removal of dopants is the optimal operating regime for an analog memristor. Through a greater understanding of analog memristors developed by the simulation described herein, researchers will be able to better harness their power and implement them in bio-inspired systems and architectures.

Made available in DSpace on 2014-06-11T19:27:08Z (GMT). No. of bitstreams: 0 Previous issue date: 2012Bitstream added on 2014-06-13T18:30:56Z : No. of bitstreams: 1 scarabello_mc_me_prud.pdf: 7894728 bytes, checksum: 7780bf65e553d805c887201bc480e587 (MD5) / Coordenação de Aperfeiçoamento de Pessoal de Nível Superior (CAPES) / Fundação de Amparo à Pesquisa do Estado de São Paulo (FAPESP) / Em um artigo publicado em maio de 2008 na revista Nature [17], um grupo de pesquisadores da Hewllet-Packard Company (HP) anunciou a fabricação de um componente eletrônico chamado memristor, uma contração para “memory resistor”. A existência teórica dos memristores havia sido prevista em 1971, pelo Engenheiro da Universidade da Califórnia em Berkeley, Leon Chua, com base em propriedades de simetria de certos circuitos elétricos, porém até 2008 sua existência física não havia sido comprovada. Tal componente é considerado o quarto componente eletrônico fundamental, ao lado do resistor, do capacitor e do indutor, pois possui propriedades que não podem ser duplicadas por nenhuma combinação desses três outros componentes. A construção física do memristor atraiu grande interesse no mundo todo, devido ao grande potencial de aplicações deste componente. No presente trabalho fazemos um estudo das bifurcações que ocorrem em um sistema de equações diferenciais ordinárias, que serve como modelo matemático de um circuito elétrico formado pelos quatro elementos fundamentais: um memristor, um capacitor, um indutor e um resistor. O circuito estudado foi proposto por Itoh e Chua em [9]... / In the present work we make a bifurcation analysis of a system of ordinary differential equations, which serves as a mathematical model of an electric circuit formed by the four fundamental elements: one memristor, one capacitor, one inductor and one resistor. The studied circuit was proposed by Itoh and Chua in [9] and was constructed based on the well-known Chua's oscillators. The studied model is given by a discontinuous piecewise-linear system, defined on three zones in R 3, determined by the following inequalities: |z|<1 (called central zone) and |z|>1 (called external zones). The z-axis is composed by equilibrium points of the system. The local normal stability of these equilibira in each zone is analyzed. We show that, due to the existence of this line of equilibria, the phase space R 3 is foliated by invariant planes transversal to the z-axis and parallel to each other, in each zone. The solutions of the system are contained in a combination of three of these invariant planes: one of them in the central zone and the other two in the external zones. We also show that the system may present nonlinear oscillations due to the existence of periodic orbits passing through two of the three zones or passing by three zones. The analysis developed here has analytical and numerical parts. The analytical part was developed based on the study of planar piecewise-linear systems with three zones presented by Freire et al. in [5]... (Complete abstract click electronic access below)

Threshold logic gates are gaining more importance in recent years due to significant development in switching devices. This renewed the interest in high performance and low power circuits with threshold logic gates. Threshold Logic Gates can be implemented using both the traditional CMOS technologies and the emerging nanoelectronic technologies. In this dissertation, we have performed performance analysis on Monostable-Bistable Threshold Logic Element based, current mode, and memristor based threshold logic implementations. Existing analytical approaches that model the delay of a Monostable-Bistable Threshold Logic Element threshold logic gate cannot explore the enormous search space in the quest of weight assignments on the inputs and threshold in order to optimize the delay of the threshold logic gate. It is shown that this can be achieved by using a quantity that depends on the constants and Resonant Tunnel Diode weights. This quantity is used to form an integer linear program that optimizes the performance and ensure that each weight can tolerate a predetermined variation by an appropriate weight assignment in a threshold logic gate. The presented experimental results demonstrate the impact of the proposed method. The optimality of our solutions and the reported improvements ensure tolerance to potential manufacturing defects. Current mode is a popular CMOS-based implementation of threshold logic functions where the gate delay depends on the sensor size. A new implementation of current mode threshold functions for improved performance and switching energy is presented. An analytical method is also proposed in order to identify quickly the optimum sensor size. Experimental results on different gates with the optimum sensor size indicate that the proposed method outperforms consistently the existing implementations, and implements high performance and low power gates that have a very large number of inputs. A new dual clocked design that uses memristors in current mode logic implementation of threshold logic gates is also presented. Memristor based designs have high potential to improve performance and energy over purely CMOS-based combinational methods. The proposed designs are clocked, and outperform a recently proposed combinational method in performance as well as energy consumption. It is experimentally verified that both designs scale well in both energy consumption as well as delay.