Dans cette thèse nous avons montré que l'on peut on peut synthétiser des nanocristaux de silicium en utilisant des plasmas pulsés de silane dilué dans l'hydrogène. Dans nos conditions de dépôt, en changeant le temps de croissance entre 100 msec et 1 seconde, nous avons pu contrôler la taille des nanocristaux (de 4 nm à 12 nm). A partir de la mesure de la taille des nanocristaux sur les images MET, nous avons pu calculer la vitesse de croissance radiale. Cette vitesse est proportionnelle à la pression partielle de silane dans le mélange gazeux. Nous avons également montré le rôle important de l'hydrogène atomique pour le processus de cristallisation des nanoparticules dans le plasma. La maîtrise de la synthèse des nanocristaux de silicium ouvre la voie à deux champs d'applications : (i) la fabrication de diodes électroluminescences et (ii) la réalisation de transistors à un électron. Pour la première application, une étude préalable de photoluminescence a montré un déplacement vers le bleu du pic de photoluminescence lorsque la taille des nanocristaux diminue. Cela est interprété à la fois comme un effet de confinement quantique et de passivation de la surface des nanocristaux par une coquille de SiOx. Nous avons également élaboré des diodes électroluminescence PIN basées sur les nanocristaux de silicium. Après une optimisation de la structure PIN et des conditions de dépôt de la couche intrinsèque, nous avons obtenu une électroluminescence dans la gamme infrarouge-visible à température ambiante. En vue de l'application aux transistors, nous avons fait des expériences préalables d'injection de charge dans les nanocristaux par AFM/KFM. L'observation qualitative des charges injectées a été réalisée. L'estimation quantitative de ces charges ainsi que l'étude de charges résiduelles dans des nanocristaux dopés est un domaine qui mérite d'être exploré dans l'avenir.

Dans la prochaine ère de l'informatique distribuée, les ordinateurs inspirés par le cerveau qui effectuent des opérations localement plutôt que dans des serveurs distants seraient un avantage majeur en réduisant les coûts énergétiques et réduisant l'impact environnemental. Une nouvelle génération de nanodispositifs de mémoire non-volatile est un candidat de premier plan pour réaliser cette vision neuromorphique. À l'aide de travaux théoriques et expérimentaux, nous avons exploré les problèmes critiques qui se posent lors de la réalisation physique des architectures de réseaux de neurones artificiels modernes (ANN) en utilisant des dispositifs de mémoire émergents (nanodispositifs « memristifs »). Dans notre travail expérimental, nos dispositifs organiques (polymeriques) se sont adaptés avec succès et automatiquement en tant que portes logiques reconfigurables en coopérant avec un neurone digital et programmable (FGPA). Dans nos travaux théoriques, nous aussi avons considéré les multicouches memristives ANNs. Nous avons développé et simulé des variantes de projection aléatoire (un système NoProp) et de rétropropagation (un système perceptron multicouche) qui utilisent deux crossbars. Ces systèmes d'apprentissage locaux ont montré des dépendances critiques sur les contraintes physiques des nanodispositifs. Enfin, nous avons examiné comment les conceptions ANNs “feed-forward” peuvent être modi-fiées pour exploiter les effets temporels. Nous avons amélioré la bio-inspiration et la performance du système NoProp, par exemple, avec des effets de plasticité dans la première couche. Ces effets ont été obtenus en utilisant un nanodispositif à ionisation d'argent avec un comportement de transition de plasticité intrinsèque. / In the next era of distributed computing, brain-based computers that perform operations locally rather than in remote servers would be a major benefit in reducing global energy costs. A new generation of emerging nonvolatile memory devices is a leading candidate for achieving this neuromorphic vision. Using theoretical and experimental work, we have explored critical issues that arise when physically realizing modern artificial neural network (ANN) architectures using emerging memory devices (“memristors”). In our experimental work, we showed organic nanosynapses adapting automatically as logic gates via a companion digital neuron and programmable logic cell (FGPA). In our theoretical work, we also considered multilayer memristive ANNs. We have developed and simulated random projection (NoProp) and backpropagation (Multilayer Perceptron) variants that use two crossbars. These local learning systems showed critical dependencies on the physical constraints of nanodevices. Finally, we examined how feed-forward ANN designs can be modified to exploit temporal effects. We focused in particular on improving bio-inspiration and performance of the NoProp system, for example, we improved the performance with plasticity effects in the first layer. These effects were obtained using a silver ionic nanodevice with intrinsic plasticity transition behavior.

At the beginning of this thesis, basic and advanced device fabrication process which I haveexperienced during study such as top-down and bottom-up approach for the nanoscale devicefabrication technique have been described. Especially, lithography technology has beenfocused because it is base of the modern device fabrication. For the advanced device structure,etching technique has been investigated in detail.The characterization of FET has been introduced. For the practical consideration in theadvanced FET, several parameter extraction techniques have been introduced such as Yfunction,split C-V etc.FinFET is one of promising alternatives against conventional planar devices. Problem ofFinFET is surface roughness. During the fabrication, the etching process induces surfaceroughness on the sidewall surfaces. Surface roughness of channel decreases the effectivemobility by surface roughness scattering. With the low temperature measurement andmobility analysis, drain current through sidewall and top surface was separated. From theseparated currents, effective mobilities were extracted in each temperature conditions. Astemperature lowering, mobility behaviors from the transport on each surface have differenttemperature dependence. Especially, in n-type FinFET, the sidewall mobility has strongerdegradation in high gate electric field compare to top surface. Quantification of surfaceroughness was also compared between sidewall and top surface. Low temperaturemeasurement is nondestructive characterization method. Therefore this study can be a propersurface roughness measurement technique for the performance optimization of FinFET.As another quasi-1 D nanowire structure device, 3D stacked SiGe nanowire has beenintroduced. Important of strain engineering has been known for the effective mobility booster.The limitation of dopant diffusion by strain has been shown. Without strain, SiGe nanowireFET showed huge short channel effect. Subthreshold current was bigger than strained SiGechannel. Temperature dependent mobility behavior in short channel unstrained device wascompletely different from the other cases. Impurity scattering was dominant in short channelunstrained SiGe nanowire FET. Thus, it could be concluded that the strain engineering is notnecessary only for the mobility booster but also short channel effect immunity.Junctionless FET is very recently developed device compare to the others. Like as JFET,junctionless FET has volume conduction. Thus, it is less affected by interface states.Junctionless FET also has good short channel effect immunity because off-state ofjunctionless FET is dominated pinch-off of channel depletion. For this, junctionless FETshould have thin body thickness. Therefore, multi gate nanowire structure is proper to makejunctionless FET.Because of the surface area to volume ratio, quasi-1D nanowire structure is good for thesensor application. Nanowire structure has been investigated as a sensor. Using numericalsimulation, generation-recombination noise property was considered in nanowire sensor.Even though the surface area to volume ration is enhanced in the nanowire channel, devicehas sensing limitation by noise. The generation-recombination noise depended on the channelgeometry. As a design tool of nanowire sensor, noise simulation should be carried out toescape from the noise limitation in advance.The basic principles of device simulation have been discussed. Finite difference method andMonte Carlo simulation technique have been introduced for the comprehension of devicesimulation. Practical device simulation data have been shown for examples such as FinFET,strongly disordered 1D channel, OLED and E-paper.

At the beginning of this thesis, basic and advanced device fabrication process which I haveexperienced during study such as top-down and bottom-up approach for the nanoscale devicefabrication technique have been described. Especially, lithography technology has beenfocused because it is base of the modern device fabrication. For the advanced device structure,etching technique has been investigated in detail.The characterization of FET has been introduced. For the practical consideration in theadvanced FET, several parameter extraction techniques have been introduced such as Yfunction,split C-V etc.FinFET is one of promising alternatives against conventional planar devices. Problem ofFinFET is surface roughness. During the fabrication, the etching process induces surfaceroughness on the sidewall surfaces. Surface roughness of channel decreases the effectivemobility by surface roughness scattering. With the low temperature measurement andmobility analysis, drain current through sidewall and top surface was separated. From theseparated currents, effective mobilities were extracted in each temperature conditions. Astemperature lowering, mobility behaviors from the transport on each surface have differenttemperature dependence. Especially, in n-type FinFET, the sidewall mobility has strongerdegradation in high gate electric field compare to top surface. Quantification of surfaceroughness was also compared between sidewall and top surface. Low temperaturemeasurement is nondestructive characterization method. Therefore this study can be a propersurface roughness measurement technique for the performance optimization of FinFET.As another quasi-1 D nanowire structure device, 3D stacked SiGe nanowire has beenintroduced. Important of strain engineering has been known for the effective mobility booster.The limitation of dopant diffusion by strain has been shown. Without strain, SiGe nanowireFET showed huge short channel effect. Subthreshold current was bigger than strained SiGechannel. Temperature dependent mobility behavior in short channel unstrained device wascompletely different from the other cases. Impurity scattering was dominant in short channelunstrained SiGe nanowire FET. Thus, it could be concluded that the strain engineering is notnecessary only for the mobility booster but also short channel effect immunity.Junctionless FET is very recently developed device compare to the others. Like as JFET,junctionless FET has volume conduction. Thus, it is less affected by interface states.Junctionless FET also has good short channel effect immunity because off-state ofjunctionless FET is dominated pinch-off of channel depletion. For this, junctionless FETshould have thin body thickness. Therefore, multi gate nanowire structure is proper to makejunctionless FET.Because of the surface area to volume ratio, quasi-1D nanowire structure is good for thesensor application. Nanowire structure has been investigated as a sensor. Using numericalsimulation, generation-recombination noise property was considered in nanowire sensor.Even though the surface area to volume ration is enhanced in the nanowire channel, devicehas sensing limitation by noise. The generation-recombination noise depended on the channelgeometry. As a design tool of nanowire sensor, noise simulation should be carried out toescape from the noise limitation in advance.The basic principles of device simulation have been discussed. Finite difference method andMonte Carlo simulation technique have been introduced for the comprehension of devicesimulation. Practical device simulation data have been shown for examples such as FinFET,strongly disordered 1D channel, OLED and E-paper. / At the beginning of this thesis, basic and advanced device fabrication process which I haveexperienced during study such as top-down and bottom-up approach for the nanoscale devicefabrication technique have been described. Especially, lithography technology has beenfocused because it is base of the modern device fabrication. For the advanced device structure,etching technique has been investigated in detail.The characterization of FET has been introduced. For the practical consideration in theadvanced FET, several parameter extraction techniques have been introduced such as Yfunction,split C-V etc.FinFET is one of promising alternatives against conventional planar devices. Problem ofFinFET is surface roughness. During the fabrication, the etching process induces surfaceroughness on the sidewall surfaces. Surface roughness of channel decreases the effectivemobility by surface roughness scattering. With the low temperature measurement andmobility analysis, drain current through sidewall and top surface was separated. From theseparated currents, effective mobilities were extracted in each temperature conditions. Astemperature lowering, mobility behaviors from the transport on each surface have differenttemperature dependence. Especially, in n-type FinFET, the sidewall mobility has strongerdegradation in high gate electric field compare to top surface. Quantification of surfaceroughness was also compared between sidewall and top surface. Low temperaturemeasurement is nondestructive characterization method. Therefore this study can be a propersurface roughness measurement technique for the performance optimization of FinFET.As another quasi-1 D nanowire structure device, 3D stacked SiGe nanowire has beenintroduced. Important of strain engineering has been known for the effective mobility booster.The limitation of dopant diffusion by strain has been shown. Without strain, SiGe nanowireFET showed huge short channel effect. Subthreshold current was bigger than strained SiGechannel. Temperature dependent mobility behavior in short channel unstrained device wascompletely different from the other cases. Impurity scattering was dominant in short channelunstrained SiGe nanowire FET. Thus, it could be concluded that the strain engineering is notnecessary only for the mobility booster but also short channel effect immunity.Junctionless FET is very recently developed device compare to the others. Like as JFET,junctionless FET has volume conduction. Thus, it is less affected by interface states.Junctionless FET also has good short channel effect immunity because off-state ofjunctionless FET is dominated pinch-off of channel depletion. For this, junctionless FETshould have thin body thickness. Therefore, multi gate nanowire structure is proper to makejunctionless FET.Because of the surface area to volume ratio, quasi-1D nanowire structure is good for thesensor application. Nanowire structure has been investigated as a sensor. Using numericalsimulation, generation-recombination noise property was considered in nanowire sensor.Even though the surface area to volume ration is enhanced in the nanowire channel, devicehas sensing limitation by noise. The generation-recombination noise depended on the channelgeometry. As a design tool of nanowire sensor, noise simulation should be carried out toescape from the noise limitation in advance.The basic principles of device simulation have been discussed. Finite difference method andMonte Carlo simulation technique have been introduced for the comprehension of devicesimulation. Practical device simulation data have been shown for examples such as FinFET,strongly disordered 1D channel, OLED and E-paper.

Les matériaux ferroélectriques sont des matériaux qui possèdent une polarisation spontanée en l'absence de champ électrique, leur conférant plusieurs propriétés intéressantes du point de vue des applications possibles. La réduction de l'épaisseur des couches ferroélectriques vers des films minces et ultra-minces s'est avérée nécessaire notamment en vue de leur intégration dans les dispositifs de la micro et nano-électronique. Cependant, cette diminution a fait apparaître certains phénomènes indésirables au sein des couches minces tels que les courants de fuite. La caractérisation électrique de ces matériaux reste donc un défi afin de comprendre les mécanismes physiques en jeu dans ces films, d'autant qu'une information à l'échelle très locale est maintenant requise. Il est donc nécessaire de faire progresser les techniques de mesure électrique pour atteindre ces objectifs. Durant cette thèse, nous mesurons la polarisation diélectrique de l'échelle mésoscopique jusqu'à l'échelle nanométrique en utilisant des caractérisations purement électriques constituées de mesures Polarisation-Tension, Capacité-Tension et Courant-Tension mais aussi des mesures électromécaniques assurées par une technique dérivée de la microscopie à force atomique et nommée Piezoresponse Force Microscopy. Au cours de nos travaux, nous montrons la limite de certaines techniques de caractérisation classiques ainsi que les artéfacts affectant la mesure électrique ou électromécanique et pouvant mener à une mauvaise interprétation des résultats de mesure. Afin de pousser nos investigations plus loin, nous avons développé de nouvelles techniques de mesure pour s'affranchir de certains signaux parasites dont nous exposerons le principe de fonctionnement. Nous présentons les premières mesures directes de polarisation rémanente à l'échelle du nanomètre grâce à une technique que nous nommons nano-PUND. Ces techniques et méthodes sont appliquées à une variété importante de matériaux tels que Pb(Zr,Ti)O3, GaFeO3 ou BaTiO3 dont, pour certains, la ferroélectricité n'a jamais été démontrée expérimentalement sans ambiguïté. / Ferroelectric materials show a spontaneous dielectric polarisation even in the absence of applied electric field, which confers them interesting possibilities of applications. The reduction of the thickness of ferroelectric layers towards ultra-thin values has been necessary in view of their integration in micro and nano-electronic devices. However, the reduction of thickness has been accompanied by unwanted phenomena in thin layers such as tunneling currents and more generally leakage currents. The electrical characterization of these materials remains a challenge which aims at better understanding the physical mechanisms at play, and requires now a nanometric spatial resolution. To do so, it is thus mandatory to enhance the techniques of electrical measurement. In this work, we measure the dielectric polarisation of ferroelectric films from mesoscopic scale down to the nanometric scale using purely electric characterisation techniques (Polarisation vs Voltage, Capacitance vs Voltage, Current vs Voltage), but also electro-mechanical techniques like Piezoresponse Force Microscopy which derives from Atomic Force Microscopy. We show the limits of several classical techniques as well as the artefacts which affect electrical or electro-mechanical measurement and may lead to an incorrect interpretation of the data. In order to push the investigation further, we have developed and we describe new measurement techniques which aim at avoiding some parasitic signals. We present the first direct measurement of the remnent polarisation at the nanoscale thanks to a technique which we call « nano-PUND ». These techniques and methods are applied to a large variety of materials like Pb(Zr,Ti)O3, GaFeO3 or BaTiO3 which (for some of them), ferroelectricity has not been measured experimentally.