The functionalization of the outer lattice of in vitro reconstituted microtubules has paved the way for the development of diverse nano-device applications. The outer lattice has been metallized for the bottom-up synthesis of nanowires composed of various materials. Moreover, a wide range of biomolecules and nanoprobes have been attached to the outer surface for nano-scale transport and detection assays in conjunction with motor proteins. The functionalization of the outer lattice has certain implications: While the nanowires adopt the overall shape of the microtubules, their surface is inhomogeneous due to the absence of any morphological control. The attachment of cargo on the outer lattice creates a ‘roadblock effect’ hindering the transport activity of the motor proteins as they share a common substrate surface. In this project, the utilization of the hollow interior region of the microtubules, called the lumen (∼15 nm in diameter) is proposed to overcome these limitations. A strategy is developed to functionalize the microtubule lumen by targeting molecular cargo conjugated to lumen-binding (anti-acetyl alpha-tubulin lysine-40) antibodies. This would optimize existing motility-based applications as the outer surface would be exclusively available for the activity of the motor proteins. Furthermore, microtubules functionalized with luminal gold nanoparticle ‘seeds’ are utilized for the lumen-templated assembly of gold nanowires.

<p>As  thefundamentallimits  of  two-dimensional(2D)geometric  scaling  of  commercial transistors  are  being reached,  there  is  tremendous  demand  for  new  materials  and  process innovations  that  can  keep  delivering  performance  improvements  for  future  generations  of computing chips. One major avenue being explored istheincorporation ofan increasing degree of three-dimensionality   by   vertically   stacking   logic   and   memory   layerswith   high-density interconnections.In  this  dissertation,  high-performanceultra-thin  amorphousindium  oxide transistors  are  demonstrated as  an  excellent  candidate  for these  back-end-of-line  (BEOL)  and monolithic 3D (M3D) integration applications.</p> <p>A  major  pain-point  in the  development  of  BEOL  and  M3D  systems is  the  strict  thermal budget imposed –once the bottom layer of devices is fabricated, they can generally withstand no more  than  400 °C.  It  is  exceedingly  difficult  to  directly  deposit  single-crystal  material  at  these temperatures, and polycrystalline materials will have grain boundary instability issues. Amorphous materials  generally  have  low  carrier  mobilities,  which  would  seemingly  remove  them  from contention as well. Indium oxideand itsclass of related metal oxides are exceptions. Indium oxideis  a  wide  bandgap  semiconductor  with  high  electron  mobility  up  to  about  100  cm²/V∙s  in amorphous form. Ithas a strong preference for native degenerate n-type doping which has hindered prior  devices  fabricated  with it.  In  this  dissertation,  extremely  thin  layers  on  the  order  of  1  nm thick are used for which quantum confinement effects widen the bandgap further, reliably enabling gate-controllable  carrier  densitiesand  demonstration  of  excellent  transistor  performance  with  a low thermal budget of just 225 °C.</p> <p>Detailed characterization is performed down to 40 nm channel lengths revealing excellent transistor characteristics  includingenhancement-mode operation withon currents greater than 2 A/μm, low  subthreshold  swing,and  high  on/off  ratios  due  to  the  wide  bandgap.  Subsequent chaptersdemonstrate the fundamental lower limits of off current around 6 ×10^-20A/μmby a novel measurement  technique,  good  gate  bias  stress  stability  behaviorwith  small  parameter  drift  at silicon  complementary  metal  oxide  semiconductor  (CMOS)  logic  voltages,  and  high-frequency operationin the GHz regime enabling easy operation at CMOS clock frequencies.</p>

<p>  </p> <p>By means of this dissertation we bring to light that FETs (that are either Si or 2D-TMD based) when coupled with piezoelectric or ferroelectric materials can offer attractive solutions such as (i) technology scaling, (ii) non-volatile memory functionality and (iii) beyond-von-Neumann computing paradigms that address the limitations of current architectures. Our efforts encompass the domains of steep switching devices, non-volatile memories, computation-in-memory and non-Boolean computing, wherein we explore devices embedded with piezoelectric (strain-based) and ferroelectric (polarization-based) properties and propose novel circuits based on them, while focusing on understanding their device-circuit interactions and system implications.</p>

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<p>With the advent of increasingly complex radio systems at higher frequencies and the slowing of traditional CMOS process scaling with power concerns, there has been an increased focus on integration, architectural, and material innovations as a continued path forward in MEMS and logic. This work presents the first comprehensive experimental study of resonant body transistors in a commercial 14nm FinFET process, demonstrating differential radio frequency transduction as a function of transistor biasing through electrostatic, piezoresistive, and threshold voltage modulation. The impact of device design changes on unreleased resonator performance are further explored, highlighting the importance of phononic confinement in achieving an f*Q product of 8.2*10¹¹ at 11.73 GHz. Also shown are initial efforts towards the understanding of coupled oscillator architectures and a perovskite nickelate material system. Finally, development of resonators based on two-dimensional materials, whose scale is particularly attractive for high-frequency nano-mechanical resonators and acoustic devices, is discussed. Experiments towards dry transfer of tellurene flakes using geometries printed via two photon polymerization are presented along with optimization of a fabrication process for gated RF devices, presenting new opportunities for high-frequency electro-mechanical interactions in this topological material. </p>

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Ce travail de thèse se compose de deux parties : tout d’abord nous avons caractérisé sur le plan morphologique des motifs de TiOx réalisés par anodisation localisée par AFM (LAO) dans des couches pleines plaques de 5 nm de titane. Nous avons étudié l’influence de la tension d’oxydation, de la vitesse de balayage de la pointe AFM, de l’humidité relative de l’environnement, du mode AFM (contact ou intermittent) et du type de pointe. Les motifs les plus fins atteignent une largeur à mi-hauteur de 21 nm pour 2.2 nm de hauteur, ils sont obtenus avec une pointe PtSi utilisée en mode intermittent sous une tension de polarisation de -7V, une vitesse de balayage de 0.4 µm.s-1 et dans un environnement comportant une humidité de 43%. La deuxième partie de notre travail a été consacrée à l’élaboration et à la caractérisation de jonctions planaires MIM Ti/TiOx/Ti. Ces jonctions sont des motifs TLM de titane comportant une ligne transverse de TiOx réalisée par LAO. Lorsque les jonctions sont stressées électriquement sous air, une transformation morphologique irréversible se produit pour une densité de courant et un champ électrique atteignant de l’ordre de 7.1010 A.m-2 et 3.107 V.m-1 respectivement. Des analyses chimiques et structurales basées sur la microscopie électronique à transmission ont montré que la ligne initiale de TiOx amorphe s’était considérablement élargie et est constituée d’une zone de TiOx cristallin. Cette transformation peut être évitée en appliquant le stress électrique sous vide. Enfin des mesures électriques en température ont permis d’élucider les mécanismes de conduction : émission Schottky sous vide et conduction ionique sous air. / This work is divided in two specific parts: first of all we caracterized oxide patterns made by local anodic oxidation using an AFM on 5nm titanium wafers. We caracterized the morphology of the patterns. We studied the influence of several parameters such as oxidation voltage, writing speed of the AFM tip, relative humidity of the environment, AFM modes (contact or tapping)and the type of the tips we used. Most thinnest pattern we made reaches a full width at half maximum of 21nm with a 2.2nm height. It was obtained using a PtSi coating tip in tapping mode with an oxidation voltage of -7V, a writing speed of 0.4 um/s and a relative humidity of 43%. The second part of our work was dedicated to the realization and the characterization of planar MIM junction Ti/TiOx/Ti. These junctions are TLM patterns with a TiOx line cross-ways over the microwire of the TLM pattern. When the junctions are stressed electrically under ambient atmosphere, an irreversible morphological transformation is happenning for a current density and an electric field of 7.1010 A/m² and 3.107 V/m respectively. Chemical and structural analysis based on transmission electronic microscopy have shown that the initial amorphous TiOx junction have grown importantly with an area of crystalline TiOx. This transformation can be avoided by applying the electric stress under vacuum. Finally, electrical measurements in temperature highlighted the transport mecanisms within the junction: Schottky emission under vacuum and ionic conduction under ambient atmosphere.

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