This thesis deals with output power calibration of a mobile platform that supports EGPRS.Two different topics are examined. First some different measurement methods are compared concerning cost efficiency, accuracy, and speed and later measurements are carried out on a mobile platform. The output power from the mobile platform is controlled by three parameters and the influence on the output power when varying those parameters is investigated and presented. Furthermore, two methods of improving the speed of the calibration are presented. The first one aims to decrease the number of bursts to average over as much as possible. The conclusion is that 10-20 bursts are enough for GMSK modulation and about five bursts for 8PSK modulation. The purpose of the second investigation is to examine the possibility to measure the output power in one modulation and frequency band, and then calculate the output power in the other bands. The conclusion in this case is that, based on the units investigated, it is possible for some values of the parameters and in some frequency bands. However, more units need to be included in the basic data for decision-making and it is possible that the hardware variation is too large.

Recent advancements in silicon technology have paved the way for the development of integrated transceivers operating well inside the mm-wave frequency range (30 - 300 GHz). This band offers opportunities for new applications such as remote sensing, short range radar, active imaging and multi-Gb/s radios. This thesis presents new ideas at the circuit and system level for a variety of such applications, up to 145 GHz and in both state-of-the-art nanoscale CMOS and SiGe BiCMOS technologies. After reviewing the theory of operation behind linear and power amplifiers, a purely digital, scalable solution for power amplification that takes advantage of the significant ft/fmax improvement in pFETs as a result of strain engineering in nanoscale CMOS is presented. The proposed Class-D power amplifier, features a stacked, cascode CMOS inverter output stage, which facilitates high voltage operation while employing only thin-oxide devices in a 45 nm SOI CMOS process. Next, a single-chip, 70-80 GHz wireless transceiver for last-mile point-to-point links is described. The transceiver was fabricated in a 130 nm SiGe BiCMOS technology and can operate at data rates in excess of 18 Gbps. The high bitrate is accomplished by taking advantage of the ample bandwidth available at the W-band frequency range, as well as by employing a direct QPSK modulator, which eliminates the need for separate upconversion and power amplification. Lastly, the system and circuit level implementation of a mm-wave precision distance and velocity sensor at 122 and 145 GHz is presented. Both systems feature a heterodyne architecture to mitigate the receiver 1/f noise, as well as self-test and calibration capabilities along with simple packaging techniques to reduce the overall system cost.

Recent advancements in silicon technology have paved the way for the development of integrated transceivers operating well inside the mm-wave frequency range (30 - 300 GHz). This band offers opportunities for new applications such as remote sensing, short range radar, active imaging and multi-Gb/s radios. This thesis presents new ideas at the circuit and system level for a variety of such applications, up to 145 GHz and in both state-of-the-art nanoscale CMOS and SiGe BiCMOS technologies. After reviewing the theory of operation behind linear and power amplifiers, a purely digital, scalable solution for power amplification that takes advantage of the significant ft/fmax improvement in pFETs as a result of strain engineering in nanoscale CMOS is presented. The proposed Class-D power amplifier, features a stacked, cascode CMOS inverter output stage, which facilitates high voltage operation while employing only thin-oxide devices in a 45 nm SOI CMOS process. Next, a single-chip, 70-80 GHz wireless transceiver for last-mile point-to-point links is described. The transceiver was fabricated in a 130 nm SiGe BiCMOS technology and can operate at data rates in excess of 18 Gbps. The high bitrate is accomplished by taking advantage of the ample bandwidth available at the W-band frequency range, as well as by employing a direct QPSK modulator, which eliminates the need for separate upconversion and power amplification. Lastly, the system and circuit level implementation of a mm-wave precision distance and velocity sensor at 122 and 145 GHz is presented. Both systems feature a heterodyne architecture to mitigate the receiver 1/f noise, as well as self-test and calibration capabilities along with simple packaging techniques to reduce the overall system cost.

The aim of this thesis is to introduce to reader the application and use of optical EDFA amplifiers in optical transmission and to show wiring and practical test, including measurements on amplifier. The aim of this thesis is to propose the use of optical amplifier in laboratory practice for subject Optical networks. The thesis briefly introduces the problems of data transmissions through optical fibers with a focus on the use of optical amplifiers. The basic characteristic of optical transmission paths and the reasons for the use of optical amplifiers are described here. One entire chapter is devoted to distinction of optical amplifiers. Amplifiers can be divided according to location in the transmission path to the booster, in-line and pre-amplifiers and according to the used of amplifying technology to optical amplifiers with subsidies, semiconductor optical amplifiers and Raman optical amplifiers. The factors affecting the efficiency of optical amplifiers, such as noise and the level of saturated power are mentioned here too. The different types of optical amplifiers from the two producers are also described. From these amplifiers was chosen EDFA CzechLight Amplifier from Optokon to be used for the laboratory exercise in the subject of Optical networks. The use of EDFA optical amplifiers in optical transmission lines is mentioned here too. These amplifiers can be used in telecommunications transmission systems and for data transmission over long distances. They will find use in WDM transmission systems and cable TV distribution through the optical fiber to the end users. Practical measurements were performed on optical amplifier CLA-PB01F. In the transmission route was located attenuator and the dependence of output power to input signal power was measured. The amplification course was linear in the range of input values provided by the manufacturer. Laboratory exercise for the subject of Optical networks is aimed at preacquaintance of students with problems EDFA optical amplifiers and practical measurements with the optical amplifier CLA-PB01F. Students acquire basic theoretical knowledge of the issue and verify the functionality of optical amplifiers on a specific exercise. This work is destined for all who wish to get basic knowledge of optical amplifiers, their characteristics and possibilities of their use in optical transmission lines.

The aim of this work is to create an automated workplace for measuring the basic parameters of audio amplifiers using a graphical programming environment LabVIEW. Subsequently, the functionality will be verified in practical measurements on the real amplifier.

This master´s thesis with the peripheral and structural design of power converter that will be used for DC welding. The drive itself is based on the principle of two single-acting permeable converters operating in counter strokes to a mutual load. The inverter operates at a frequency of 60kHz, and its output current can be controlled from 0 - 100A. Welder is equipped with a variable constant current or power adjustment. The device is powered from a single-phase 230V.

This thesis aims to increase photovoltaic (PV) panel power efficiency by employing a cooling system based on water circulation, which represents an improved version of water flow based active cooling systems. Theoretical calculations involved finding the heat produced by the PV panel and the circulation water flow required to remove this heat. A data logger and a cooling system for a test panel of 20W was designed and employed to study the relationship between the PV panel surface temperature and its output power. This logging and cooling system includes an Arduino microcontroller extended with a data logging shield, temperature sensing probes, current sensors, and a DC water pump. Real-time measurements were logged every minute for one or two day periods under various irradiance and air temperature conditions. For these experiments, a load resistance was chosen to operate the test panel at its maximum power point. Results indicate that the cooling system can yield an improvement of 10% in power production. Based on the observations from the test panel experiments, a cooling system was devised for a PV panel array of 640 W equipped with a commercial charge controller. The test data logger was repurposed for this larger system. An identical PV array was left uncooled and monitored simultaneously to compare the effect of cooling, demonstrating that the cooled array provided up to an extra 132W or 20% of maximum power for sunny weather conditions. Future expansion possibilities of the project include automated water level monitoring system and water filtration systems.

Phased array element RF front ends typically use single pole double throw (SPDT) switches or circulators with high isolation to prevent leakage of transmit energy into the receiver circuits. However, as phased-array designs scale to the millimeter-wave range, with high degrees of integration, the physical size and performance degradations associated with switches and circulators can present challenges in meeting system performance and size/weight/power (SWAP) requirements. This work demonstrates a loss-aware methodology for analysis and design of switchless transmit/receive (T/R) circuits. The methodology provides design insights and a practical, generally applicable approach for solving the multi-variable optimization problem of switchless power amplifier/low-noise amplifier (PALNA) matching networks, which present optimal matching impedances to both the power amplifier (PA) and the low noise amplifier (LNA) while maximizing power transfer efficiency and minimizing dissipative losses in each (transmit or receive) mode of operation. Three PALNA example designs at W-band are presented in this dissertation, each following a distinct design methodology. The first example design in 32SOI CMOS leverages PA and LNA circuits that already include 50 Ω matching networks at both input and output. The second example design in 8XP SiGe develops the PA and LNA circuits and integrates the PA output and LNA input matching networks into the PALNA matching network that connects the PA and the LNA. The third design in 32SOI CMOS leverages the loss-aware PALNA design methodology to develop a PALNA that achieves simulated maximum power added efficiency of 18 % in transmit and noise figure of 7.5 dB in receive at 94 GHz, which is beyond the published state-of-art for T/R circuits. In addition, for comparison purposes, this dissertation also presents an efficient, switch-based T/R circuit design in 32SOI CMOS technology, which achieves a simulated maximum power added efficiency of 15 % in transmit and noise figure of 6.5 dB in receive at 94 GHz, which is also beyond the published state-of-art for T/R circuits. / Doctor of Philosophy / In military and commercial applications, phased arrays are devices primarily used to achieve focusing and steering of transmitted or received electromagnetic energy. Phased arrays consist of many elements, each with an ability to both transmit and receive radio frequency (RF) signals. Each element incorporates a power amplifier (PA) for transmit and a low noise amplifier (LNA) for receive, which are typically connected using a single pole double throw (SPDT) switch or a circulator with high isolation to prevent leakage of transmit energy into the receiver circuits. However, as phased arrays exploit the latest technological advances in circuit integration and their frequencies of operation increase, physical size and performance degradations associated with switches and circulators can present challenges in meeting system performance and size/weight/power (SWAP) requirements. This dissertation provides a loss-aware methodology for analysis and design of switchless transmit/receive (T/R) circuits where the switches and circulators are replaced by carefully designed power amplifier/low-noise amplifier (PALNA) impedance matching networks. In the switchless T/R circuits, the design goals of maximum power efficiency and minimum noise in transmit and receive, respectively, are achieved through impedance matching that is optimal and low-loss in both modes of operation simultaneously. Three distinct PALNA example designs at W-band are presented in this dissertation, each following a distinct design methodology. With each new design, lessons learned are leveraged and design methodologies are enhanced. The first example design leverages already available PA and LNA circuits and connects them using 50 Ω transmission lines whose lengths are designed to guarantee optimum impedance match in receive and transmit mode of operation. The second example design develops new PA and LNA circuits and connects them using 50 Ω transmission lines whose lengths are designed to simultaneously achieve optimum impedance matching for maximum power efficiency in transmit mode of operation and lowest noise in receive mode of operation. The third design leverages a loss-aware PALNA design methodology, a multi-variable optimization procedure, to develop a PALNA that achieves simulated maximum power added efficiency of 18 % in transmit and noise figure of 7.5 dB in receive at 94 GHz, which is beyond the published state-of-art for T/R circuits. In addition, for comparison purposes with the third PALNA design, this dissertation also presents an efficient, switch-based T/R circuit design, which achieves a simulated maximum power added efficiency of 15 % in transmit and noise figure of 6.5 dB in receive at 94 GHz, which is also beyond the published state-of-art for T/R circuits.

<p dir="ltr">The short lifespan of capacitors in power electronics converters is a significant challenge. These capacitors, often electrolytic, are vital for voltage smoothing and frequency filtering. However, their susceptibility to heat, ripple current, and aging can lead to premature faults. This can cause issues like output voltage instability and short circuits, ultimately resulting in catastrophic failure and system shutdown. Capacitors are responsible for 30% of power electronics failures.</p><p dir="ltr">To tackle this challenge, scientists, researchers, and engineers are exploring various approaches detailed in technical literature. These include exploring alternative capacitor technologies, implementing active and passive cooling solutions, and developing advanced monitoring techniques to predict and prevent failures. However, these solutions often come with drawbacks such as increased complexity, reduced efficiency, or higher upfront costs. Additionally, research in material science is ongoing to develop corrosion-resistant capacitors, but such devices are not readily available.</p><p dir="ltr">This dissertation presents a capacitorless solution for dc-dc and dc-ac converters. The proposed solution involves harnessing parasitic elements and integrating them as intrinsic components in power converter technology. This approach holds the promise of enhancing power electronics reliability ratings, thereby facilitating breakthroughs in electric vehicles, compact power processing units, and renewable energy systems. The central scientific premise of this proposal is that the capacitance requirement in a power converter can be met by deliberately augmenting parasitic components.</p><p dir="ltr">Our research hypothesis that incorporating high dielectric material-based thin-films, fabricated using nanotechnology, into planar magnetics will enable the development of a family of capacitorless electronic converters that do not rely on discrete capacitors. This innovative approach represents a departure from the traditional power converter schemes employed in industry.</p><p dir="ltr">The first family of converters introduces a novel capacitorless solid-state power filter (SSPF) for single-phase dc-ac converters. The proposed configuration, comprising a planar transformer and an H-bridge converter operating at high frequency, generates sinusoidal ac voltage without relying on capacitors. Another innovative dc-ac inverter design is the twelve step six-level inverter, which does not incorporate capacitors in its structure.</p><p dir="ltr">The second family of capacitorless topologies consists of non-isolated dc-dc converters, namely the buck converter and the buck-boost converter. These converters utilize alternative materials with high dielectric constants, such as calcium copper titanate (CCTO), to intentionally enhance specific parasitic components, notably inter capacitance. This innovative approach reduces reliance on external discrete capacitors and facilitates the development of highly reliable converters.</p><p dir="ltr">The study also includes detailed discussions on the necessary design specifications for these parasitic capacitors. Furthermore, comprehensive finite element analysis solutions and detailed circuit models are provided. A design example is presented to demonstrate the practical application of the proposed concept in electric vehicle (EV) low voltage side dc-dc power converters used to supply EVs low voltage loads.</p>