Approved for public release; distribution is unlimited / OFDM systems have experienced increased attention in recent years and have found applications in a number of diverse areas including telephone-line based ADSL links, digital audio and video broadcasting systems, and wireless local area networks (WLAN). Orthogonal frequency-division multiplexing (OFDM) is a powerful technique for high data-rate transmission over fading channels. However, to deploy OFDM in a WLAN environment, precise frequency synchronization must be maintained and tricky frequency offsets must be handled. In this thesis, various techniques to improve the data throughput of OFDM WLAN are investigated. A simulation tool was developed in Matlab to evaluate the performance of the IEEE 802.11a physical layer. We proposed a rapid time and frequency synchronization algorithm using only the short training sequence of the IEEE 802.11a standard, thus reducing the training overhead to 50%. Particular attention was paid to channel coding, block interleaving and antenna diversity. Computer simulation showed that drastic improvement in error rate performance is achievable when these techniques are deployed. / Lieutenant, Hellenic Navy

Approved for public release, distribution is unlimited / Orthogonal frequency division multiplexing (OFDM) is being successfully used in numerous applications. It was chosen for IEEE 802.11a wireless local area network (WLAN) standard, and it is being considered for the fourthgeneration mobile communication systems. Along with its many attractive features, OFDM has some principal drawbacks. Sensitivity to frequency errors is the most dominant of these drawbacks. In this thesis, the frequency offset and phase noise effects on OFDM based communication systems are investigated under a variety of channel conditions covering both indoor and outdoor environments. The simulation performance results of the OFDM system for these channels are presented. / Lieutenant Junior Grade, Turkish Navy

This thesis presents a body of work on the theme of millimetre-wave FMCW radar, for the purposes of security screening and remote sensing. First, the development of an optimised software radar signal processor will be outlined. Through use of threading and GPU acceleration, high data processing rates were achieved using standard PC hardware. The flexibility of this approach, compared to specialised hardware (e.g. DSP, FPGA etc…), allowed the processor to be rapidly adapted and has produced a significant performance increase in a number of advanced real-time radar systems. An efficient tracker was developed and was successfully deployed in live trials for the purpose of real-time wave detection in an autonomous boat control system. Automated radar operation and remote data telemetry functions were implemented in a terrain mapping radar to allow continuous monitoring of the Soufrière Hills volcano on the Caribbean island of Montserrat. This work concluded with the installation of the system 3 km from the volcano. Hardware modifications were made to enable coherent measurement in a number of existing radar systems, allowing phase sensitive measurements, including range-Doppler, to be performed. Sensitivity to displacements of less than 200 nm was demonstrated, which is limited by the phase noise of the system. Efficient compensation techniques are presented which correct for quadrature mixer imbalance, FMCW chirp non-linearity, and scanner drive distortions. In collaboration with the Home Office, two radar systems were evaluated for the stand-off detection of concealed objects. Automatic detection capability, based on polarimetric signatures, was developed using data gathered under controlled conditions. Algorithm performance was assessed through blind testing across a statistically significant number of subjects. A detailed analysis is presented, which evaluates the effect of clothing and object type on detection efficiency.

Le travail presente dans ce memoire a pour objet principal l'etude des phenomenes de bruit du fond electrique basse frequence dans des transistors pour applications micro-ondes de type effet de champ (HEMT) sur SiGe et GaN ainsi que de type bipolaire a heterojonction (TBH) a base de silicium-germanium (SiGe). Dans un premier chapitre nous rappelons les caracteristiques et proprietes essentielles des sources de bruit en exces que l'on rencontre generalement dans ce type de composants et proposons une description des bancs de mesure de bruit mis en oeuvre. Dans les deuxieme et troisieme chapitres, nous proposons une analyse detaillee de l'evolution du bruit observe en fonction de la frequence, de la polarisation, et de la geometrie sur des HEMTs des deux familles technologiques SiGe et GaN. Nous avons en particulier etudie les deux generateurs de bruit en courant en entree et en sortie respectivement iG et iD ainsi que leur correlation. Ceci nous a permis, en nous appuyant aussi sur l'analyse des caracteristiques statiques des transistors, d'identifier les diverses sources de bruit en exces presentes dans ces composants et de faire des hypotheses sur leurs origines. Le dernier chapitre est consacre aux TBHs a base de SiGe. Dans une premiere partie nous etablissons comment varie le bruit basse frequence de TBHs, fabriques par un premier constructeur, en fonction de la polarisation, de la geometrie et de la fraction molaire de germanium. Dans une seconde partie nous mettons en evidence, d'apres nos observations effectuees sur des TBHs fabriques par un second constructeur, l'impact important sur le bruit BF de stress thermiques appliques sur ce type de composants.

The present work is dedicated to the development of high performance integrated circuits for wireless communications, by acting of three different levels: technologies, devices, and circuits. Silicon-on-Insulator (SOI) CMOS technology is used in the frame of this work. Micromachining technologies are also investigated for the fabrication of three-dimensional tunable capacitors. The reliability of micromachined thin-film devices is improved by the coating of silanes in both liquid- and vapor-phases. Since in telecommunication applications, distortion is responsible for the generation of spurious frequency bands, the linearity behavior of different SOI transistors is analyzed. The validity range of the existing low-frequency nonlinear characterization methods is discussed. New simple techniques valid at both low- and high-frequencies, are provided, based on the integral function method and on the Volterra series. Finally, the design of a crucial nonlinear circuit, the voltage-controlled oscillator, is introduced. The describing function formalism is used to evaluate the oscillation amplitude and is embedded in a design methodology. The frequency tuning by SOI varactors is analyzed in both small- and large-signal regimes.

This thesis presents the analysis, design and characterization of an integrated high-frequency phase-locked loop (PLL) frequency multiplier. The frequency multiplier is novel in its use of a low multiplication factor of 4 and a fully differential topology for rejection of common mode interference signals. The PLL is composed of a voltage controlled oscillator (VCO), injection-locked frequency divider (ILFD) for the first divide-by-two stage, a static master-slave flip-flop (MSFF) divider for the second divide-by-two stage and a Gilbert cell mixer phase detector (PD). The circuit has been fabricated using a standard CMOS 0.18-um process based on its relatively low cost and ready availability. The PLL frequency multiplier generates an output signal at 26 GHz and is the highest operational frequency PLL in the technology node reported to date. Time domain phase plane analysis is used for prediction of PLL locking range based on initial conditions of phase and frequency offsets. Tracking range of the PLL is limited by the inherent narrow locking range of the ILFD, and is confirmed via experimental results. The performance benefits of the fully differential PLL are experimentally confirmed by the injection of differential- and common-mode interfering signals at the VCO control lines. A comparison of the common- and differential-mode modulation indices reveals that a common mode rejection ratio (CMRR) of greater than 20 dB is possible for carrier offset frequencies of less than 1 MHz. Closed-loop frequency domain transfer functions are used for prediction of the PLL phase noise response, with the PLL being dominated by the reference and VCO phase noise contributions. Regions of dominant phase noise contributions are presented and correlated to the overall PLL phase noise performance. Experimental verifications display good agreement and confirm the usefulness of the techniques for PLL performance prediction. The PLL clock multiplier has an operational output frequency of 26.204 to 26.796 GHz and a maximum output frequency step of 16 MHz. Measured phase noise at 1 MHz offset from the carrier is -103.9 dBc/Hz. The PLL clock multiplier core circuit (VCO/ILFD/MSFF Divider/PD) consumes 186 mW of combined power from 2.8 and 4.3 V DC rails. / Thesis (Ph.D, Electrical & Computer Engineering) -- Queen's University, 2009-04-24 11:31:35.384

Αντικείμενο της παρούσας διδακτορικής διατριβής είναι η μελέτη και ο σχεδιασμός καινοτόμων αλγορίθμων φυσικού επιπέδου σε ασύρματα συστήματα επικοινωνίας που χρησιμοποιούν διαμόρφωση με πολύπλεξη συχνότητας ορθογωνίων φερουσών (Orthogonal Frequency Division Multiplexing - OFDM). Η έρευνα επικεντρώθηκε σε δύο κατηγορίες προβλημάτων, στον σχεδιασμό αλγορίθμων προσαρμοστικής διαμόρφωσης καθώς και αλγορίθμων αντιμετώπισης ισχυρού θορύβου φάσης. Αναπτύχθηκαν αλγόριθμοι εκτίμησης φάσης με γραμμική πολυπλοκότητα, μέσω ενός καινούργιου εναλλακτικού μοντέλου περιγραφής του συστήματος. Το μοντέλο αυτό επιτρέπει την επέκταση των κλασικών αλγορίθμων εκτίμησης της κοινής φάσης με στόχο την εκτίμηση του συνολικού διανύσματος θορύβου φάσης. Επιπλέον, η τεχνική διαγώνιας φόρτωσης (diagonal-loading) προσαρμόστηκε κατάλληλα για τη βελτίωση σύγκλισης της προτεινόμενης λύσης. Τέλος, προτάθηκε και αξιολογήθηκε ένα συνολικό σύστημα OFDM όπου η εκτίμηση του καναλιού, της διαταραχής φάσης και των δεδομένων βασίζονται στο κριτήριο ελαχίστων τετραγώνων, διατηρώντας έτσι τη συνολική πολυπλοκότητα σε χαμηλά επίπεδα. Στο πλαίσιο του σχεδιασμού αλγορίθμων προσαρμοστικής διαμόρφωσης προτείνεται ένα γενικό μοντέλο περιγραφής απόδοσης συστήματος ικανό να περιγράψει τα αναπτυσσόμενα πρωτόκολλα μετάδοσης. Η πρόταση αυτή εντάσσεται στην οικογένεια των τεχνικών ισοδύναμης σηματοθορυβικής απεικόνισης (Εffective SNR Μapping - ESM). Χρησιμοποιώντας τις τεχνικές ESM και κατάλληλους περιορισμούς στην παραμετροποίηση των μεταβλητών μετάδοσης, αναπτύχθηκαν αλγόριθμοι προσαρμοστικής διαμόρφωσης χαμηλής πολυπλοκότητας που ικανοποιούν διαφορετικά κριτήρια βελτιστοποίησης. Επιπρόσθετα, προτείνεται ένα γενικό πλαίσιο για τον σχεδιασμό αλγορίθμων προσαρμοστικής διαμόρφωσης, χρησιμοποιώντας προσεγγιστικά μοντέλα απόδοσης. Ορίστηκαν οι κατάλληλες μετρικές για την ποσοτικοποίηση της σπατάλης ενέργειας που επιφέρει η χρήση προσεγγιστικών μοντέλων. Μελετήθηκε η επίδραση της καθυστέρησης ανατροφοδότησης πληροφορίας καναλιού στους αλγορίθμους και παρήχθησαν κατάλληλα μοντέλα περιγραφής απόδοσης που συμπεριλαμβάνουν το χρόνο καθυστέρησης. Το συνολικό αποτέλεσμα της εργασίας είναι αλγόριθμοι που καταφέρνουν υψηλή απόδοση συστήματος, με χαμηλή πολυπλοκότητα, κάτι το οποίο τους κάνει υλοποιήσιμους σε ρεαλιστικά συστήματα. / The objective of this thesis is to study and develop novel, low complexity physical layer algorithms for Orthogonal Frequency Division Multiplexing (OFDM) based communication systems. The study aims at two algorithmic categories, namely adaptive modulation and coding and compensation of severe phase noise (PHN) errors. A parameterized windowed least-squares (WLS) decision directed phase error estimator is proposed via proper (alternative) system modeling, applied to both channel estimation and data detection stage in OFDM systems. The window is optimized so as to minimize the post-compensation error variance (PCEV) of the residual phase, analytically computed for arbitrary PHN and frequency offset (FO) models. Closed-form expressions for near-optimal windows are derived for zero-mean FO, Wiener and first-order autoregressive PHN models, respectively. Furthermore, the diagonal-loading approach is properly employed, initially proposed for providing robustness to a general class of estimators in the presence of model mismatch, to enhance convergence of the iterative estimation scheme, in those high-SNR regions where the effect of data decision errors dominates performance. In the proposed OFDM scheme, channel, IFO estimation and data equalization are also based on the LS criterion, thus keeping the overall system complexity low. A generic performance description model is proposed and used for AMC algorithmic design, capable of describing most of current and under preparation communication protocols. This model proposition is incorporated to a larger family of performance modelling techniques named Effective SNR Mapping techniques (ESM). Using the ESM techniques and proper parameter adaptation constraints, a number of low-complexity AMC algorithms are developed under a chosen set of optimization scenarios. A framework for the design of AMC algorithms using approximate performance description models is proposed. Specific bounds are derived for quantifying the power loss when using approximate models. The effect of outdated channel state information is also studied by statistically characterizing the effective SNR at the receiver. This description allows parameter adaptation under mobility scenarios. The main value of this collective procedure is the development of low complexity- high performance algorithms, implementable on pragmatic OFDM systems.

[pt] As características do canal rádio móvel são essenciais ao desenvolvimento de equipamentos e sistemas modernos de telecomunicações sem fio. Para os ambientes nos quais o sistemas operarão, o conhecimento dos principais parâmetros do canal em banda larga é obtido através do uso do conjunto formado por um equipamento transmissor e outro equipamento receptor com suas respectivas antenas. A este conjunto transmissor e receptor atribui-se o nome de sonda. Existem diversas tecnologias sobre as quais as sondas são projetadas e construídas. Em particular mencionam-se as técnicas STDCC (swept time-delay cross-correlation), o Filtro Casado e o OFDM (orthogonal frequency-division multiplexing). Esta tese compara, por simulação, o desempenho de sondas que utilizam estas três técnicas. São propostas alterações nos métodos Filtro Casado e OFDM, de forma que estes proporcionem resultados mais precisos. Além disto, são estudadas imperfeições em dispositivos comuns a todas elas e comparadas sua influência sobre a qualidade das estimações, de forma isolada e combinada. Para o amplificador de potência é considerado o seu principal fator de degradação: suas não linearidades. Para o oscilador local existente no receptor é analisada a contribuição do ruído de fase. O ruído térmico, sempre presente à entrada do receptor em qualquer situação, é variado em uma extensa faixa de valores e o seu efeito sobre a precisão de cada método é analisado. Os resultados obtidos são apresentados na forma de tabelas e gráficos representando, diretamente, o resultado da comparação com o canal de referência ou por meio dos indicadores erro RMS e desvio padrão. / [en] The mobile radio channel characterization is essential to the development of modern wireless telecommunication equipment and systems. The main wideband channel parameters of the environments where these systems will operate are collected by the use of a set comprising a transmitter, a receiver and an aerial system. This set is named sounder. There are many techniques used to project and implement these sounders, such as STDCC (Swept Time-Delay Cross-Correlation), Matched Filter and OFDM (Orthogonal Frequency-Division Multiplexing). This thesis compares, by means of computer simulations, the performance of these three techniques. Some changes are proposed on the Matched Filter and OFDM methods to reach more precise results. Moreover, imperfections in common devices used by all sounders are studied, both independently and jointly, and the impact over the precision of channel estimations is analyzed. The main degradation factor of power amplifiers, which are the nonlinearities, was also considered, as well as the contribution of the phase noise in the receiver local oscillator. The effect of the thermal noise, always present on the receiver input, was also considered, over a large range of values. The results are presented by diagrams and tables showing results of comparisons with a reference channel or by mean of RMS errors and standard deviations.

La vitesse des liens séries haut débit (USB, SATA, PCI-express, etc.) a atteint les multi-gigabits par seconde, et continue à augmenter. Deux des principaux paramètres électriques utilisés pour caractériser les performances des SerDes sont la gigue transmis à un niveau de taux d’erreur donné et la capacité du récepteur à suivre la gigue à un taux d’erreur donné.Modéliser le bruit de phase des différents components du SerDes, et extraire la gigue temporelle pour la décomposer, aideraient les ingénieurs en conception de circuits à atteindre les meilleurs résultats pour les futures versions des SerDes. Générer des patterns de gigue synthétiques de bruits blancs ou colorés permettrait de mieux analyser les effets de la gigue dans le système pendant la phase de vérification.La boucle d’asservissement de phase est un des contributeurs de la gigue d’horloge aléatoire et déterministe à l’intérieur du système. Cette thèse présente une méthode pour modéliser la boucle d’asservissement de phase avec injection du bruit de phase et estimation de la gigue temporelle. Un modèle dans le domaine temporel en incluant les effets de non-linéarité de la boucle a été créé pour estimer cette gigue. Une nouvelle méthode pour générer des patterns synthétiques de gigue avec une distribution Gaussienne à partir de profils de bruit de phase coloré a été proposée.Les standards spécifient des budgets séparés de gigue aléatoire et déterministe. Pour décomposer la gigue de la sortie de la boucle d’asservissement de phase (ou la gigue généré par la méthode présentée), une nouvelle technique pour analyser et décomposer la gigue a été proposée. Les résultats de modélisation corrèlent bien avec les mesures et cette technique aidera les ingénieurs de conception à identifier et quantifier proprement les sources de la gigue ainsi que leurs impacts dans les systèmes SerDes.Nous avons développé une méthode, pour spécifier la boucle d’asservissement de phase en termes de bruit de phase. Cette méthode est applicable à tout standard (USB, SATA, PCIe, …) et définit les profils de bruits de4phases pour les différentes parties de la boucle d’asservissement de phase, pour s’assurer que les requis des standards sont satisfaits en termes de gigue. Ces modèles nous ont également permis de générer les spécifications de la PLL, pour des standards différents. / Bit rates of high speed serial links (USB, SATA, PCI-express, etc.) have reached the multi-gigabits per second, and continue to increase. Two of the major electrical parameters used to characterize SerDes Integrated Circuit performance are the transmitted jitter at a given bit error rate (BER) and the receiver capacity to track jitter at a given BER.Modeling the phase noise of the different SerDes components, extracting the time jitter and decomposing it, would help designers to achieve desired Figure of Merit (FoM) for future SerDes versions. Generating white and colored noise synthetic jitter patterns would allow to better analyze the effect of jitter in a system for design verification.The phase locked loop (PLL) is one of the contributors of clock random and periodic jitter inside the system. This thesis presents a method for modeling the PLL with phase noise injection and estimating the time domain jitter. A time domain model including PLL loop nonlinearities is created in order to estimate jitter. A novel method for generating Gaussian distribution synthetic jitter patterns from colored noise profiles is also proposed.The Standard Organizations specify random and deterministic jitter budgets. In order to decompose the PLL output jitter (or the generated jitter from the proposed method), a new technique for jitter analysis and decomposition is proposed. Modeling simulation results correlate well with measurements and this technique will help designers to properly identify and quantify the sources of deterministic jitter and their impact on the SerDes system.We have developed a method, for specifying PLLs in terms of Phase Noise. This method works for any standard (USB, SATA, PCIe, …), and defines Phase noise profiles of the different parts of the PLL, in order to be sure that the standard requirements are satisfied in terms of Jitter.

This research looks into the design of an integrated in-phase/quadrature (I/Q) VCO operating at 5 GHz. The goal is to design a phase shifter that is implemented at the LO used for RF up conversion. The target application for the phase shifter is towards phased array antennas operating at 5 GHz. Instead of designing multiple VCOs that each deliver a variety of phases, two identical LC-VCOs are coupled together to oscillate at the same frequency and deliver four outputs that are 90 ° out of phase. By varying the amplitudes of the in-phase and quadrature signals independently using VGAs before adding them together, a resultant out-of-phase signal is obtained. A number of independently variable out-of-phase signals can be obtained from these 90 ° out-of-phase signals and this technique is better known as the vector sum method of phase shifting. Control signals to the inputs of the VGAs required to obtain 22.5 ° phase shifts were designed from simulations and are generated using 16-bit DACs. The design is implemented and manufactured using a 0.35 µm SiGe BiCMOS process and the complete prototype IC occupies an area of 2.65 × 2.65 mm2. The I/Q VCO with 360 ° variable phase outputs occupies 1.10 × 0.85 mm2 of chip area and the 16-bit DAC along with its decoding circuitry occupies 0.41 × 0.13 mm2 of chip area. The manufactured quadrature VCO was found to oscillate between 4.12 ~ 4.74 GHz and consumes 23.1 mW from a 3.3 V supply without its buffer circuitry. A maximum phase noise of -78.5 dBc / Hz at a 100 kHz offset and -108.17 dBc / Hz at a 1 MHz offset was measured and the minimum VCO figure of merit is 157.8 dBc / Hz. The output voltages of the 16 bit DAC are within 3.5 % of the design specifications. When the phase shifter is controlled by the 16 DAC signals, the maximum measured phase error of the phase shifter is lower than 10 %. / Dissertation (MEng)--University of Pretoria, 2009. / Electrical, Electronic and Computer Engineering / unrestricted