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This thesis deals with the main aspects in chemical vapordeposition (CVD) of silicon (Si) and silicon-germanium (Si1-xGex) films for high-speed bipolar transistors.In situdoping of polycrystalline silicon (poly-Si)using phosphine (PH3) and disilane (Si2H6) in a low-pressure CVD reactor was investigated toestablish a poly-Si emitter fabrication process. The growthkinetics and P incorporation was studied for amorphous Si filmgrowth. Hydrogen (H) incorporated in the as-deposited films wasrelated to growth kinetics and the energy for H2desorption was extracted. Film properties such asresistivity, mobility, carrier concentration and grain growthwere studied after crystallization using either furnaceannealing or rapid thermal annealing (RTA). In order tointegrate an epitaxial base, non-selective epitaxial growth(NSEG) of Si and SiGe in a lamp-heated single-waferreduced-pressure CVD reactor was examined. The growth kineticsfor Si epitaxy and poly-Si deposition showed a differentdependence on the deposition conditions i.e. temperature andpressure. The growth rate difference was mainly due to growthkinetics rather than wafer surface emissivity effects. However,it was observed that the growth rate for Si epitaxy and poly-Sideposition was varying during growth and the time-dependencewas attributed to wafer surface emissivity variations. A modelto describe the emissivity effects was established, taking intoconsideration kinetics and the reactor heating mechanisms suchas heat absorption, emission andconduction. Growth ratevariations in opening of different sizes (local loading) andfor different oxide surface coverage (global loading) wereinvestigated. No local loading effects were observed, whileglobal loading effects were attributed to chemical as well astemperature effects. Finally, misfit dislocations formed in theSiGe epitaxy during NSEG were found to originate from theinterface between the epitaxial and polycrystalline regions.The dislocations tended to propagate across the activearea. <b>Keywords:</b>chemical vapor deposition (CVD), bipolarjunction transistor (BJT), heterojunction bipolar transistor(HBT), silicon-germanium (SiGe), epitaxy, poly-Si emitter,in situdoping, non-selective epitaxy (NSEG), loadingeffect, emissivity effect

A wide variety of novel complementary-metal-oxide-semiconductor (CMOS) devices that are strong contenders for future high-speed and low-noise RF circuits have been evaluated by means of static electrical measurements and low-frequency noise characterizations in this thesis. These novel field-effect transistors (FETs) include (i) compressively strained SiGe channel pMOSFETs, (ii) tensile strained Si nMOSFETs, (iii) MOSFETs with high-k gate dielectrics, (iv) metal gate and (v) silicon-on-insulator (SOI) devices. The low-frequency noise was comprehensively characterized for different types of operating conditions where the gate and bulk terminal voltages were varied. Detailed studies were made of the relationship between the 1/f noise and the device architecture, strain, device geometry, location of the conduction path, surface cleaning, gate oxide charges and traps, water vapour annealing, carrier mobility and other technological factors. The locations of the dominant noise sources as well as their physical mechanisms were investigated. Model parameters and physical properties were extracted and compared. Several important new insights and refinements of the existing 1/f noise theories and models were also suggested and analyzed. The continuing trend of miniaturizing device sizes and building devices with more advanced architectures and complex materials can lead to escalating 1/f noise levels, which degrades the signal-to-noise (SNR) ratio in electronic circuits. For example, the 1/f noise of some critical transistors in a radio receiver may ultimately limit the information capacity of the communication system. Therefore, analyzing electronic devices in order to control and find ways to diminish the 1/f noise is a very important and challenging research subject. We present compelling evidence that the 1/f noise is affected by the distance of the conduction channel from the gate oxide/semiconductor substrate interface, or alternatively the vertical electric field pushing the carriers towards the gate oxide. The location of the conduction channel can be varied by the voltage on the bulk and gate terminals as well by device engineering. Devices with a buried channel architecture such as buried SiGe channel pMOSFETs and accumulation mode MOSFETs on SOI show significantly reduced 1/f noise. The same observation is made when the substrate/source junction is forward biased which decreases the vertical electric field in the channel and increases the inversion layer separation from the gate oxide interface. A 1/f noise model based on mobility fluctuations originating from the scattering of electrons with phonons or surface roughness was proposed. Materials with a high dielectric constant (high-k) is necessary to replace the conventional SiO2 as gate dielectrics in the future in order to maintain a low leakage current at the same time as the capacitance of the gate dielectrics is scaled up. In this work, we have made some of the very first examinations of 1/f noise in MOSFETs with high-k structures composed by layers of HfO2, HfAlOx and Al2O3. The 1/f noise level was found to be elevated (up to 3 orders of magnitude) in the MOSFETs with high-k gate dielectrics compared to the reference devices with SiO2. The reason behind the higher 1/f noise is a high density of traps in the high-k stacks and increased mobility fluctuation noise, the latter possibly due to noise generation in the electron-phonon scattering that originates from remote phonon modes in the high-k. The combination of a TiN metal gate, HfAlOx and a compressively strained surface SiGe channel was found to be superior in terms of both high mobility and low 1/f noise. / QC 20100928

The objective of this research is to explore the possibilities of developing transmit/receive (T/R) modules using silicon-germanium (SiGe) heterojunction bipolar transistor (HBT) BiCMOS technology to integrate with organic liquid crystal polymer (LCP) packages for the next-generation phased-array radar system. The T/R module requirements are low power, compact, lightweight, low cost, high performance, and high reliability. All these requirements have provided a very strong motivation for developing fully monolithic T/R modules. SiGe HBT BiCMOS technology is an excellent candidate to integrate all the RF circuit blocks on the T/R module into a single die and thus, reducing the overall cost and size of the phase-array radar system. In addition, this research also investigates the effects and the modeling issues of LCP package on the SiGe circuits at X-band.

Design techniques and procedures to improve performances of radio-frequency and millimeter-wave front-end integrated circuits were developed. Power amplifiers for high data-rate wireless communication applications were designed using CMOS technology employing a novel device resizing and concurrent power-combining technique to implement a multi-mode operation. Comprehensive analysis on the efficiency degradation effect of multi-input-single-output combining transformers with idle input terminals was performed. The proposed discrete resizing and power-combining technique effectively enhanced the efficiency of a linear CMOS power amplifier at back-off power levels. In addition, a novel power-combining transformer that is suitable to generate multi-watt-level output power was proposed and implemented. Employing the proposed power-combining transformer, a high-power linear CMOS power amplifier was designed. Furthermore, receiver building blocks such as a low-noise amplifier, a down-conversion mixer, and a passive balun were implemented using SiGe technology for W-band applications.

This thesis presents an efficient self-consistent Hybrid Spectral Ray Tracing (HSRT) technique for analysis and design of multi-scale sub-millimeter wave problems, where sub-wavelength features are modeled using rigorous methods, and complex structures with dimensions in the order of tens or even hundreds of wavelengths are modeled by asymptotic methods. Quasi-optical devices are used in imaging arrays for sub-millimeter and terahertz applications, THz time-domain spectroscopy (THz-TDS), high-speed wireless communications, and space applications to couple terahertz radiation from space to a hot electron bolometer. These devices and structures, as physically small they have become, are very large in terms of the wavelength of the driving quasi-optical sources and may have dimension in the tens or even hundreds of wavelengths. Simulation and design optimization of these devices and structures is an extremely challenging electromagnetic problem. The analysis of complex electrically large unbounded wave structures using rigorous methods such as method of moments (MoM), finite element method (FEM), and finite difference time domain (FDTD) method can become almost impossible due to the need for large computational resources. Asymptotic high-frequency techniques are used for analysis of electrically large quasi-optical systems and hybrid methods for solving multi-scale problems. Spectral Ray Tracing (SRT) has a number of unique advantages as a candidate for hybridization. The SRT method has the advantages of Spectral Theory of Diffraction (STD). STD can model reflection, refraction and diffraction of an arbitrary wave incident on the complex structure, which is not the case for diffraction theories such as Geometrical Theory of Diffraction (GTD), Uniform theory of Diffraction (UTD) and Uniform Asymptotic Theory (UAT). By including complex rays, SRT can effectively analyze both near-fields and far-fields accurately with minimal approximations. In this thesis, a novel matrix representation of SRT is presented that uses only one spectral integration per observation point and applied to modeling a hemispherical and hyper-hemispherical lens. The hybridization of SRT with commercially available FEM and MoM software is proposed in this work to solve the complexity of multi-scale analysis. This yields a computationally efficient self-consistent HSRT algorithm. Various arrangements of the Hybrid SRT method such as FEM-SRT, and MoM-SRT, are investigated and validated through comparison of radiation patterns with Ansoft HFSS for the FEM method, FEKO for MoM, Multi-level Fast Multipole Method (MLFMM) and physical optics. For that a bow-tie terahertz antenna backed by hyper-hemispherical silicon lens, an on-chip planar dipole fabricated in SiGe:C BiCMOS technology and attached to a hyper-hemispherical silicon lens and a double-slot antenna backed by silica lens will be used as sample structures to be analyzed using the HSRT. Computational performance (memory requirement, CPU/GPU time) of developed algorithm is compared to other methods in commercially available software. It is shown that the MoM-SRT, in its present implementation, is more accurate than MoM-PO but comparable in speed. However, as shown in this thesis, MoM-SRT can take advantage of parallel processing and GPU. The HSRT algorithm is applied to simulation of on-chip dipole antenna backed by Silicon lens and integrated with a 180-GHz VCO and radiation pattern compared with measurements. The radiation pattern is measured in a quasi-optical configuration using a power detector. In addition, it is shown that the matrix formulation of SRT and HSRT are promising approaches for solving complex electrically large problems with high accuracy. This thesis also expounds on new measurement setup specifically developed for measuring integrated antennas, radiation pattern and gain of the embedded on-chip antenna in the mmW/ terahertz range. In this method, the radiation pattern is first measured in a quasi-optical configuration using a power detector. Subsequently, the radiated power is estimated form the integration over the radiation pattern. Finally, the antenna gain is obtained from the measurement of a two-antenna system.

As Si-manufacturing compatible SiGe HBTs are making rapid in-roads into RF through mm-wave circuit applications, with performance levels steadily marching upward, the use of these devices under extreme environment conditions are being studied extensively. In this work, test structures of SiGe HBTs were designed and put into extremely low temperatures, and a new negative differential resistance effect and a novel collector current kink effect are investigated in the cryogenically-operated SiGe HBTs. Theory based on an enhanced positive feedback mechanism associated with heterojunction barrier effect at deep cryogenic temperatures is proposed. The accumulated charge induced by the barrier effect acts at low temperatures to enhance the total collector current, indirectly producing both phenomena. This theory is confirmed using calibrated 2-D DESSIS simulations over temperature. These unique cryogenic effects also have significant impact on the ac performance of SiGe HBTs operating at high-injection. Technology evolution plays an important role in determining the magnitude of the observed phenomena, and the scaling implications are addressed. Circuit implication is discussed.

A comprehensive study of the High-pass/Low-pass topology has been performed, increasing the understanding of error sources arising from bit layout issues and fabrication tolerances. This included a detailed analysis of error sources in monolithic microwave phase shifters due to device size limitations, inductor parasitics, loading effects, and non-ideal switches. Each component utilized in the implementation of a monolithic high-low pass phase shifter was analyzed, with its influence on phase behavior shown in detail. An emphasis was placed on the net impact on absolute phase variation, which is critical to the system performance of a phased array radar system. The design of the individual phase shifter filter sections, and the influence of bit ordering on overall performance was also addressed. A variety of X-band four- and five-bit phase shifters were fabricated in a 200 GHz SiGe HBT BiCMOS technology platform, and further served to validate the analysis and design methodology. The SiGe phase shifter can be successfully incorporated into a single-chip T/R module forming a system-on-a-chip (SoC). Reduction in the physical size of transmission lines was shown to be a possibility with spinel magnetic nanoparticle films. The signal transmission properties of phase lines treated with nanoparticle thin films were examined, showing the potential for significant size reduction in both delay line and High-pass/Low-pass phase topologies. Wide-band, low-loss, and near-hermetic packaging techniques for RF MEMS devices were presented. A thermal compression bonding technique compatible with standard IC fabrication techniques was shown, that uses a low temperature thermal compression bonding method that avoids plastic deformations of the MEMS membrane. Ultimately, a system-on-a-package (SoP) approach was demonstrated that utilized packaged RF MEMS switches to maintain the performance of the SiGe phase shifter with much lower loss. The extremely competitive performance of the MEMS-based High-pass/Low-pass phase shifter, despite the lack of the extensive toolkits and commercial fabrication facilities employed with the active-based SiGe phase shifters, confirms both the effectiveness of the detailed phase error analysis presented in this work and the robust nature of the High-pass/Low-pass topology.

This thesis presents an overview of the simulation, design, and measurement of state-of-the-art Silicon-Germanium Hetro-Junction Bipolar Transistor (SiGe HBT) low-noise amplifiers (LNAs). The LNA design trade-off space is presented and methods for achieving an optimized design are discussed. In Chapter 1, we review the importance of LNAs and the benefits of SiGe HBT technology in high frequency amplifier design. Chapter 2 introduces LNA design and basic noise theory. A graphical LNA design approach is presented to aid in understanding of the high-frequency LNA design process. Chapter 3 presents an LNA design optimization method for power constrained applications. Measured results using this design technique are highlighted and shown to have record performance. Lastly, in Chapter 4, we highlight cryogenic noise performance and present measured results from cryogenic operation of SiGe HBT LNAs. We demonstrate in this thesis that SiGe HBT LNAs have the capability to meet the demanding needs for next generation wireless systems. The aim of the analysis presented herein is to provide designers with the fundamentals of designing SiGe HBT LNAs through relevant design examples and measured results.

This work investigates the challenges associated with designing silicon-germanium (SiGe) analog and mixed-signal circuits capable of operating reliably in extreme environment conditions. Three extreme environment operational conditions, namely, operation over an extremely wide temperature range, operation at extremely low temperatures, and operation under radiation exposure, are considered. As a representative for critical analog building blocks, bandgap voltage reference (BGR) circuit is chosen. Several architectures of the BGRs are implemented in two SiGe BiCMOS technology platforms. The effects of wide-temperature operation, deep cryogenic operation, and proton and x-ray irradiation on the performance of BGRs are investigated. The impact of Ge profile shape on BGR's wide-temperature performance is also addressed. Single-event transient response of the BGR circuit is studied through microbeam experiments. In addition, proton radiation response of high-voltage transistors, implemented in a low-voltage SiGe platform, is investigated. A platform consisting of a high-speed comparator, digital-to-analog (DAC) converter, and a high-speed flash analog-to-digital (ADC) converter is designed to facilitate the evaluation of the extreme environment capabilities of SiGe data converters. Room temperature measurement results are presented and predictions on how temperature and radiation will impact their key electrical properties are provided.