The motivation behind this work is to target the demand for high-speed medium-resolution ADCs for satellite communication systems. An 8-bit, 12.5GS/s folding-interpolating ADC was designed in 0.25µm, 190GHz SiGe BiCMOS technology from IHP. The ADC consists of a THA, a reference resistor ladder, folding amplifiers, an interpolating resistor string, a comparator array, a digital encoder, a coarse quantizer and a bit synchronizer. Post-layout simulation results of the ADC verify that its performance meets all the required specifications. By comparison to other high-speed ADCs, implemented in SiGe technologies, the present design features the highest sampling rate for 8-bit resolution ADCs to date with a good FOM (12.9pJ/conversion). The THA and the comparator were implemented experimentally and characterized to verify their performance and to ascertain the possibility of implementing the complete ADC. The experimental results meet the expected specifications and indicate that both circuits are suitable for the implementation of the ADC.

Depuis ces dernières années, parmi tous les composants de puissance, l’IGBT (Transistor Bipolaire à Grille Isolée) occupe une place prépondérante, On le retrouve dans une multitude d’applications et il est devenu un composant de référence de l’électronique de puissance. Dans cette thèse, nous nous intéresserons au fonctionnement de l’IGBT en conditions thermiques et électriques extrêmes. À l'aide de la simulation physique bidimensionnelle d'un modèle d'IGBT de type Punch Through à structure de grille en tranchée, on s'intéressera plus particulièrement aux limites des aires de sécurité, et plus précisément aux mécanismes qui peuvent amener à la défaillance du composant. Une étude expérimentale présentera le comportement de différentes structures d’IGBT dans différents modes de fonctionnement, on traitera plus particulièrement l’influence de la température et de la résistance de grille sur ces modes de fonctionnement. Enfin, une proposition d’amélioration d’IGBT sera développée en simulation mettant en œuvre une couche tampon SiGe. / For these last years, the IGBT (Insulated Gate Bipolar Transistor) has occupied a dominating place comparing to other power components. Used in a multitude of applications, it became the component of reference in power electronics domain. In this thesis, I will be interested in operation of the IGBT in extreme thermal and electrical conditions. Using the simulation of a bi-dimensional physical model of a Punch Through Trench IGBT, I will be interested more particularly in the limits of the SOA (Safe Operating Area), and more precisely in the mechanisms which can lead to the failure of the component. An experimental study will present the behaviour of various structures of IGBT in various electrical and thermal operating conditions, more particularly the influence of the temperature and the gate resistance. Lastly, a proposal for an improvement of IGBT will be developed in simulation by implementing a layer SiGe in the N+ buffer layer of the IGBT.

The research conducted in this dissertation studies the issues regarding the improvement of phase noise performance in a BiCMOS Silicon Germanium (SiGe) cross-coupled differential-pair voltage controlled oscillator (VCO) in a narrowband application as a result of a tail-current shaping technique. With this technique, low-frequency noise components are reduced by increasing the signal amplitude without consuming additional power, and its effect on overall phase noise performance is evaluated. The research investigates effects of the tail-current as a main contributor to phase noise, and also other effects that may influence the phase noise performance like inductor geometry and placement, transistor sizing, and the gain of the oscillator. The hypothesis is verified through design in a standard 0.35 μm BiCMOS process supplied by Austriamicrosystems (AMS). Several VCOs are fabricated on-chip to serve for a comparison and verify that the employment of tail-current shaping does improve phase noise performance. The results are then compared with mathematical models and simulated results, to confirm the hypothesis. Simulation results provided a 3.3 dBc/Hz improvement from -105.3 dBc/Hz to -108.6 dBc/Hz at a 1 MHz offset frequency from the 5 GHz carrier when employing tail-current shaping. The relatively small increase in VCO phase noise performance translates in higher modulation accuracy when used in a transceiver, therefore this increase can be regarded as significant. Parametric analysis provided an additional 1.8 dBc/Hz performance enhancement in phase noise that can be investigated in future works. The power consumption of the simulated VCO is around 6 mW and 4.1 mW for the measured prototype. The circuitry occupies 2.1 mm2 of die area. Copyright / Dissertation (MEng)--University of Pretoria, 2010. / Electrical, Electronic and Computer Engineering / unrestricted

Les études qui seront présentées dans le cadre de cette thèse portent sur le développement et l’optimisation des techniques pour la modélisation compacte des transistors bipolaires à hétérojonction (TBH). Ce type de modélisation est à la base du développement des bibliothèques de composants qu’utilisent les concepteurs lors de la phase de simulation des circuits intégrés. Le but d’une technologie BiCMOS est de pouvoir combiner deux procédés technologiques différents sur une seule et même puce. En plus de limiter le nombre de composants externes, cela permet également une meilleure gestion de la consommation dans les différents blocs digitaux, analogiques et RF. Les applications dites rapides peuvent ainsi profiter du meilleur des composants bipolaires et des transistors CMOS. Le défi est d’autant plus critique dans le cas des applications analogiques/RF puisqu’il est nécessaire de diminuer la puissance consommée tout en maintenant des fréquences de fonctionnement des transistors très élevées. Disposer de modèles compacts précis des transistors utilisés est donc primordial lors de la conception des circuits utilisés pour les applications analogiques et mixtes. Cette précision implique une étude sur un large domaine de tensions d’utilisation et de températures de fonctionnement. De plus, en allant vers des nœuds technologiques de plus en plus avancés, des nouveaux effets physiques se manifestent et doivent être pris en compte dans les équations du modèle. Les règles d’échelle des technologies plus matures doivent ainsi être réexaminées en se basant sur la physique du dispositif. Cette thèse a pour but d’évaluer la faisabilité d’une offre de modèle compact dédiée à la technologie avancée SiGe TBH de chez ST Microelectronics. Le modèle du transistor bipolaire SiGe TBH est présenté en se basant sur le modèle compact récent HICUMversion L2.3x. Grâce aux lois d’échelle introduites et basées sur le dessin même des dimensions du transistor, une simulation précise du comportement électrique et thermique a pu être démontrée.Ceci a été rendu possible grâce à l’utilisation et à l’amélioration des routines et méthodes d’extraction des paramètres du modèle. C’est particulièrement le cas pour la détermination des éléments parasites extrinsèques (résistances et capacités) ainsi que celle du transistor intrinsèque. Finalement, les différentes étapes d’extraction et les méthodes sont présentées, et ont été vérifiées par l’extraction de bibliothèques SPICE sur le TBH NPN Haute-Vitesse de la technologie BiCMOS avancée du noeud 55nm, avec des fréquences de fonctionnement atteignant 320/370GHz de fT = fmax. / The aim of BiCMOS technology is to combine two different process technologies intoa single chip, reducing the number of external components and optimizing power consumptionfor RF, analog and digital parts in one single package. Given the respectivestrengths of HBT and CMOS devices, especially high speed applications benefit fromadvanced BiCMOS processes, that integrate two different technologies.For analog mixed-signal RF and microwave circuitry, the push towards lower powerand higher speed imposes requirements and presents challenges not faced by digitalcircuit designs. Accurate compact device models, predicting device behaviour undera variety of bias as well as ambient temperatures, are crucial for the development oflarge scale circuits and create advanced designs with first-pass success.As technology advances, these models have to cover an increasing number of physicaleffects and model equations have to be continuously re-evaluated and adapted. Likewiseprocess scaling has to be verified and reflected by scaling laws, which are closelyrelated to device physics.This thesis examines the suitability of the model formulation for applicability to production-ready SiGe HBT processes. A derivation of the most recent model formulationimplemented in HICUM version L2.3x, is followed by simulation studies, whichconfirm their agreement with electrical characteristics of high-speed devices. Thefundamental geometry scaling laws, as implemented in the custom-developed modellibrary, are described in detail with a strong link to the specific device architecture.In order to correctly determine the respective model parameters, newly developed andexisting extraction routines have been exercised with recent HBT technology generationsand benchmarked by means of numerical device simulation, where applicable.Especially the extraction of extrinsic elements such as series resistances and parasiticcapacitances were improved along with the substrate network.The extraction steps and methods required to obtain a fully scalable model library wereexercised and presented using measured data from a recent industry-leading 55nmSiGe BiCMOS process, reaching switching speeds in excess of 300GHz. Finally theextracted model card was verified for the respective technology.

State-of-the-art SiGe BiCMOS technologies leverage the maturity of deep-submicron silicon CMOS processing with bandgap-engineered SiGe HBTs in a single platform that is suitable for a wide variety of high performance and highly-integrated applications (e.g., system-on-chip (SOC), system-in-package (SiP)). Due to their bandgap-engineered base, SiGe HBTs are also naturally suited for cryogenic electronics and have the potential to replace the costly de facto technologies of choice (e.g., Gallium-Arsenide (GaAs) and Indium-Phosphide (InP)) in many cryogenic applications such as radio astronomy. This work investigates the response of mixed-signal circuits (both RF and analog circuits) when operating in extreme environments, in particular, at cryogenic temperatures and in radiation-rich environments. The ultimate goal of this work is to attempt to fill the existing gap in knowledge on the cryogenic and radiation response (both single event transients (SETs) and total ionization dose (TID)) of specific RF and analog circuit blocks (i.e., RF switches and voltage references). The design approach for different RF switch topologies and voltage references circuits are presented. Standalone Field Effect Transistors (FET) and SiGe HBTs test structures were also characterized and the results are provided to aid in the analysis and understanding of the underlying mechanisms that impact the circuits' response. Radiation mitigation strategies to counterbalance the damaging effects are investigated. A comprehensive study on the impact of cryogenic temperatures on the RF linearity of SiGe HBTs fabricated in a new 4th-generation, 90 nm SiGe BiCMOS technology is also presented.

Le travail presente dans ce memoire a pour objet principal l'etude des phenomenes de bruit du fond electrique basse frequence dans des transistors pour applications micro-ondes de type effet de champ (HEMT) sur SiGe et GaN ainsi que de type bipolaire a heterojonction (TBH) a base de silicium-germanium (SiGe). Dans un premier chapitre nous rappelons les caracteristiques et proprietes essentielles des sources de bruit en exces que l'on rencontre generalement dans ce type de composants et proposons une description des bancs de mesure de bruit mis en oeuvre. Dans les deuxieme et troisieme chapitres, nous proposons une analyse detaillee de l'evolution du bruit observe en fonction de la frequence, de la polarisation, et de la geometrie sur des HEMTs des deux familles technologiques SiGe et GaN. Nous avons en particulier etudie les deux generateurs de bruit en courant en entree et en sortie respectivement iG et iD ainsi que leur correlation. Ceci nous a permis, en nous appuyant aussi sur l'analyse des caracteristiques statiques des transistors, d'identifier les diverses sources de bruit en exces presentes dans ces composants et de faire des hypotheses sur leurs origines. Le dernier chapitre est consacre aux TBHs a base de SiGe. Dans une premiere partie nous etablissons comment varie le bruit basse frequence de TBHs, fabriques par un premier constructeur, en fonction de la polarisation, de la geometrie et de la fraction molaire de germanium. Dans une seconde partie nous mettons en evidence, d'apres nos observations effectuees sur des TBHs fabriques par un second constructeur, l'impact important sur le bruit BF de stress thermiques appliques sur ce type de composants.

The objective of the proposed research is to design, implement, and characterize low-cost, lightweight front-end components and subsystems in the microwave domain through innovative packaging architectures for remote sensing applications. Particular emphasis is placed on system-on-package (SoP) solutions implemented in organic substrates as a low-cost alternative to conventional, expensive, rigid, and fragile radio- frequency substrates. To this end, the dielectric properties of organic substrates RT/duroid 5880, 6002 and 6202 are presented from 30 GHz to 70 GHz, covering most of the Ka and V radar bands, giving also a thorough insight on the uncertainty of the microstrip ring resonator method by means of the Monte Carlo uncertainty analysis. Additionally, an ultra-thin, high-power antenna-array technology, with transmit/ receive (T/R) functionality is introduced for mobile applications in the X band. Two lightweight SoP T/R array panels are presented in this work using novel technologies such as Silicon Germanium integrated circuits and microelectromechanical system switches on a hybrid organic package of liquid crystal polymer and RT/duroid 5880LZ. A maximum power of 47 dBm is achieved in a package with a thickness of 1.8 mm without the need of bulky thermal management devices. Finally, to address the thermal limitations of thin-film substrates of interest (liquid crystal polymer, RT/duroid 6002, alumina and Aluminum Nitride), a thermal assessment of microstrip structures is presented in the X band, along with the thermal characterization of the dielectric properties of RT/duroid 6002 from 20 C to 200 C and from 30 GHz to 70 GHz. Additional high-power, X-band technologies presented in this work include: a novel and compact topology for evanescent mode filters, and low-profile Wilkinson power dividers implemented on Aluminum Nitride using Tantalum Nitride thin-film resistors.

This thesis investigates the effects of low temperatures on Silicon Germanium (SiGe) Hterojunction Bipolar Transistors (HBT) BiCMOS technology. A comprehensive set of dc measurements were taken on first, second, third and fourth generation IBM SiGe technology over a range of temperatures (room temperature to 43K for first generation, and room temperature to 15K for the rest). This work is unique in the sense that this sort of comprehensive study of dc characteristics on four SiGe HBT technology generations over a wide range of temperatures has never been done before to the best of the authors knowledge.

The objective of this work is to provide a comprehensive analysis of the small-signal and broadband noise performance of highly scaled silicon-based field-effect transistors (FETs), and develop high-frequency noise models for robust radio frequency (RF) circuit design. An analytical RF noise model is developed and implemented for scaled Si-CMOS devices, using a direct extraction procedure based on the linear two-port noise theory. This research also focuses on investigating the applicability of modern CMOS technologies for extreme environment electronics. A thorough analysis of the DC, small-signal AC, and broadband noise performance of 0.18 um and 130 nm Si-CMOS devices operating at cryogenic temperatures is presented. The room temperature RF noise model is extended to model the high-frequency noise performance of scaled MOSFETs at temperatures down to 77 K and 10 K. Significant performance enhancement at cryogenic temperatures is demonstrated, indicating the suitability of scaled CMOS technologies for low temperature electronics. The hot-carrier reliability of MOSFETs at cryogenic temperatures is investigated and the worst-case gate voltage stress condition is determined. The degradation due to hot-carrier-induced interface-state creation is identified as the dominant degradation mechanism at room temperature down to 77 K. The effect of high-energy proton radiation on the DC, AC, and RF noise performance of 130 nm CMOS devices is studied. The performance degradation is investigated up to an equivalent total dose of 1 Mrad, which represents the worst case condition for many earth-orbiting and planetary missions. The geometric scaling of MOSFETs has been augmented by the introduction of novel FET designs, such as the Si/SiGe MODFETs. A comprehensive characterization and modeling of the small-signal and high-frequency noise performance of highly scaled Si/SiGe n-MODFETs is presented. The effect of gate shot noise is incorporated in the broadband noise model. SiGe MODFETs offer the potential for high-speed and low-voltage operation at high frequencies and hence are attractive devices for future RF and mixed-signal applications. This work advances the state-of-the-art in the understanding and analysis of the RF performance of highly scaled Si-CMOS devices as well as emerging technologies, such as Si/SiGe MODFETs. The key contribution of this dissertation is to provide a robust framework for the systematic characterization, analysis and modeling of the small-signal and RF noise performance of scaled Si-MOSFETs and Si/SiGe MODFETs both for mainstream and extreme-environment applications.

Wireless operation, near-field or far-field, is a core functionality of any mobile or autonomous system. These systems are battery operated or most often utilize energy scavenging as a means of power generation. Limited access to power, expected long and uninterrupted operation, and constrained physical parameters (e.g. weight and size), which limit overall power harvesting capabilities, are factors that outline the importance for innovative low-power approaches and designs in advanced low-power wireless applications. Low-power approaches become especially important for the wireless transceiver, the block in charge of wireless/remote functionality of the system, as this block is usually the most power hungry component in an integrated system-on-chip (SoC). Three such advanced applications with stringent power requirements are examined including space-based exploratory remote sensing probes and their associated radiation effects, millimeter-wave phased-array radar for high-altitude tactical and geological imaging, and implantable biomedical devices (IMDs), leading to the proposal and implementation of low-power wireless solutions for these applications in SiGe BiCMOS and CMOS and platforms.