Integration of optical wireless communications (OWC) within switched-mode power supplies (SMPS) / Although visible light communication(VLC) systems can provide high density links for use with IoT devices, an energy efficient, high rate method of designing a VLC transmitter is still unclear. Present designs for transmitters such as the bias-T, designs with switch manipulation, and interleaved converters are not commercially viable due to costly and complex designs that sacrifice energy efficiency for data rate. A design allowing for efficient, high rate communications, while maintaining a low cost would allow for widespread adoption of this technology. In this thesis, a novel approach of integrating power converters and VLC systems is explored by replacing commutating diodes with LEDs. By leveraging switched-mode power supply(SMPS) structures, the power dissipated within the converter may be harnessed and used for communications. The result is a simple and energy efficient solution capable of high rate links. Simulation and experimental results demonstrate buck and boost SMPS topologies that simultaneously increase energy efficiency and provide communications at SMPS switching rate without increasing component count. / Thesis / Master of Applied Science (MASc)

Switched mode power supplies (SMPS) have found wide spread acceptance in all power processing applications. The design demand is moving towards higher power densities. For reduction in size and weight, it is imperative to process the power at a higher switching frequency. High switching frequency requires soft switching techniques to reduce the switching losses. Several families of soft switching converters have emerged in the past two decades. Analysis and modelling methods have been proposed in relation with these topologies. Active clamp converters are the recently introduced soft switching topologies. Steady state analysis and model of these converters have been reported in literature. This thesis presents a unified equivalent circuit oriented model for the family of active clamp converters. Analytical expressions for DC conversion ratio in terms of pole current and throw voltage are derived for all the DC-DC converters with active clamp. The special feature is that, the conversion ratio exhibits a load dependent drop (IRd), where I is the pole current and Rd is the damping resistance. The damping resistance Rd is a mathematical artifact to represent the voltage loss on account of delay in the turn-on of the active switch. There is no energy loss associated with this load dependent drop. This is conveniently expressed as an appropriate lossless resistance in the equivalent circuit model. The proposed equivalent circuit models are valid for both steady-state and dynamic performance. A spread sheet based design is presented for the basic DC-DC converters with active clamp. A prototype design following the spreadsheet is made. The performance of the same is validated and verified by simulation and measurements. Steady state and dynamic results are presented. The stability criterion for the active clamp converters under current programming is investigated. The same is verified through simulation and validated on a current programmed active clamp converter prototype. The active clamp converters suffer from a few disadvantages: Higher VA ratings of switches, load dependent ZVS performance and increased component count. Several soft switching topologies have been reported in literature. Efficiency improvement and increase in switching frequency are obtained to different degrees. This thesis proposes a new family of soft switching converters. This family of converters switch at constant frequency and maintains the advantages of traditional PWM converters. The proposed topology employs an auxiliary circuit to achieve soft switching. The auxiliary circuit consists of a dependent voltage source, an auxiliary switch, a series diode and a set of resonant elements (Inductor and capacitor). The switching transitions of both the active switch and the auxiliary switch are lossless. The novelty in the proposed circuit is the method of generating the dependent source required to enable zero current switching of the auxiliary switch. The dependent source is realized by a coupled winding in the energy storage inductor or tapped from the energy transfer transformer of non-isolated and isolated converters respectively. The proposed topology is applicable to most of the isolated and non-isolated DC-DC converters. The circuit equations governing the sub-intervals of the converter are expressed in terms of pole current and throw voltage. With such a definition, performance results and the design equations are identical for all types of DC-DC converters. Equivalent circuit models are obtained for the whole family of DC-DC converters. The proposed model is valid for steady state and dynamic performance. Analytical expressions of DC conversion ratio for all topologies, in terms of pole current and throw voltage are derived. The special feature is that, the conversion ratio exhibits a load dependent drop (IRd), where I is the pole current and Rd is the damping resistance. The damping resistance Rd is a mathematical artifact to represent the voltage loss on account of delay in the turn-on of the active switch. There is no energy loss associated with this load dependent drop. This is conveniently expressed as an appropriate lossless resistance in the equivalent circuit model. Design guidelines are established for the whole family of proposed converters; the same are validated through prototype converters.

This Master of Applied Science thesis proposes a new design of low power, power factor corrected (PFC), power supplies. By lifting the hold up time restriction for devices that have a battery built in, the energy storage elements of the converter can be reduced, permitting a small and inexpensive power converter to be built. In addition, a new control technique for controlling cascaded converters is presented, named duty mode control (DMC). Its advantages are shown through simulations. The system was proven using a prototype developed in the laboratory designed for a universal ac input voltage (85 - 265VRMS at 50 - 60Hz) and a 40W output at 12V. It consisted of two interleaved phases sensed and digitally controlled on the isolated side of the converter. The prototype was able to achieve a power factor of greater than 0.98 for all operating conditions, and input harmonic current distortion well below any set of standards.

This Master of Applied Science thesis proposes a new design of low power, power factor corrected (PFC), power supplies. By lifting the hold up time restriction for devices that have a battery built in, the energy storage elements of the converter can be reduced, permitting a small and inexpensive power converter to be built. In addition, a new control technique for controlling cascaded converters is presented, named duty mode control (DMC). Its advantages are shown through simulations. The system was proven using a prototype developed in the laboratory designed for a universal ac input voltage (85 - 265VRMS at 50 - 60Hz) and a 40W output at 12V. It consisted of two interleaved phases sensed and digitally controlled on the isolated side of the converter. The prototype was able to achieve a power factor of greater than 0.98 for all operating conditions, and input harmonic current distortion well below any set of standards.

No description available.

No description available.

Les technologies avancées de semi-conducteur permettent de mettre en œuvre un contrôleur numérique dédié aux convertisseurs à découpage, de faible puissance et de fréquence de découpage élevée sur FPGA et ASIC. Cette thèse vise à proposer des contrôleurs numériques des performances élevées, de faible consommation énergétique et qui peuvent être implémentés facilement. En plus des contrôleurs numériques existants comme PID, RST, tri-mode et par mode de glissement, un nouveau contrôleur numérique (DDP) pour le convertisseur abaisseur de tension est proposé sur le principe de la commande prédictive: il introduit une nouvelle variable de contrôle qui est la position de la largeur d'impulsion permettant de contrôler de façon simultanée le courant dans l'inductance et la tension de sortie. La solution permet une dynamique très rapide en transitoire, aussi bien pour la variation de la charge que pour les changements de tension de référence. Les résultats expérimentaux sur FPGA vérifient les performances de ce contrôleur jusqu'à la fréquence de découpage de 4MHz. Un contrôleur numérique nécessite une modulation numérique de largeur d'impulsion (DPWM). L'approche Sigma-Delta de la DPWM est un bon candidat en ce qui concerne le compromis entre la complexité et les performances. Un guide de conception d'étage Sigma-Delta pour le DPWM est présenté. Une architecture améliorée de traditionnelles 1-1 MASH Sigma-Delta DPWM est synthétisée sans détérioration de la stabilité en boucle fermée ainsi qu'en préservant un coût raisonnable en ressources matérielles. Les résultats expérimentaux sur FPGA vérifient les performances des DPWM proposées en régimes stationnaire et transitoire. Deux ASICs sont portés en CMOS 0,35µm: le contrôleur en tri-mode pour le convertisseur abaisseur de tension et la commande par mode de glissement pour les convertisseurs abaisseur et élévateur de tension. Les bancs de test sont conçus pour conduire à un modèle d'évaluation de consommation énergétique. Pour le contrôleur en tri-mode, la consommation de puissance mesurée est seulement de 24,56mW/MHz lorsque le ratio de temps en régime de repos (stand-by) est 0,7. Les consommations de puissance de command par mode de glissement pour les convertisseurs abaisseur et élévateur de tension sont respectivement de 4,46mW/MHz et 4,79mW/MHz. En utilisant le modèle de puissance, une consommation de la puissance estimée inférieure à 1mW/MHz est envisageable dans des technologies CMOS plus avancées. Comparé aux contrôlés homologues analogiques de l'état de l'art, les prototypes ASICs illustrent la possibilité d'atteindre un rendement comparable pour les applications de faible et de moyen puissance mais avec l'avantage d'une meilleure précision et une meilleure flexibilité. / Owing to the development of modern semiconductor technology, it is possible to implement a digital controller for low-power high switching frequency DC-DC power converter in FPGA and ASIC. This thesis is intended to propose digital controllers with high performance, low power consumption and simple implementation architecture. Besides existing digital control-laws, such as PID, RST, tri-mode and sliding-mode (SM), a novel digital control-law, direct control with dual-state-variable prediction (DDP control), for the buck converter is proposed based on the principle of predictive control. Compared to traditional current-mode predictive control, the predictions of the inductor current and the output voltage are performed at the same time by adding a control variable to the DPWM signal. DDP control exhibits very high dynamic transient performances under both load variations and reference changes. Experimental results in FPGA verify the performances at switching frequency up to 4MHz. For the boost converter exhibiting more serious nonlinearity, linear PID and nonlinear SM controllers are designed and implemented in FPGA to verify the performances. A digital control requires a DPWM. Sigma-Delta DPWM is therefore a good candidate regarding the implementation complexity and performances. An idle-tone free condition for Sigma-Delta DPWM is considered to reduce the inherent tone-noise under DC-excitation compared to the classic approach. A guideline for Sigma-Delta DPWM helps to satisfy proposed condition. In addition, an 1-1 MASH Sigma-Delta DPWM with a feasible dither generation module is proposed to further restrain the idle-tone effect without deteriorating the closed-loop stability as well as to preserve a reasonable cost in hardware resources. The FPGA-based experimental results verify the performances of proposed DPWM in steady-state and transient-state. Two ASICs in 0.35µm CMOS process are implemented including the tri-mode controller for buck converter and the PID and SM controllers for the buck and boost converters respectively. The lab-scale tests are designed to lead to a power assessment model suggesting feasible applications. For the tri-mode controller, the measured power consumption is only 24.56mW/MHz when the time ratio of stand-by operation mode is 0.7. As specific power optimization strategies in RTL and system-level are applied to the latter chip, the measured power consumptions of the SM controllers for buck converter and boost converter are 4.46mW/MHz and 4.79mW/MHz respectively. The power consumption is foreseen as less than 1mW/MHz when the process scales down to nanometer technologies based on the power-scaling model. Compared to the state-of-the-art analog counterpart, the prototype ICs are proven to achieve comparable or even higher power efficiency for low-to-medium power applications with the benefit of better accuracy and better flexibility.

Les technologies avancées de semi-conducteur permettent de mettre en œuvre un contrôleur numérique dédié aux convertisseurs à découpage, de faible puissance et de fréquence de découpage élevée sur FPGA et ASIC. Cette thèse vise à proposer des contrôleurs numériques des performances élevées, de faible consommation énergétique et qui peuvent être implémentés facilement. En plus des contrôleurs numériques existants comme PID, RST, tri-mode et par mode de glissement, un nouveau contrôleur numérique (DDP) pour le convertisseur abaisseur de tension est proposé sur le principe de la commande prédictive: il introduit une nouvelle variable de contrôle qui est la position de la largeur d'impulsion permettant de contrôler de façon simultanée le courant dans l'inductance et la tension de sortie. La solution permet une dynamique très rapide en transitoire, aussi bien pour la variation de la charge que pour les changements de tension de référence. Les résultats expérimentaux sur FPGA vérifient les performances de ce contrôleur jusqu'à la fréquence de découpage de 4MHz. Un contrôleur numérique nécessite une modulation numérique de largeur d'impulsion (DPWM). L'approche Sigma-Delta de la DPWM est un bon candidat en ce qui concerne le compromis entre la complexité et les performances. Un guide de conception d'étage Sigma-Delta pour le DPWM est présenté. Une architecture améliorée de traditionnelles 1-1 MASH Sigma-Delta DPWM est synthétisée sans détérioration de la stabilité en boucle fermée ainsi qu'en préservant un coût raisonnable en ressources matérielles. Les résultats expérimentaux sur FPGA vérifient les performances des DPWM proposées en régimes stationnaire et transitoire. Deux ASICs sont portés en CMOS 0,35µm: le contrôleur en tri-mode pour le convertisseur abaisseur de tension et la commande par mode de glissement pour les convertisseurs abaisseur et élévateur de tension. Les bancs de test sont conçus pour conduire à un modèle d'évaluation de consommation énergétique. Pour le contrôleur en tri-mode, la consommation de puissance mesurée est seulement de 24,56mW/MHz lorsque le ratio de temps en régime de repos (stand-by) est 0,7. Les consommations de puissance de command par mode de glissement pour les convertisseurs abaisseur et élévateur de tension sont respectivement de 4,46mW/MHz et 4,79mW/MHz. En utilisant le modèle de puissance, une consommation de la puissance estimée inférieure à 1mW/MHz est envisageable dans des technologies CMOS plus avancées. Comparé aux contrôlés homologues analogiques de l'état de l'art, les prototypes ASICs illustrent la possibilité d'atteindre un rendement comparable pour les applications de faible et de moyen puissance mais avec l'avantage d'une meilleure précision et une meilleure flexibilité.

The use of SMPS (Switched mode power supply) in embedded systems is continuously increasing. The technological requirements of these systems include simultaneously a very good voltage regulation and a strong compactness of components. SEPIC ( Single-Ended Primary Inductor Converter) is a DC/DC switching converter which possesses several advantages with regard to the other classical converters. Due to the difficulty in control of its 4th-order and non linear property, it is still not well-exploited. The objective of this work is the development of successful strategies of control for a SEPIC converter on one hand and on the other hand the effective implementation of the control algorithm developed for embedded applications (FPGA, ASIC) where the constraints of Silicon surface and the loss reduction factor are important. To do it, two non linear controls and two observers of states and load have been studied: a control and an observer based on the principle of sliding mode, a deadbeat predictive control and an Extended Kalman observer. The implementation of both control laws and the Extended Kalman observer are implemented in FPGA. An 11-bit digital PWM has been developed by combining a 4-bit Δ-Σ modulation, a 4-bit segmented DCM (Digital Clock Management) phase-shift and a 3-bit counter-comparator. All the proposed approaches are experimentally validated and constitute a good base for the integration of embedded switching mode converters

L’utilisation des alimentations à découpage (SMPSs : switched mode power supplies) est à présent largement répandue dans des systèmes embarqués en raison de leur rendement. Les exigences technologiques de ces systèmes nécessitent simultanément une très bonne régulation de tension et une forte compacité des composants. SEPIC (Single-Ended Primary Inductor Converter) est un convertisseur à découpage DC/DC qui possède plusieurs avantages par rapport à d’autres convertisseurs de structure classique. Du fait de son ordre élevé et de sa forte non linéarité, il reste encore peu exploité. L’objectif de ce travail est d’une part le développement des stratégies de commande performantes pour un convertisseur SEPIC et d’autre part l’implémentation efficace des algorithmes de commande développés pour des applications embarquées (FPGA, ASIC) où les contraintes de surface silicium et le facteur de réduction des pertes sont importantes. Pour ce faire, deux commandes non linéaires et deux observateurs augmentés (observateurs d’état et de charge) sont exploités : une commande et un observateur fondés sur le principe de mode de glissement, une commande prédictive et un observateur de Kalman étendu. L’implémentation des deux lois de commande et l’observateur de Kalman étendu sont implémentés sur FPGA. Une modulation de largeur d’impulsion (MLI) numérique à 11-bit de résolution a été développée en associant une technique de modulation Δ-Σ de 4-bit, un DCM (Digital Clock Management) segmenté et déphasé de 4-bit, et un compteur-comparateur de 3-bit. L’ensemble des approches proposées sont validées expérimentalement et constitue une bonne base pour l’intégration des convertisseurs à découpage dans les alimentations embarquées. / The use of SMPS (Switched mode power supply) in embedded systems is continuously increasing. The technological requirements of these systems include simultaneously a very good voltage regulation and a strong compactness of components. SEPIC ( Single-Ended Primary Inductor Converter) is a DC/DC switching converter which possesses several advantages with regard to the other classical converters. Due to the difficulty in control of its 4th-order and non linear property, it is still not well-exploited. The objective of this work is the development of successful strategies of control for a SEPIC converter on one hand and on the other hand the effective implementation of the control algorithm developed for embedded applications (FPGA, ASIC) where the constraints of Silicon surface and the loss reduction factor are important. To do it, two non linear controls and two observers of states and load have been studied: a control and an observer based on the principle of sliding mode, a deadbeat predictive control and an Extended Kalman observer. The implementation of both control laws and the Extended Kalman observer are implemented in FPGA. An 11-bit digital PWM has been developed by combining a 4-bit Δ-Σ modulation, a 4-bit segmented DCM (Digital Clock Management) phase-shift and a 3-bit counter-comparator. All the proposed approaches are experimentally validated and constitute a good base for the integration of embedded switching mode converters