Este trabalho apresenta o estudo do comportamento da resistência série de fonte e dreno em transistores SOI FinFET de porta tripla e com canal tensionado. Nos dispositivos SOI FinFETs há um aumento da resistência série de fonte e dreno devido ao estreitamento dessas regiões, sendo esse parâmetro considerado como uma das limitações quanto à introdução desses dispositivos em tecnologias futuras. O uso de tensão mecânica no canal dos dispositivos surge como alternativa para aumentar a condução de corrente através do aumento da mobilidade dos portadores do canal, reduzindo assim, a resistência total dos transistores e, conseqüentemente, a resistência série de fonte e dreno. Inicialmente, foi feito o estudo de alguns métodos de extração da resistência série de fonte e dreno existentes na literatura, com o objetivo de se obter o mais adequado para aplicação e análise posterior. Esse trabalho foi realizado baseado em resultados experimentais e em simulações numéricas que possibilitaram o entendimento físico do fenômeno estudado. A resistência série de fonte e dreno foi explorada em diferentes tecnologias, como transistores SOI FinFETs de porta tripla convencionais e sob influência de tensionamento uniaxial e biaxial. O uso do crescimento seletivo epitaxial (SEG) nas regiões de fonte e dreno altamente dopadas das diferentes tecnologias também foi analisado, pois com essa técnica, a resistência série de fonte e dreno é reduzida substancialmente não comprometendo a condução de corrente e a transcondutância. Os resultados obtidos das diferentes tecnologias com e sem o uso de SEG foram analisados e comparados mostrando que em transistores SOI FinFETs de porta tripla, com crescimento seletivo epitaxial, apresentam o menor valor da resistência série de fonte e dreno mesmo para aqueles sem tensão mecânica na região do canal. / This work presents the study of the source and drain series resistance behavior in standard and strained SOI FinFETs triple gate transistors. In SOI FinFETs transistors there is an increase of the source and drain series resistance due to the narrow of these regions, being this parameter a key limiting factor to the next generations. The use of strained transistors is one of the potential technologies to the next generation high performance because it increase the drive current through an enhance in the carrier mobility, decreasing the transistors total resistance and, therefore, the source and drain series resistance. Initially, a study of some series resistance extraction methods, present in the literature was done, in order to obtain the most appropriate for applications and analysis subsequent. This work was done based on experimental results and numerical simulations, enabling the physical understanding of the phenomenon studied. The series resistance was explored in different technologies, as standard SOI FinFETs triple gates and with uniaxial and biaxial strain. The use of selective epitaxial growth (SEG) in the source and drain regions, with high doping levels, was also studied in the different technologies, because with the use of this technique, the series resistance decreases substantially without compromising the drive current and transconductance. The obtained results from the different technologies with and without the use of SEG were analyzed and compared showing that, SOI FinFETs triple gate transistors with SEG present the lower values of series resistance even for standard devices if compared with strained ones without the use of SEG.

Neste trabalho, é apresentada uma análise da operação analógica de transistores de múltiplas portas, avaliando a tensão Early, o ganho de tensão em malha aberta, a razão da transcondutância pela corrente de dreno (gm/IDS), a condutância de dreno e, em especial, a distorção harmônica, exibida por estes dispositivos. Ao longo deste trabalho, foram estudados FinFETs, dispositivos de porta circundante (Gate-All-Around GAA) com estrutura de canal gradual (Graded-Channel GC) e transistores MOS sem junções (Junctionless - JL). Inicialmente, foi efetuada a análise da distorção harmônica apresentada por FinFETs com e sem a presença de tensão mecânica biaxial, com diversas larguras de fin (Wfin) e comprimentos de canal (L), quando estes operavam em saturação, como amplificadores de um único transistor. Nesta análise, as não-linearidades foram avaliadas através da extração das distorções harmônicas de segunda e terceira ordens (HD2 e HD3, respectivamente), mostrando que a presença de tensão mecânica tem pouca influência em HD2, mas altera levemente a HD3. Quando os ganhos de tensão em malha aberta dos dispositivos são levados em conta, transistores sem tensão, também chamados de convencionais, mais estreitos apresentam grande vantagem em termos de HD2 em relação aos tensionados. Ainda nesta análise, percebeu-se que HD2 e HD3 de transistores tensionados pioram com a redução da temperatura, especialmente em inversão mais forte. Na seqüência, foi efetuada uma análise de HD3 em FinFETs com e sem tensão mecânica de vários comprimentos e larguras de canal, operando em região triodo e aplicados a estruturas balanceadas 2-MOS, mostrando que presença de tensão mecânica traz pouca influência em HD3, mas reduz a resistência do canal dos dispositivos (RON), o que não é bom em estruturas resistivas, como as avaliadas. Nesta análise, ainda, pode-se perceber uma melhora em HD3 superior a 30 dB ao se incrementar VGT de zero a 1,0 V, em cuja tensão dispositivos mais estreitos apresentam curvas mais lineares que os mais largos. Então, foi estudada a distorção apresentada por transistores GAA e GC GAA operando em regime triodo, aplicados a estruturas 2-MOS, onde se pôde perceber que GC GAAs com maiores comprimentos da região fracamente dopada apresentam vantagem em HD3 em relação aos demais, para valores de VGT superiores a 2 V. Na avaliação destas estruturas em função da temperatura, percebeu-se que, para VGT superiores a 1,1 V, HD3 depende fortemente da temperatura e piora conforme a temperatura diminui. O estudo envolvendo transistores sem junções foi mais focado em seus parâmetros analógicos, comparando-os aos apresentados por dispositivos de porta tripla ou FinFETs. Em inversões moderada e forte, transistores sem junção apresentaram menores valores para gm/IDS em relação a dispositivos de FinFETs polarizados em um mesmo nível de corrente, entretanto, a dependência de gm/IDS com a temperatura em transistores sem junção também foi menor que a apresentada por FinFETs. JL e FinFETs apresentaram comportamentos distintos para a tensão Early e o ganho de tensão em malha aberta em função da temperatura. Estes parâmetros sempre melhoram com o aumento da temperatura em dispositivos JL, enquanto que exibem seu máximo valor em temperatura ambiente em FinFETs. Nas proximidades da tensão de limiar, transistores sem junção com largura de fin de 30 nm exibiram tensão Early e ganho superiores a 80 V a 57 dB, respectivamente, enquanto que FinFETs mostraram Tensão Early de 35 V e ganho de 50 dB. Em todos os estudos efetuados ao longo do trabalho, procurou-se apontar as causas das não-linearidades apresentadas pelos dispositivos, a partir de modelos analíticos que pudessem relacionar a física de funcionamento dos transistores com os resultados experimentalmente obtidos. / In this work it is presented an analysis of the analog operation of multiple gate transistors, evaluating the Early Voltage, the open-loop voltage gain, the transconductance over the drain current ratio (gm/IDS), the drain conductance and, especially, the harmonic distortion exhibited by these devices. Along the work, FinFETs, Gate-All-Around (GAA) devices with the Graded-Channel (GC) structure and MOS transistors without junctions (Junctionless - JL) were studied. Initially, an analysis of the harmonic distortion presented by conventional and biaxially strained FinFETs with several fin widths (Wfin) and channel lengths (L) was performed, when these devices were operating in saturation as single transistor amplifiers. In this analysis, the non-linearities were evaluated through the extraction of the second and the third order harmonic distortions (HD2 and HD3, respectively), and it was shown that the presence of strain has negligible influence in HD2, but slightly changes HD3. When the open loop voltage gain of the devices is taken into consideration, narrower conventional transistors present a huge advantage with respect to the strained ones in terms of HD2. Also, it was perceived that both HD2 and HD3 of strained FinFETs worsen with the temperature decrease, especially in stronger inversion. In the sequence, an analysis of the HD3 presented by conventional and strained FinFETs of several fin widths and channel lengths operating in the triode regime was performed. These devices were applied to 2-MOS balanced structures, showing that the presence of the strain does not influence significantly the HD3, but reduces the resistance in the channel of the transistors (RON), which is not good for resistive structures as the ones evaluated. In this analysis, it can also be observed an HD3 improvement of 30 dB when VGT is increased from zero up to 1,0 V, where narrower devices present transfer characteristics more linear than the wider ones. Then, it was studied the distortion presented by GAA and GC GAA devices operating in the triode regime, applied to 2-MOS structures. In this case, it could be perceived that GC GAAs with longer lightly doped regions present better HD3 in comparison to the other devices for VGT higher than 2.0 V. In the evaluation of these structures as a function of the temperature, it could be seen that for VGT higher than 1.1 V, HD3 strongly depends on the temperature and worsens as the temperature decreases. The study involving JL transistors was focused on their analog parameters, comparing them to the ones presented by triple gate devices or FinFETs. In moderate and strong inversions, Junctionless showed lower values for gm/IDS with respect to triple gate devices biased at a similar current level. However, the dependence of gm/IDS from Junctionless with the temperature was also smaller than the one presented by FinFETs. Junctionless and FinFETs exhibited distinct behaviors for the Early voltage and the open-loop voltage gain as a function of the temperature. These parameters always improve with the temperature raise in JL devices whereas they exhibit their maximum values around room temperatures for FinFETs. In the proximity of the threshold voltage, Junctionless with fin width of 30 nm presented Early voltage and intrinsic gain larger than 80 V and 57 dB, respectively, whereas FinFETs exhibited Early voltage of 35 V and gain of 50 dB. For all the studies performed in this work, the probable causes of the non-linearities were pointed out, from analytic models that could correlate the physical work of the devices with the experimental results.

O objetivo deste trabalho é investigar a aplicação ressoadores WGM (Whispering-Gallery Mode) em plataforma SOI (silicon-on-insulator) baseados em grafeno como candidatas potenciais para aplicações como moduladores de eletro-absorção. O grafeno apresenta variação de condutividade considerável quando submetido a uma aplicação de tensão, o que reflete na parte imaginária de seu índice de refração (relacionada às perdas de propagação). Com isso, é possível atribuir estados ligado e desligado (on-off) que conferem ao dispositivo sua característica de modulação óptica. A geometria utilizada é do tipo anel, o que permite uma elevada seletividade em frequência possibilitando, assim, uma grande profundidade de modulação. As simulações foram realizadas no software de elementos finitos COMSOL Multiphysics, o qual é bastante apropriado para a definição das diferentes figuras de mérito a serem utilizadas para a caracterização do desempenho do modulador. / The goal of this work is to investigate SOI (silicon on insulator) WGM (Whispering-Gallery Modes) resonators based on graphene as potential candidates for electro-absorption modulator applications. Graphene conductivity varies substantially when submitted to an applied voltage, which reflects directly in the imaginary part of its refractive index (responsible for the propagation losses). Therefore, it is possible to assign on-off states that render the device its optical modulation characteristics. The geometry adopted for the design is the ring type, which allows high frequency selectivity and modulation depth. The simulations were carried out in the finite elements software COMSOL Multiphysics, which is quite appropriate for the definition of the different figure of merits to be used in the modulator characterization.

Ce mémoire de thèse traite de l’étude de la sensibilité des composants électroniques avancés en milieu radiatif. Le travail porte sur la modélisation détaillée du dépôt d’énergie induit par un ion lourd dans la matière, et sur l’influence de la prise en compte de cette trace d’ion dans les outils de simulation de la réponse de composants irradiés. Dans ce but, nous avons développé une chaîne de simulation, combinant différents codes de calcul à des échelles variées. Dans une première étape, le code d’interactions particule-matière Geant4 est ainsi utilisé pour modéliser la trace d’ion. Ces traces sont ensuite implémentées dans un code de simulation TCAD, afin d’étudier la réponse de transistors élémentaires à ces dépôts d’énergies détaillés. Cette étape est complétée par des mesures expérimentales. Enfin, l’étude est étendue au niveau circuit, en interfaçant les traces d’ions avec un outil de prédiction des SEE. Ces différentes étapes mettent en évidence la nécessité de prendre en compte la dimension radiale de la trace d’ion à tous les niveaux de simulation, pour modéliser de façon adéquate la réponse de composants avancés sous irradiation par des ions lourds. / This thesis studies the sensitivity of advanced electronic devices in radiative environments. The work deals with the detailed modeling of the deposited energy induced by heavy-ion in matter, and the influence of taking it into account in the tools simulating the response of irradiated devices. To do so, a simulation chain was developed, combining different calculation codes at various scales. In a first step, the particle-matter interaction code Geant4 is used to model the heavy ion track. These tracks are then implemented in a TCAD simulator, in order to study the response of elementary transistors to these detailed energy deposits. This step is completed with experimental measurements. Finally, the study is extended to the circuit level, by interfacing the heavy ion tracks with a SEE prediction tool. These different steps evidence the need for taking into account the radial extension of the ion track to all simulation levels, to adequately model the response of advanced devices under heavy ion irradiations.

Cette thèse s'interroge sur la connaissance de soi émotionnelle, sur sa place ainsi que sa participation à la connaissance de soi, sur la valeur qu'elle a pour les individus ordinaires et sur la manière dont les individus ordinaires peuvent l'obtenir. L'examen de la nature des émotions et de la valeur que les individus accordent à la connaissance de leurs émotions, qui est effectué dans cette thèse, met en avant l'importance de l'acquisition de la connaissance de soi émotionnelle, ainsi que le lien que cette dernière est communément entendue entretenir avec le bonheur. Si l'acquisition de cette connaissance apparaît comme primordiale, elle n'en est pas pour autant facile. Elle requiert le déploiement d'un certain nombre de capacités cognitives, ainsi qu'un effort cognitif important, notamment au cours de l'utilisation de l'introspection. En effet, cette thèse discute exclusivement de l'accès introspectif à la connaissance de soi émotionnelle, et laisse de côté les autres formes d'accès à la connaissance de soi. Je m'interroge donc dans ce travail, sur la portée pratique mais aussi morale de l'utilisation de l'introspection au regard des émotions, en proposant une défense du processus introspectif comme d'un processus capable de permettre à un individu ordinaire de détecter, d'identifier et d'interpréter ses propres émotions. Cette thèse est donc axée autour de deux arguments principaux. Le premier de ces aruments octroie à la connaissance de soi émotionnelle, une place fondamentale au sein de la forme de connaissance de soi qui importe aux individus ordinaires. Le second défend l'idée selon laquelle l'introspection offre un accès à cette connaissance émotionnelle, notamment par le biais de l'appréhension qu'elle permet de la phénoménologie des émotions, et que cet accès a une fiabilité minimale et donc une valeur épistémique, même faible, ainsi qu'une valeur morale et intrinsèque. / This thesis examines emotional self-knowledge, its place as well as its participation in self-knowledge, the value it has for ordinary individuals and how ordinary individuals can obtain it. The examination of the nature of the emotions and the value that individuals place on the knowledge of their emotions, which is carried out in this thesis, highlights the importance of the acquisition of emotional-selfknowledge, as well as the link thet the latter is commonly heard to maintain with happiness. If the acquisition of this knowledge appears to be essential, it is not easy. It requires the unfurling of a number of cognitive abilities, as well as a significant cognitive effort, especially during the use of introspection. Indeed, this thesis exclusively discusses introspective access to emotional self-knowledge, and set aside other forms of access to self-knowledge. In this woek, I therefore question the practical but also moral scope of the use of introspection with regard to emotions, proposing a defense of the introspective process as a process capable of allowing an ordinary individual to detect, to identify and interpret one's own emotions. This thesis is therefore organized around two main arguments. The first of these arguments gives emotional self-knowledge a fundamental place in the form of self-knowledge that matters to ordinary people. The second defends the idea that introspection offers access ti this emotional knowledge, notably through the apprehension that its allows of the phenomenology of emotions, and that this access has a minimum reliability and therefore an epistemic value - even a weak one - as well as a moral and intrinsic value.

L’utilisation des ultrasons pour l’imagerie présente plusieurs avantages : elle est extrêmement sure car ellen'utilise pas de radiations ionisantes et ne présente pas d'effets néfastes sur la santé. D’autre part, elle donne desrésultats d’excellente qualité avec un coût relativement faible. Historiquement, les matériaux piézoélectriques et leurscomposites ont été très tôt utilisés pour la génération d’ultrasons. Les transducteurs fabriqués à partir de ces matériauxdominent actuellement le marché des sondes ultrasonores. Cependant, pour certaines applications, ils ne peuvent pasêtre utilisés pour des raisons de dimensionnement et de limitations dues aux propriétés des matériaux. Une solutionpeut être apportée par l’utilisation des transducteurs ultrasonores capacitifs micro-usinés dits CMUTs. Ces dernierssuscitent un intérêt croissant dans le milieu de l’imagerie ultrasonore et sont considérés comme une alternativepotentielle et viable aux transducteurs piézoélectriques. Cette nouvelle technologie CMUTs est caractérisée par uneplus large bande passante, une sensibilité élevée, une facilité de fabrication et une réduction des coûts de production.Cette thèse est consacrée à la mise en place d’un certain nombre d’outils théoriques et expérimentaux permettant lamodélisation/conception, la fabrication et la caractérisation de transducteurs CMUTs à membrane circulaire pourl’émission des ultrasons. Nous commençons par développer des outils de simulation à base de calculs par élémentsfinis, permettant la compréhension et la modélisation du comportement électromécanique des CMUTs pour laconception et le dimensionnement des cellules élémentaires et des réseaux. Nous proposons par la suite un nouveauprocédé de fabrication de transducteurs CMUTs basé sur le collage anodique d’une couche de silicium monocristallind’épaisseur fixe d’une plaquette de SOI sur un substrat de verre. L’évolution du procédé de fabrication est détailléepour chaque étape technologique en soulignant à chaque fois les améliorations/modifications apportées pour unefiabilité et une répétitivité accrue associées à une connaissance des limites de faisabilité. Dans la dernière partie de cetravail, on s’intéresse à la mise en œuvre de plusieurs plateformes expérimentales permettant différentescaractérisations électromécaniques statiques et dynamiques des dispositifs CMUTs fabriqués / The use of ultrasound imaging has several advantages: it is extremely safe because it does not use ionizingradiation and has no adverse effects on health. It gives excellent quality results with a relatively low cost. Historically,piezoelectric materials and their composites have been early used for ultrasound generation. Transducers made fromthese materials dominate currently the ultrasonic probes market. However, for some applications, they can’t bebecause of design and limitation reasons due to material properties. A solution can be provided by the use ofcapacitive micromachined ultrasonic transducers CMUTs. A growing interest in the field of the ultrasound imaging isshown to this technology considered as a potential and viable alternative to piezoelectric transducers andcharacterized by a wide bandwidth, high sensitivity, ease of manufacture and reduce production costs. This thesis isdevoted to the establishment of a number of experimental and theoretical tools for the modeling/design, fabricationand characterization of circular membrane CMUTs transducers for ultrasound transmission. We begin by developingsimulation tools based on finite elements method in order to understand/model the CMUTs electromechanicalbehavior for the design and dimensioning of elementary cells and networks. Thereafter, we introduce a new CMUTtransducers fabrication process based on the anodic bonding a fixed thickness single crystal silicon layer of a SOIwafer on a glass substrate. The process evolution is detailed for each technological step highlighting everyimprovements/changes introduced for increased reliability and repeatability associated with an increased knowledgeof feasibility limits. In the last part of this work, we focus on the implementation of several experimental platformsallowing different static and dynamic electromechanical characterizations of the fabricated CMUTs devices.

Cette thèse s’intéresse à une technique de caractérisation particulièrement bien adaptée à l’étude de couches diélectriques ultra-minces sur semiconducteurs. La génération de seconde harmonique (SHG) est une méthode très prometteuse, basée sur l’optique non-linéaire. Un laser est focalisé sur l'échantillon à caractériser et le signal à deux fois la fréquence fondamentale est mesuré. Pour les matériaux centrosymétriques comme c-Si, SiO2 et Al2O3, le signal SHG est dû aux défauts et au champ électrique Edc d’interface (induit par les charges préexistantes Qox et/ou piégées au niveau des pièges d’interface Dit). La SHG donne ainsi accès à la qualité des interfaces entre diélectriques/semiconducteurs. Néanmoins, le signal SHG dépend aussi des phénomènes de propagation optique dans les structures multicouches. Pour cette raison, nous avons développé un programme de simulation qui prend en compte les phénomènes optiques et les champs électriques statiques aux interfaces. Nous avons utilisé la SHG pour analyser la qualité de passivation de structures Al2O3/Si préparées avec des procédés différents et nous avons montré une corrélation entre SHG et mesure de durée de vie des porteurs de charges. Les valeurs de Qox et Dit ont été extraites par des mesures de capacité-tension et elles ont permis de calculer le champ Edc. La simulation optique, avec les valeurs extraites de Edc a permis de reproduire les données expérimentales de SHG dans ces structures. La SHG a été utilisée également pour la caractérisation des substrats Silicium-sur-Isolant (SOI). Pour les structures SOI épaisses, la simulation et les résultats expérimentaux ont montré que la réponse SHG est dominée par les interférences optiques (faible impact de Edc). Pour les structures SOI ultraminces, les interfaces sont couplées électriquement et des valeurs de Edc sont nécessaires pour reproduire les données expérimentales par simulation. Cela implique que pour les SOI ultraminces, la SHG pourrait donner accès aux champs électriques au niveau des interfaces d’une manière non-destructive. / This PhD work was developed in the context of research for novel characterization methods for ultra-thin dielectric films on semiconductors and their interfacial quality. Second harmonic generation (SHG) is a very promising non-invasive technique based on nonlinear optics. A laser emitting at the fundamental frequency is incident upon the sample which responds through its 2nd order polarization, generating a signal at twice the fundamental frequency. For centrosymmetric materials such as c-Si, amorphous SiO2 or Al2O3, the SHG signal is mainly due to the defects and to the static electric field Edc present at the interface (due to pre-existing charges Qox and/or photo-injected charge trapping/detrapping at interface traps Dit). Thus, SHG measurement gives access to the quality of dielectric/semiconductor interfaces. Nevertheless, the SHG signal is also dependent on multilayer optical propagation phenomena. For this reason, we have developed a simulation program which accounts for the optical phenomena and the static electric fields at the interfaces. We have used SHG to monitor the passivation quality of Al2O3/Si structures prepared with different processes and showed a correlation between SHG and minority carrier lifetime measurements. Qox and Dit were extracted from capacitance-voltage measurements and helped calculating the Edc values. The optical simulation, fed with known Edc values reproduced the experimental SHG data in these structures. The SHG was also used for Silicon-on-Insulator (SOI) substrates characterization. In thick SOI structures, both simulations and experimental results show that the SHG response is mainly given by optical interferences (Edc has no impact). In ultrathin SOI, the interfaces are electrically coupled and Edc is needed as input in the simulation in order to reproduce the experimental SHG data. This implies that in ultrathin SOI, SHG can access the interface electric fields in a non-destructive way.

Afin de suivre le rythme effréné des évolutions des systèmes embarqués et des dispositifs portables, il s’avère aujourd’hui indispensable d’optimiser la gestion de l’énergie sans pour autant compromettre la performance et la robustesse des circuits. Dans ce contexte, cette thèse étudie de nouveaux dispositifs de gestion de l’énergie ainsi que leur mise en œuvre, en combinant deux approches: la logique asynchrone et les techniques de polarisation du substrat (Adaptive Body Biasing - ABB). Cette thèse comporte quatre contributions permettant la conception de circuits asynchrones énergétiquement plus efficaces. 1) Une unité arithmétique et logique (UAL) asynchrone quasi insensible aux délais (Quasi Delay Insensitive - QDI) a été conçue et utilisée pour mener une analyse comparative entre systèmes synchrones et asynchrones. Cette étude démontre notamment  la meilleure efficacité énergétique et la plus grande robustesse des circuits asynchrones QDI, surtout lorsqu’ils fonctionnent à basse tension. 2) Une cellule standard a été spécialement développée pour mettre en œuvre nos schémas d’adaptation dynamique du substrat (ABB) qui ajustent la tension de seuil (Vth) des transistors. En outre, cette cellule s’est révélée très utile pour la détection de fautes transitoires causées par des radiations environnementales. Cette cellule est en outre un élément clé pour exploiter la polarisation du substrat, un des intérêts majeurs de la technologie FD-SOI, et d’améliorer la fiabilité du système. 3) Trois stratégies de polarisation de substrat ont été évaluées. Ces stratégies reposent sur la détection automatique de l’activité des circuits asynchrones QDI et de la polarisation de multiples domaines dans le substrat (Body Biasing Domains - BBD). De plus, une méthode pour analyser l’efficacité énergétique des stratégies de polarisation pour les circuits asynchrones QDI a également été proposée dans le cadre de cette thèse. 4) Enfin, un flot de conception de circuits numériques intégrés a été proposé et développé. Ce flot, basé sur des cellules standards, permet d’exploiter des stratégies de polarisation (ABB) avec plusieurs domaines (BBD) en utilisant la cellule standard spécialement développée. Un testchip a été conçu et fabriqué pour valider notre flot de conception et évaluer l’efficacité de la cellule proposée. / Keeping the fast evolving pace of embedded systems of portable devices require ameliorations of power management techniques, without compromising the circuit performance and robustness. In this context, this thesis studies novel energy management schemes, and how to implement them, by using two main design approaches: asynchronous logic and adaptive body biasing (ABB) techniques. Four main contributions have been done, thus enabling the design of more energy efficient asynchronous circuits. 1) We contributed with the design of a Quasi-delay Insensitive (QDI) asynchronous ALU architecture, used in a comparative analysis of asynchronous versus synchronous systems. This first study has demonstrated the energy efficiency and robustness of QDI circuits, especially if operating at low power supply (Vdd ). 2) We proposed a new body built-in cell for implementing ABB schemes by tuning the circuit threshold voltage (Vth) on-the-fly; and detecting short-duration and long-duration transient faults (TF) caused by environmental radiation. The proposed cell is a key building block to fully benefit from body biasing features of the FD-SOI technology while enhancing system’s reliability. 3) We assessed three different ABB strategies - based on automatic activity detection and multiple body-biasing domains (BBDs) - for QDI asynchronous circuits. Furthermore, a methodology for analyzing energy efficiency of ABB strategies in QDI asynchronous circuits is also proposed in this work. 4) We developed a standard cell-based IC design flow to apply ABB strategies with multiple BBDs by using the proposed body built-in cells. A testchip has been designed and fabricated to validate the developed design flow and the efficacy of the body built-in cell.

Dans le cadre des nouvelles applications dans la bande de fréquence millimétrique, une évaluation de la technologie CMOS 65nm SOI pour la conception de circuits est proposée. Cette évaluation s'articule autour de deux axes principaux. Tout d'abord les composants actifs et passifs spécifiques à la technologie font l'objet d'une étude en terme de performances et de modélisations. Ensuite la technologie est évaluée au travers l'exemple de circuits composant une chaîne de réception

Cette thèse s'intéresse à la construction du Concept de Soi (CDS) en situation d'enseignement d'Education Physique et Sportive (EPS). L'objectif de ce travail doctoral est de mettre en évidence différents antécédents du CDS mais également d'envisager le rôle que joue le CDS dans sa propre formation et évolution. La théorie de la vérification de soi (Swann, 1990) insiste en effet sur le rôle actif du CDS dans le maintien et la recherche de stabilité des visions de soi au cours du temps. Dans une série de 6 études, nous envisageons différents modèles de la formation du CDS développés en contexte scolaire (i.e., modèle d'ordre causal, modèle Interne/Externe, modèle « Gros poisson – Petit Bassin », travaux sur les choix de cibles de comparaison) dans une matière physique et « secondaire », l'EPS. Plusieurs modulateurs des différentes antécédents du CDS relatifs à ces modèles sont également envisagés (e.g., le sexe de l'élève, le niveau de pratique, le degré d'autodétermination de l'élève). Enfin, les postulats de la théorie de la vérification de soi sont interrogés au regard de l'influence du CDS de l'élève sur (1) les perceptions des autrui significatifs (i.e., l'enseignant), (2) le traitement et la perception des feedback reçus, et (3) l'utilisation des stratégies de présentation de soi, dès lors que la situation met en danger la stabilité de ce construit.