To provide more information mobility, many wireless communication systems such as WCDMA and EDGE in phone systems, bluetooth and WIMAX in communication networks have been recently developed. Recent efforts have been made to build the allin- one next generation device which integrates a large number of wireless services into a single receiving path in order to raise the competitiveness of the device. Among all the receiver architectures, the high-IF receiver presents several unique properties for the next generation receiver by digitalizing the signal at the intermediate frequency around a few hundred MHz. In this architecture, the modulation/demodulation schemes, protocols, equalization, etc., are all determined in a software platform that runs in the digital signal processor (DSP) or FPGA. The specifications for most of front-end building blocks are relaxed, except the analog-to-digital converter (ADC). The requirements of large bandwidth, high operational frequency and high resolution make the design of the ADC very challenging. Solving the bottleneck associated with the high-IF receiver architecture is a major focus of many ongoing research efforts. In this work, a 6th-order bandpass continuous time sigma-delta ADC with measured 68.4dB SNDR at 10MHz bandwidth to accommodate video applications is proposed. Tuned at 200 MHz, the fs/4 architecture employs an 800 MHz clock frequency. By making use of a unique software-based calibration scheme together with the tuning properties of the bandpass filters developed under the umbrella of this project, the ADC performance is optimized automatically to fulfill all requirements for the high-IF architecture. In a separate project, other critical design issues for continuous-time sigma-delta ADCs are addressed, especially the issues related to unit current source mismatches in multi-level DACs as well as excess loop delays that may cause loop instability. The reported solutions are revisited to find more efficient architectures. The aforementioned techniques are used for the design of a 25MHz bandwidth lowpass continuous-time sigma-delta modulator with time-domain two-step 3-bit quantizer and DAC for WiMAX applications. The prototype is designed by employing a level-to-pulse-width modulation (PWM) converter followed by a single-level DAC in the feedback path to translate the typical digital codes into PWM signals with the proposed pulse arrangement. Therefore, the non-linearity issue from current source mismatch in multi-level DACs is prevented. The jitter behavior and timing mismatch issue of the proposed time-based methods are fully analyzed. The measurement results of a chip prototype achieving 67.7dB peak SNDR and 78dB SFDR in 25MHz bandwidth properly demonstrate the design concepts and effectiveness of time-based quantization and feedback. Both continuous-time sigma-delta ADCs were fabricated in mainstream CMOS 0.18um technologies, which are the most popular in today?s consumer electronics industry.

A single-stage high-power-factor electronic ballast is designed for fluorescent lamps with dimming capability. The circuit configuration is originated from the integration of the half-bridge resonant inverter and the buck-boost converter. The buck-boost converter is designed to operate in discontinuous conduction mode (DCM) to provide nearly unit power factor at a fixed switching frequency. With asymmetrical pulse-width-modulation (APWM), the lamp power can be effectively regulated. The power switches of the inverter exhibit either zero-voltage-switching (ZVS) or zero-current-switching (ZCS) over the whole dimming range. Design equations are derived and computer analyses are performed based on a power-dependent lamp model and fundamental approximation. Design guidelines for determining circuit parameters are provided. A prototype circuit for a T8-36W fluorescent lamp is built and tested to verify the analytical predictions.

To minimize the size of the electronic ballast, a half-bridge load- resonant inverter with a cascading Rosen-type piezoelectric transformer (PT) is designed for cold cathode fluorescent lamps (CCFLs). The electrical characteristics of the PT are investigated to obtain a higher voltage gain by adapting the load impedance to the interposed network. The circuit parameters are selected under the considerations of (1) the minimum inductor size, (2) the higher circuit efficiency, (3) the rated current of the PT, and (4) the stable lamp operation. The electronic ballasts are designed for operating the lamp at the rated lamp power and with dimming control by asymmetrical pulse-width-modulation (APWM),respectively. Laboratory circuits are assembled and, experimental tests are carried out to validate the theoretical analyse

The design and implementation of the digital signal processing (DSP) based on a brushless DC (BLDC) motor sensorless driver with Sine PWM. Because of dispensable power consumption problems generated by closed-loop speed control methods with speed estimation signal feedback are adopted for improvement. In addition, current feedback is added to the driver for the sake of increasing efficiency. Then, sine wave closes 30¢X, 15¢X, and 8¢X to comparing the improvements for efficiency. Experimental results from a laboratory prototype are shown to verify the feasibility of the proposed scheme. The laboratory results show that current feedback and sine wave closed 8¢X have high efficiency.

<p>After only two years of service, extensive cracking was found in the webs of two light-rail commuter line bridges in Stockholm, the Gröndal and Alvik bridges. Due to this incident it was found necessary to study the means available for analysing shear cracking in concrete structures subjected to in-plane stresses. The aim of this PhD project is to study shear cracking with these two bridges as reference. In this thesis, the first part aims to study the possibility of using finite element analysis as a tool for predicting shear cracking for plane state stresses. The second part is concerning how the shear cracks are treated in the concrete design standards.</p><p>Shear cracking in reinforced beams has been studied with non-linear finite element analyses. In these analyses the shear cracking behaviour was compared to experiments conducted to analyse the shear failure behaviour. Finite element analyses were performed with two different FE programs Abaqus and Atena. The material model used in Atena is a smeared crack model based on damage and fracture theory with either fixed or rotated crack direction. The material model used in Abaqus is based on plasticity and damage theory. The fixed crack model in Atena and the model in Abaqus gave good results for all studied beams. For the two studied deep beams with flanges the results from the rotated crack model were almost the same as obtained with the fixed crack model. The rotated crack model in Atena gave though for some beams a rather poor estimation of the behaviour.</p><p>The calculation of crack widths of shear cracks has been studied for the long-term load case in the serviceability state for the Gröndal and Alvik bridges, with the means available in the design standards. The methods based on the crack direction corresponding to the principal stress and do not include the effect of aggregate interlocking seems to be too conservative. Two of the studied methods included the effect of aggregate interlocking, it was made either by introducing stresses in the crack plane or implicitly by changing the direction of the crack so that it no longer coincide with the direction of principal stress. For calculations based on probable load conditions, these methods gave estimations of the crack widths that were close to the ones observed at the bridges. Continuous measurements of cracks at the Gröndal and the Alvik bridges have also been included. Monitoring revealed that the strengthening work with post-tensioned tendons has, so far, been successful. It also revealed that the crack width variations after strengthening are mainly temperature dependent where the daily temperature variation creates movements ten times greater than those from a passing light-rail vehicle. Monitoring a crack between the top flange and the webs on the Gröndal Bridge showed that the top flange was moving in a longitudinal direction relative to the web until the strengthening was completed. The crack widths in the sections strengthened solely by carbon fibre laminates seem to increase due to long-term effects.</p>

The objective of this dissertation is the application of Minkowskian cross-section measures (i.e., section and projection measures in finite-dimensional linear normed spaces over the real field) to various topics of geometric convexity in Minkowski spaces, such as bodies of constant Minkowskian width, Minkowskian geometry of simplices, geometric inequalities and the corresponding optimization problems for convex bodies. First we examine one-dimensional Minkowskian cross-section measures deriving (in a unified manner) various properties of these measures. Some of these properties are extensions of the corresponding Euclidean properties, while others are purely Minkowskian. Further on, we discover some new results on the geometry of a simplex in Minkowski spaces, involving descriptions of the so-called tangent Minkowskian balls and of simplices with equal Minkowskian heights. We also give some (characteristic) properties of bodies of constant width in Minkowski planes and in higher dimensional Minkowski spaces. This part of investigation has relations to the well known \emph{Borsuk problem} from the combinatorial geometry and to the widely used monotonicity lemma from the theory of Minkowski spaces. Finally, we study bodies of given Minkowskian thickness ($=$ minimal width) having least possible volume. In the planar case a complete description of this class of bodies is given, while in case of arbitrary dimension sharp estimates for the coefficient in the corresponding geometric inequality are found. / Die Dissertation befasst sich mit Problemen fuer spezielle konvexe Koerper in Minkowski-Raeumen (d.h. in endlich-dimensionalen Banach-Raeumen). Es wurden Klassen der Koerper mit verschiedenen metrischen Eigenschaften betrachtet (z.B., Koerper konstante Breite, reduzierte Koerper, Simplexe mit Inhaltsgleichen Facetten usw.) und einige kennzeichnende und andere Eigenschaften fuer diese Klassen herleitet.

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This report is a study of the effects of a commercial 0.13[mu] process and automotive temperature corners on a synchronous DC-DC buck converter design. The basics of switching converters will be explored with an emphasis on voltage-mode controlled feedback. A Type-III compensation network is designed using transfer function analysis to compensate for the inherent double pole introduced by an LC network. The output of the compensation network will drive a pulse width modulation comparator to vary the duty cycle of the high-side PMOS and low-side NMOS transistor switches. After the synchronous buck converter design was complete, the effect of process and temperature on efficiency, output voltage ripple, inductor peak to peak current, and output voltage load response was examined. / text

The objective of this research is to explore circuit techniques and architectures suitable for implementation in digital technologies, that can be used to enhance the efficiency of power stages. Specifically, the use of switching power stages with pulse-width modulation techniques is considered. Switching power stages, such as Class D amplifiers, are inherently well-suited for implementation in deep-submicron CMOS. Pulse-width modulation (PWM) employs discrete amplitude levels and encodes signal information in local time-based averages, and as such can also benefit from such technologies. Additionally PWM does not suffer from quantization noise, and is well-suited for low noise applications. PWM designs, that can be applied for a range of signal bandwidth requirements, spanning several tens to hundreds of kHz are proposed. Applications for these architectures include audio systems, powerline communications and wireless communications. Design challenges and requirements that can arise in different application contexts are considered in the specification of the architectures. A common goal in the definition of the architectures is to minimize complexity of the designs. In the first part of the dissertation, a third-order self-oscillating PWM class-D amplifier for audio applications, that utilizes a hysteretic comparator is described. The design is analyzed and its THD is theoretically determined by employing an equivalent model, that relates the approach to natural sampling pulse-width modulation. The architecture eliminates the requirement for a high-quality carrier generator. A low-cost hysteresis compensation technique is utilized to enhance distortion performance at high output power levels. An implementation is presented in a 0.7um CMOS process. The design achieves a dynamic range (DR) of 116.5 dB, and a THD+N of 0.0012%, while delivering a power of 125 mW into an 8[Omega] load at 1 kHz. The THD+N is under 0.006% up to 90% of the maximum output power. The amplifier can deliver 1.45 W into the load with a THD of 5% with a 5 V power supply. The efficiency is greater than 84% for output power larger than 1 W. The area of the amplifier is 6 mm². The achieved performance indicates that the design is well-suited for high-performance audio applications. A class D line driver that utilizes a phase-locked loop (PLL) based PWM generation technique is presented next. The principle of operation, and implementation details relating to loop stability, linearity and noise performance are analyzed. An implementation is presented in a 130nm CMOS process. The amplifier can deliver 1.2 W into an 6.8[Omega] load with a 4.8 V power supply. The architecture eliminates the requirement for a high-quality carrier generator and a fast, continuous voltage comparator that are often required in PWM implementations. The design can achieve a THD of -65 dB, with a switching frequency that can be as high as 20 MHz. The peak efficiency is 83% for output power larger than 1 W, for a switching frequency of 10 MHz. The area of the amplifier is 2.25 mm². This architecture is potentially suitable for powerline applications. Finally, a phase-locked loop based PWM Cartesian transmitter with the capability to drive switched power amplifiers, such as a Class D power amplifier, is proposed. A phase-locked loop based technique is employed to generate a high-frequency PWM pulse stream centered at 1.28 GHz. The prototype is simulated in a 130 nm CMOS process, and achieves 35% peak efficiency for 17 dBm output power with a carrier frequency of 900 MHz. Operation of the architecture with non-constant envelope modulation, such as that employed in the WCDMA standard, is verified in simulation. / text

This thesis presents a measurement of the mass, natural width, and signal strength, defined as the yield normalized to the Standard Model prediction, of the Higgs boson in the \(H \rightarrow ZZ^{(*)} \rightarrow 4l\) decay channel using an approach which utilizes event-by-event detector response information. The measurement is performed on p-p collision data recorded by the ATLAS experiment at the CERN Large Hadron Collider. The data corresponds to an integrated luminosity of \(25 fb^{-1}\) with center-of-mass energies of 7 TeV and 8 TeV. The measured mass of the Higgs boson is \(m_H = 124.57_{-0.43}^{+0.48} GeV\). The signal strength was estimated at \(\mu = 1.76_{-0.37}^{+0.46}\). Finally, the natural width of the Higgs was determined to be < 2.6 GeV with 95% confidence. The event-by-event approach used in this analysis involves the parameterization of the behavior of single leptons in the ATLAS detector and the convolution of a mass response with the Higgs truth distribution to derive the reconstruction level signal model. / Physics