Global ETD Search

11	Episode 7.05 – Flipping Bits using the Bitwise Inverse and Bitwise-XOR Tarnoff, David 01 January 2020 (has links) Inverting or flipping the bits of an integer is the third and last method of “bit bashing” we will discuss. There are two ways to invert bits: either flip all of them at once or use a mask to identify which bits to flip and which to leave alone. computer organization computer design flipping bits Bitwise Inverse Bitwise-XOR Computer Sciences
12	Probability of Solvability of Random Systems of 2-Linear Equations over <i>GF</i>(2) Yeum, Ji-A January 2008 (has links) No description available. Mathematics random system Boolean equations probability of solvability random graph phase transition satisfiability XOR problem
13	Conventional verification for unconventional computing: a genetic XOR gate example Konur, Savas, Gheorghe, Marian, Dragomir, C., Ipate, F., Krasnogor, N. January 2014 (has links) No / As unconventional computation matures and non-standard programming frameworks are demonstrated, the need for formal verification will become more prevalent. This is so because “programming” in unconventional substrates is difficult. In this paper we show how conventional verification tools can be used to verify unconventional programs implementing a logical XOR gate. / SK and MG acknowledge the EPSRC support (grant number: EP/I031812/1) support; NK’s work is supported by EPSRC (grant numbers: EP/I031642/1, EP/J004111/1, EP/L001489/1). MG and FI are partially supported by CNCS UEFISCDI (grant number: PN-II-ID-PCE-2011-3-0688). CD acknowledges an EPSRC studentship.
14	A secure localization framework of RAIN RFID objects for ambient assisted living / Un système sécurisé de localisation d’objets RAIN RFID pour l’assistance et l'autonomie des personnes à domicile Khalid, Ahmad 13 November 2017 (has links) Internet des objets (IoT) est actuellement à notre portée. De nombreux domaines ont bénéficié de cette technologie. Cela va d'une application simple, comme l'identification d'un objet jusqu'à la gestion d'un système plus complexe. L'identification par radiofréquence (RFID) est l'une des technologies a une part importante dans l’IoT aujourd'hui. C’est une technologie embarqué, pas cher et ne nécessite aucune source d'alimentation supplémentaire dans le cas de tag passif. Avec sa fonctionnalité omniprésente, cette technologie permet de positionner un objet dans une zone spécifique. L’Assistance et l'Autonomie des personnes à Domicile (AAL) est l'un des nombreux domaines qui bénéficient de l'IoT. Il vise à aider les personnes âgées dans leurs routines quotidiennes en fournissant de nouveaux services d'assistance dans les maisons intelligentes (smart home). La présence de RFID dans une maison intelligente sont d'une grande aide pour une personne âgée et/ou déficiente, par exemple, pour l’aider à trouver un objet dans son environnement quotidien. Cependant, même avec tous ces avantages d’assistance dans notre vie, il est malheureusement à double tranchant où l'avantage qu'il apporte à un objet pourrait à son tour se tourner contre lui-même. En effet, pour pouvoir aider les personnes âgées à localiser un objet, le système nécessite certaines données relatives au positionnement de l'objet, tout au moins son identification. Étant donné que la couverture de l'étiquette RFID passive est très faible, une fois sa présence détectée, il est difficile de la cacher. La capacité de cette technologie à localiser des objets donne l'occasion à une tierce personne de profiter du système. Parallèlement au besoin persistant et constant de confidentialité par les utilisateurs, l'objectif de cette thèse consiste à améliorer la confidentialité dans la localisation d'un objet grâce à un nouveau protocole basé sur la deuxième génération de RFID passive. Le protocole proposé doit pouvoir empêcher un objet d'être identifié et localisé par des parties non autorisées ou par un lecteur malveillant. La première contribution de ce travail est l'évaluation de la gestion anti-collision RFID. Elle est réalisée par la création d'un modèle OMNET++, construit sur la base de la dernière norme RFID développée par GS1 et adaptée par ISO / IEC appelé Gen2V2 (RFID classe 2 Génération 2 Version 2). Dans cette norme une étiquette RFID passive ne nécessite aucune source d'alimentation interne. Il communique en utilisant la fréquence UHF. La norme Gen2V2 propose une liste de suites cryptographiques qui peuvent être utilisées comme méthodes pour authentifier une étiquette et un lecteur. Cette nouvelle génération d'étiquettes est soutenue par une alliance de fabricants appelée RAIN (RAdio frequency IdentifatioN) qui favorise l'adoption du Gen2V2. Nous évaluons les performances globales du protocole anti-collision et nous comparons ensuite quatre de ses suites cryptographiques, à savoir PRESENT80, XOR, AES128 et cryptoGPS pour garantir l’authentification lecteur/tag. Parmi les performances évaluées dans ce modèle, nous nous sommes intéressé au nombre de collisions et à la durée requise pour interroger un groupe d'étiquettes. Nous avons intégré en fonctionnalité de localisation dans le modèle en s’appuyant sur les messages échangés avant l’authentification, ce qui peut conduire à une localisation malveillante d'un objet. Pour augmenter la confidentialité de la localisation au sein des applications AAL, nous proposons donc une deuxième contribution qui est une nouvelle méthode de localisation basée sur les échanges standard Gen2V2 en anonymisant l'identité de l'étiquette. / Internet of things (IoT) is currently on our doorsteps. Numerous domains have beneted from this technology. It ranges from a simple application such as identifying an object up to handling a more complex system. The Radio Frequency IDentication (RFID) is one of the enabling technologies that drive the IoT to its position today. It is small, cheap and does not require any additional power sources. Along with its ubiquitous functionality, this technology enables the positioning of an object within a specic area. Ambient Assisted Living (AAL) is one of the many domains that benet from the IoT. It aims at assisting elderly people in their daily routines by providing new assistive services in smart homes for instance. RFIDs in a smart home come as a great help to an elderly person, for example, to nd an object that they misplaced. However, even with all its benets in simplifying our lives, it is unfortunately double-edged where the advantage that it brings to an object could in turn go against itself. Indeed to be able to help the older adults to locate an object, the system requires certain data in relation to the positioning of the object and its identication. As the passive RFID tag coverage is very small, once its presence is detected, it is dicult to hide it. The ability of this technology in localizing objects gives an opportunity to a third person to take an advantage of the system. In parallel with the persistent and constant need of privacy and secrecy by the users, the objective of this thesis consists of improving the privacy in localizing an object through a new protocol based on the latest version of the RFID second generation passive tag. The proposed protocol must be able to prevent an object from being identied and located by unauthorized parties or a malicious reader. The rst contribution of this work is the assessment of the RFID anti collision management. It is performed through the creation of an OMNET++ framework, modelled and built based on the latest RFID standard developed by GS1 and incorporated by ISO/IEC called Gen2V2 (RFID class 2 Generation 2 Version 2). It is a passive RFID tag that does not require any internal power sources to operate. It communicates using the UHF frequency. The Gen2V2 standard provides a list of cryptographical suites that can be used as a method to authenticate a tag and a reader. This new generation of tags is supported by an alliance of manufacturers called RAIN (RAdio frequency IdenticatioN) that promotes the adoption of the Gen2V2. The anti collision management overall performance is then compared with its theoretical value and four of its cryptographical suites namely PRESENT80, XOR, AES128 and cryptoGPS. Among the performances evaluated within the framework is the number of collisions and the duration required to interrogate a group of tags. Note that an addition of a localization functionality within the framework reveals that exchanged messages through wireless channel prior to the authentication can lead to a malicious localization of an object. To increase the localization privacy within AAL application, we propose therefore a second contribution which is a new localization method that is based on the current Gen2V2 standard exchanges by anonymizing the tag identity. Internet des objets - IoT Localisation Trilatération Sécurité Authentification AES128 XOR PRESENT-80 CryptoGPS Internet of Things - IoT Ambient Assisted Living - AAL Localization Trilateration - ToA Security Authentification AES128 XOR PRESENT-80 CryptoGPS
15	On The Avalanche Properties Of Misty1, Kasumi And Kasumi-r Akleylek, Sedat 01 February 2008 (has links) (PDF) The Global System for Mobile (GSM) Communication is the most widely used cellular technology. The privacy has been protected using some version of stream ciphers until the 3rd Generation of GSM. KASUMI, a block cipher, has been chosen as a standard algorithm in order to be used in 3rd Generation. In this thesis, s-boxes of KASUMI, MISTY1 (former version of KASUMI) and RIJNDAEL (the Advanced Encryption Standard) are evaluated according to their linear approximation tables, XOR table distributions and satisfaction of the strict avalanche criterion (SAC). Then, the nonlinear part, FI function, of KASUMI and MISTY1 are investigated for SAC. A new FI function is defined by replacing both s-boxes of KASUMI by RIJNDAEL&rsquo / s s-box. Calling this new version KASUMI-R, it is found to have an FI function significantly better than others. Finally, the randomness characteristics of the overall KASUMI-R for different rounds are compared to those of MISTY1 and KASUMI, in terms of avalanche weight distribution (AWD) and some statistical tests. The overall performance of the three ciphers is found to be same, although there is a significant difference in their FI functions.
16	A Dual-Port Data Cache with Pseudo-Direct Mapping Function Gade, Arul Sandeep 07 May 2005 (has links) Conventional on-chip (L1) data caches such as Direct-Mapped (DM) and 2-way Set-Associative Caches (SAC) have been widely used for high-performance uni (or multi)-processors. Unfortunately, these schemes suffer from high conflict misses since more than one address is mapped onto the same cache line. To reduce the conflict misses, much research has been done in developing different cache architectures such as 2-way Skewed-Associative cache (Skew cache). The 2-way Skew cache has a hardware complexity equivalent to that of 2-way SAC and has a miss-rate approaching that of 4-way SAC. However, the reduction in the miss-rate using a Skew cache is limited by the confined space available to disperse the conflicting accesses over small memory banks. This research proposes a dual-port data cache called Pseudo-Direct Cache (PDC) to minimize the conflict misses by dispersing addresses effectively over a single memory bank. Our simulation results show that PDC reduces those misses significantly compared to any conventional L1 caches and also achieves 10-15% lesser miss-rates than a 2-way Skew cache. SimpleScalar simulator is used for these simulations with SPEC95FP benchmark programs. Similar results were also seen over SPEC2000FP benchmark programs. Simulations over CACTI 3.0 were performed to evaluate the hardware implications of PDC over Skew cache. The simulation results show that the PDC has a simple hardware complexity similar to 2-way SAC and has 4-15% better AMAT compared to 2-way Skew cache. The PDC also reduces execution cycles significantly. Writeback rates Xor mapping functions Skewed mapping Execution time AMAT Energy consumption Data cache Miss rates Pseudo direct cache
17	Photonic logic-gates: boosting all-optical header processing in future packet-switched networks Martínez Canet, Josep Manuel 06 May 2008 (has links) Las redes ópticas de paquetes se han convertido en los últimos años en uno de los temas de vanguardia en el campo de las tecnologías de comunicaciones. El procesado de cabeceras es una de las funciones más importantes que se llevan a cabo en nodos intermedios, donde un paquete debe ser encaminado a su destino correspondiente. El uso de tecnología completamente óptica para las funciones de encaminamiento y reconocimiento de cabeceras reduce el retardo de procesado respecto al procesado eléctrico, disminuyendo de ese modo la latencia en el enlace de comunicaciones. Existen diferentes métodos de procesado de datos para implementar el reconocimiento de cabeceras. El objetivo de este trabajo es la propuesta de una nueva arquitectura para el procesado de cabeceras basado en el uso de puertas lógicas completamente ópticas. Estas arquitecturas tienen como elemento clave el interferómetro Mach-Zehnder basado en el amplificador óptico de semiconductor (SOA-MZI), y utilizan el efecto no lineal de modulación cruzada de fase (XPM) en los SOAs para realizar dicha funcionalidad. La estructura SOA-MZI con XPM es una de las alternativas más atractivas debido a las numerosas ventajas que presenta, como por ejemplo los requisitos de baja energía para las señales de entrada, su diseño compacto, una elevada relación de extinción (ER), regeneración de la señal y el bajo nivel de chirp que introducen. Este trabajo se ha centrado en la implementación de la funcionalidad lógica XOR. Mediante esta función se pueden realizar diversas funcionalidades en las redes ópticas. Se proponen dos esquemas para el reconocimiento de cabeceras basados en el uso de la puerta XOR. El primer esquema utiliza puertas en cascada. El segundo esquema presenta una arquitectura muy escalable, y se basa en el uso de un bucle de realimentación implementado a la salida de la puerta. Asimismo, también se presentan algunas aplicaciones del procesado de cabeceras para el encaminamiento de paquetes basadas en el uso d / Martínez Canet, JM. (2006). Photonic logic-gates: boosting all-optical header processing in future packet-switched networks [Tesis doctoral no publicada]. Universitat Politècnica de València. https://doi.org/10.4995/Thesis/10251/1874 / Palancia Interferometers Packet-switching All-optical Logic Gates Header/label Xor Networks Soa-mzi TEORIA DE LA SEÑAL Y COMUNICACIONES
18	Šifrování telefonních hovorů / Encrypting Landlines Phone Communication Vávra, Jakub January 2008 (has links) This master's thesis is about making draft and implementing land-line phone call encryption using FITkit. The ultimate goal is to find suitable compression and encryption methods, implement or adapt them for FITkit board and create functional solution.
19	Analysis of Accuracy for Engine and Gearbox Sensors Dogantimur, Erkan, Johnsson, Daniel January 2019 (has links) This thesis provides a standardized method to measure accuracy for engine and gearbox sensors. Accuracy is defined by ISO 5725, which states that trueness and precision need to be known to provide a metric for accuracy. However, obtaining and processing the data required for this is not straight forward. In this thesis, a method is presented that consists of two main parts: data acquisition and data analysis. The data acquisition part shows how to connect all of the equipment used and how to sample and store all the raw data from the sensors. The data analysis part shows how to process that raw data into statistical data, such as trueness, repeatability and reproducibility for the sensors. Once repeatability and reproducibility are known, the total precision can be determined. Accuracy can then be obtained by using information from trueness and precision. Besides, this thesis shows that measurement error can be separated into error caused by the sensors and error caused by the measurand. This is useful information, because it can be used to assess which type of error is the greatest, whether or not it can be compensated for, and if it is economically viable to compensate for such error. The results are then shown, where it is possible to gain information about the sensors’ performance from various graphs. Between Hall and inductive sensors, there were no superior winner, since they both have their strengths and weaknesses. The thesis ends by making recommendations on how to compensate for some of the errors, and how to improve upon the method to make it more automatic in the future. statistical analysis engine gearbox sensor sensors rotation rotational speed differential pressure performance characteristics trueness precision accuracy Hall inductive induction gauge pressure reference hysteresis bias noise linearity non-linearity DEWESoft DAQ wheel tooth teeth absolute rotary encoder matlab XOR Gray binary LabView sampling measurement measuring statistisk analys motor växellåda sensor sensorer rotation rotationell hastighet fart differentiell tryck prestanda karaktäristik trueness precision accuracy noggrannhet onoggrannhet Hall induktiv induktion tryckskillnad referens hysteres bias avstånd brus linjäritet linearitet olinear olinjär olinearitet olinjäritet DEWESoft DAQ sampling mätning hjul tand tänder absolut rotationsgivare givare matlab XOR Gray binär LabView Elektroteknik och elektronik
20	Zabezpečení vysokorychlostních komunikačních systémů / Protection of highspeed communication systems Smékal, David January 2015 (has links) The diploma thesis deals with 128–bit AES data encryption and its implementation in FPGA network card using VHDL programming language. The theoretical part explains AES encryption and decryption, its individual steps and operating modes. Further was described the VHDL programming language, development environment Vivado, FPGA network card Combo–80G and configurable framework NetCOPE. The practical part is the implementation of AES–128 in VHDL. A simulation was used to eliminate errors, then the synthesis was performed. These steps were made using Vivado software. Last step of practical part was testing of synthesized firmware on COMBO–80G card. Total of 4 projects were implemented in FPGA card. Two of them were AES encryption and decryption with ECB mode and another two describe the encryption and decryption with CBC mode.

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