This master thesis presents a comparative analysis of the starting performance and losses at rated operation for a 15 kW, 4-pole industrial induction motor, mounted with standard skewed, unskewed and unskewed asymmetrical die-cast aluminium rotors through measurements and simulations. It is a well-known fact that rotor skewing suppresses the synchronous torques at low speeds and also reduces the audible noise of the machine. However, the casting process results in a low resistive path between the rotor bars and the iron laminations, for skewed rotors, this promotes the flow of inter-bar currents. These currents, flowing between the rotorbars, increase the harmonic torques during a start and create additional losses at rated operation. For standard unskewed rotors, these losses are ideally zero, but these rotors may produce high audible noise. Studies have shown that rotors with asymmetrical rotor slot pitch can reduce the audible noise level in unskewed machines. By removing the skew, the inter-bar current losses are suppressed to a negligible level; ultimately increased machine efficiency is obtained. In this work the electrical performance is verified through measurements on the built prototypes. Direct-on-line starts and rated performance for motors with different rotor slot arrangements is simulated using 2D FEM tool FCSmek. The three prototypes are tested in the laboratory according to IEC 60034-2-1 standard and the simulation results are in good agreement with the measured results. An additional test for the measurement of high frequency delta connected stator winding currents for each prototype machine is also performed, in order to study the losses induced in the stator winding. Results have shown that by introducing the proposed asymmetry in the rotor slots, the synchronous torques at low speeds are suppressed effectively, thus, improving the starting performance of the asymmetrical rotor compared to the standard unskewed rotor. Additionally, a higher pull-out torque is obtained for the unskewed rotor motor compared to the standard skewed rotor motor. However, the losses were more or less re-distributed in the unskewed rotor motor, resulting in similar efficiency as the standard skewed rotor motor. One important observation is that; to capture the inter-bar current losses which are estimated to be 5.5% of the total losses, requires more accurate methods of measurements than the existing. And sufficient repeatability must be achieved; alternatively one should rely on statistical data obtained from measurements on several number of motors.

The modulation methods Space Vector PWM (SVPWM), Discontinuous PWM (DPWM1, DPWMMAX) and six-step mode are investigated in the overmodulation range of a voltage-fed induction motor drive. This area enables an increase of inverter output voltage so that drive performance can be enhanced. Though, pulse dropping occurs which results in increased iron losses and current waveform quality degradation. Due to differences in harmonic distortion the modulation methods cause various torque oscillations and power losses in induction motors and inverter drives. To quantify these effects in a squirrel cage induction motor drive a simulation model containing a finite element machine model and an analytic inverter model is developed, in order to find the PWM scheme offering maximum torque and minimal power losses. Additionally, the holistic investigation of machine and inverter losses allows for making statements concerning total losses of drive systems and the most suitable overmodulation scheme for the application.

For predicting the performance characteristics of highly utilized induction machines, commonly finite element analysis (FEA) is applied. If only the stationary behavior is of interest, both time-harmonic and transient calculations are feasible. Both procedures offer benefits and drawbacks regarding precision and computing time. In this paper the stationary torque-slip-characteristic of a squirrel cage induction machine for electric vehicle application is calculated by means of time-harmonic and transient FEA. The simulation results are compared to measurements taken on the test bench. For low saturation levels the time-harmonic and transient simulation produce nearly equivalent stationary torque results. For high saturation levels, the commonly used approach for nonlinear time-harmonic calculation is to use a corrected magnetization curve. It is shown that the assumption of sinusoidal time variation of the magnetic field strength usually made in this case results in a torque error increasing with the saturation level for the time-harmonic calculation.

付記する学位プログラム名: 京都大学卓越大学院プログラム「先端光・電子デバイス創成学」 / 京都大学 / 新制・課程博士 / 博士(工学) / 甲第25293号 / 工博第5252号 / 新制||工||1999(附属図書館) / 京都大学大学院工学研究科電気工学専攻 / (主査)教授 松尾 哲司, 教授 引原 隆士, 教授 土居 伸二 / 学位規則第4条第1項該当 / Doctor of Agricultural Science / Kyoto University / DFAM

Multilevel inverter technology has emerged recently as a very important alternative in the area of high-power medium-voltage energy control. Voltage operation above semiconductor device limits, lower common mode voltages, near sinusoidal outputs together with small dv/dt’s, are some of the characteristics that have made this power converters popular for industry and modern research. However, the existing solutions suffer from some inherent drawbacks like common mode voltage problem, DC-link capacitor voltage fluctuation etc. Cascaded multi-level inverter with open-end winding induction motor structure promises significant improvements for high power medium-voltage applications. This dissertation investigates such cascaded multi-level inverters for open-end winding induction motor drive with reduced switch count. Similar to the conventional two-level inverters, other multi-level inverters with PWM control generate alternating common mode voltage (CMV). The alternating common mode voltage coupled through the parasitic capacitors in the machine and results in excessive bearing current and shaft voltage. The unwanted shaft voltage may cross the limit of insulation breakdown voltage and cause motor failure. This alternating common mode voltage adds to the total leakage current through ground conductor and acts as a source of conducted EMI which can interfere with other electronic equipments around. As the number of level increase in the inverter, different voltage levels are made available by using DC-link capacitor banks, instead of using different isolated power supplies. The intermediate-circuit capacitor voltages which are not directly supplied by the power sources are inherently unstable and require a suitable control method for converter operation, preferably without influence on the load power factor. Apart from normal operation, the sudden fault conditions may occur in the system and it is necessary to implement the control strategy considering this condition also. A five-level inverter topology with cascaded power circuit structure is proposed in this dissertation with the strategy to eliminate the common mode voltage and also to maintain the balance in the DC-link capacitor voltages. The proposed scheme is based on a dual five-level inverter for open-end winding induction motor. The principle achievement of this work is the reduction of power circuit complexity in the five-level inverter compared to a previously proposed five-level inverter structure for open-end winding IM drive with common mode voltage elimination. The reduction in the number of power switching devices is achieved by sharing the two two-level inverters for both the inverter structures. The resultant inverter structure can produce a nine-level voltage vector structure with the presence of alternating common mode voltage. The inverter structure is formed by cascading conventional two-level inverters together with NPC three-level inverters. Thus it offers modular and simpler power bus structure. As the power circuit is realised by cascading conventional two-level and NPC three-level inverters the number of power diodes requirements also reduced compared to the conventional NPC five-level inverters. The present proposed structure is implemented for the open-end winding induction motor and the power circuit offers more number of switching state redundancies compared to any conventional five-level inverter. The inverter structure required half the DC-link voltage compared to the DC-link voltage required for the conventional five-level inverter structure for induction motor drive and this reduces the voltage stress on the individual power devices. The common mode voltage is eliminated by selecting only the switching states which do not generate any common mode voltage in pole voltages hence there will be no common mode voltage at the motor phase also. The technique of using the switching state selection for the common mode voltage elimination, cancels out the requirement of the filter for the same purpose. As the inverter output is achieved without the presence of common mode voltage, the dual inverter can be fed from the common DC-link sources, without generating any zero sequence current. Hence the proposed dual five-level inverter structure requires only four isolated DC supplies. The multi-level inverters supplied by single power supply, have inherent unbalance in the DC-link capacitor voltages. This unbalance in the DC-link capacitor voltages causes lower order harmonics at the inverter output, resulting in torque pulsation and increased voltage stress on the power switching devices. A five-level inverter with reduced power circuit complexity is proposed to achieve the dual task of eliminating common mode voltage and DC-link capacitor voltage balancing. The method includes the analysis of current through the DC-link capacitors, depending on the switching state selections. The conditions to maintain all the four DC-link capacitor voltages are analysed. In an ideal condition when there is no fault in the power circuit the balance in the capacitor voltages can be maintained by selecting switching states in consecutive intervals, which have opposite effect on the capacitor voltages. This is called the open loop control of DC-link capacitor voltage balancing, since the capacitor voltages are not sensed during the selection of the switching states. The switching states with zero common mode voltages are selected for the purpose of keeping the capacitor voltages in balanced condition during no fault condition. The use of any extra hardware is avoided. The proposed open loop control of DC-link capacitor voltage balancing is capable of keeping the DC-link capacitor voltages equal in the entire modulation region irrespective of the load powerfactor. The problem with the proposed open loop control strategy is that, it can not take any corrective action if there is any initial unbalance in the capacitor voltages or if any unbalance occurs in the capacitor voltages during operation of the circuit,. To get the corrective action in the capacitor voltages due occurrence of any fault in the circuit, the strategy is further improved and a closed loop control strategy for the DC-link capacitor voltages is established. All the possible fault conditions in the four capacitors are identified and the available switching states are effectively used for the corrective action in each fault condition. The strategy is implemented such a way that the voltage balancing can be achieved without affecting the output fundamental voltage. The proposed five-level inverter structure presented in this thesis is based on a previous work, where a five-level inverter structure is proposed for the open-end winding induction motor. In that previous work 48 switches are used for the realization of the power circuit. It is observed that all the available switching states in this previous work are not used for any of the performance requirement of CMV elimination or DC-link voltage balancing. So, in this proposed work, the power circuit is optimized by reducing some of the switches, keeping the performance of the inverter same as the power circuit proposed in the previous work. The five-level inverter proposed in this thesis used 36 switches and the number of switching states is also reduced. But, the available switching states are sufficient for the CMV elimination and DC-link capacitor voltage balancing. The advantage of the modular circuit structure of this proposed five-level inverter is further investigated and the inverter structure is modified to a seven-level inverter structure for the open end winding induction motor. The proposed power circuit of the seven-level inverter uses only 48 switches, which is less compared to any seven-level inverter structure for the open end winding induction motor with common mode voltage elimination. The power circuit is reduced by sharing four two-level inverters to both the individual seven-level inverters in both the sides of the of the open end winding induction motor. The cascaded structure eliminates the necessity of the power diodes as required by the conventional NPC multilevel inverters. The proposed seven-level inverter is capable of producing a thirteen-level voltage vector hexagonal structure with the presence of common mode voltage. The common mode voltage elimination is achieved by selecting only the switching states with zero common mode voltage from both the inverters and the combined inverter structure produce a seven-level voltage vector structure with zero common mode voltage. The switching frequency is also reduced for the seven-level inverter compared to the proposed five-level inverter. The advantage of this kind of power circuit structure is that the number of power diode requirement is same in both five-level and seven-level inverters. Since there is no common mode voltage in the output voltages, the dual seven-level inverter structure can be implemented with the common DC-link voltage sources for both the sides. Six isolated power supplies are sufficient for both the seven-level inverters. The available switching states in this proposed seven-level inverter are further analysed to implement the open loop and closed loop capacitor voltage balancing and this allow the power circuit to run with only three isolated DC supplies. All the proposed work presented in this thesis are initially simulated in SIMULINK toolbox and then implemented in a form of laboratory prototype. A 2.5KW open end winding induction motor is used for the implementation of these proposed works. But all these work general in nature and can be implemented for high power drive applications with proper device ratings.

In DC to AC power conversion, voltage source inverters (VSI) based current controllers are usually preferred for today’s high performance AC drive which requires excellent dynamic and steady state performances at different transient and load conditions, with the additional advantages like inherent short circuit and over current protection. Out of different types of current controllers, hysteresis controllers are widely used due to their simplicity and ability to meet the requirements for a high performance AC drives. But the conventional hysteresis controllers suffers from wide variation of PWM switching frequency, overshoot in current errors, sub-harmonic components in the current waveform and non-optimum switching at different operating point of the drive system. To mitigate these problems, particularly to control the switching frequency variation, which is the root cause of all other problems, several methodologies like ramp comparison based controller, predictive current controller, etc. were proposed in the literature. But amplitude and phase offset error in the ramp comparison based controllers and complexities involved in the predictive controllers have limited the use of these controllers. Moreover, these type of controllers, which uses three separate and independently controlled tolerance band (sinusoidal type or adaptive) to control the 3-phase currents, shows limited dynamic responses and they are not simple to implement. To tackle the problem of controlling 3-phase currents simultaneously, space vector based hysteresis current controller is very effective as it combines the current errors of all the three phases as a single entity called current error space vector. It has a single controller’s logic with a hysteresis boundary for controlling this current error space vector. Several papers on space vector based hysteresis controllers for 2-level inverter with constant switching frequency have been published, but the application of the constant switching frequency based hysteresis current controllers for multi¬level inverter fed drive system, has not been addressed properly. Use of multi-level inverter in modern high performance drive for medium and high voltage levels is more prominent because of multi-level’s inherent advantages like good power quality, good electromagnetic compatibility (EMC), better DC link voltage utilization, reduced device voltage rating, so on. Even though some of the earlier works describe three-level space vector based hysteresis current controller techniques, they are specific to the particular level of inverters and does not demonstrate constant switching frequency of operation. This thesis proposes a novel approach where nearly constant switching frequency based hysteresis controller can be implemented for any general n-level inverter and it is also independent of inverter topology. In this work, varying parabolic boundary is used as the hysteresis current error boundary for controlling the current in a multi-level space vector structure. The computation of the parabolic boundary is accomplished offline and all the necessary boundary parameters at different operating points are stored in the look-up tables. The varying parabolic boundary for the multi-level space vector structure depends on the sampled reference phase voltage values which are estimated from stator current error information and then using the equivalent circuit model of induction motors. Here, a mapping technique is adopted to bring down all the three phase references to the inner- most carrier region, which results in mapping any outer triangular structure where tip of the voltage space vector is located, to one of the sectors of the inner most hexagon of the multi-level space vector structure. In this way, the required mapped sector information is easily found out to fix the correct orientation of the parabolic boundary in the space vector plane. This mapping technique simplifies the controller’s logic similar to that of a 2-level inverter. For online identification of the inverter switching voltage vectors constructing the present outer triangle of the multi-level space vector structure, the proposed controller utilizes the sampled phase voltage references. This identification technique is novel and also generic for any n-level inverter structure. This controller is having all the advantages of a space vector based hysteresis current controller and that of a multi-level inverter apart from having a nearly constant switching frequency spectrum similar to that of a voltage controlled space vector PWM (VC-SVPWM). Using the proposed controller, simulation study of a five-level inverter fed induction motor (IM) drive scheme, was carried out using Matlab-Simulink. Simulation study showed that the switching frequency variations in a fundamental cycle and over the entire speed range of the linear modulation region, is similar to that of a VC-SVPWM based multi-level VSI. The proposed hysteresis controller is experimentally verified on a 7.5 kW IM vector control drive fed with a five-level VSI. The proposed current error space vector based hysteresis controller providing nearly constant switching frequency is implemented on a TI TMS320LF2812 DSP and Xilinx XC3S200FT256 FPGA based platform. The three-phase reference currents are generated depending on the frequency command and the controller is tested with the drive for the entire operating speed range of the machine in forward and reverse directions. Steady state and quick transient results of the proposed drive are presented in this thesis. This thesis also proposes another type of hysteresis controller, firstly for 2-level inverter and then for general n-level multi-level inverter, which eliminates the parabolic boundary and replaces it with a boundary which is computed online and does not use any look up table for boundary selection. The current error boundary for the proposed hysteresis controller is computed online in a very simple way, using the information of estimated fundamental stator voltages along α and β axes of space vector plane. The method adopted for the proposed controller to compute the boundary does not involve any complicated computations and it selects the optimal vector for switching when current error space vector crosses the boundary. This way adjacent voltage vector switching similar to VC-SVPWM can be ensured. For 2-level inverter, it precisely determines the sector, in which reference voltage vector is present. In multi-level inverter, this controller also finds out the mapped sector information using the same mapping techniques as explained in the first part of this thesis. In both 2-level and multi-level inverter, the proposed controller does not use any look up table for finding individual voltage vector switching times from the estimated voltage references. These switching times are used for the computation of hysteresis boundary for individual vectors. Thus the hysteresis boundary for individual vectors is exactly calculated and the boundary is similar to that of VC-SVPWM scheme for the respective levels of inverter. In the present scheme, the phase voltage harmonic spectrum is very close to that of a constant switching frequency VC-SVPWM inverter. In this thesis, at first, the proposed on line boundary computation scheme is implemented for a 2-level inverter based controller for the initial study, so that it can be executed as fast as 10 µs in a DSP platform, which is required for accurate current control. Then the same algorithm of 2-level inverter is extended for multi-level inverter with the additional logic for online identification of nearest switching voltage vectors (also used in the parabolic boundary case) for the present sampling interval. Previously mentioned mapping technique for multi-level inverter, is also implemented here to bring down the phase voltage references to the inner-most carrier region to realize the multi-level current control strategy equivalent to that of a 2-level inverter PWM current control. Simulation study to verify the steady state as well as transient performance of the proposed controller for both 2-level as well as five-level VSI fed IM drive is carried out using Simulink tool box of MATLAB Simulation Software. The proposed hysteresis controllers are experimentally verified on a 7.5 kW IM vector control drive fed with a two-level VSI and five-level VSI separately. The proposed current error space vector based hysteresis controller providing nearly constant switching frequency profile for phase voltage is implemented on the TI TMS320LF2812 DSP and Xilinx XC3S200FT256 FPGA based platform. The three-phase reference currents are generated depending on the frequency command and the proposed hysteresis controllers are tested with drive for the entire operating speed range of the machine in forward and reverse directions. Steady state and transient results of the proposed drive are also presented for different operating conditions, through the simulation study followed by experimental verifications. Even though the simulation and experimental verifications are done on a 5-level inverter to explain the proposed hysteresis controller, it can be easily implemented for any general n-level inverter, as described in this thesis.

MULTILEVEL inverters are the preferred choice of converters for electronic power conversion for high power applications. They are gaining popularity in variety of industrial applications including electric motor drives, transportation, energy management, transmission and distribution of power. A large portion of energy conversion systems comprises of multilevel inverter fed induction motor drives. The multilevel inverters are ideal for such applications, since the switching frequency of the devices can be kept low. In conventional two level inverters, to get nearly sinusoidal phase current waveform, the switching frequency of the inverter is increased and the harmonics in the currents are pushed higher in the frequency spectrum to reduce the size and cost of the filters. But higher switching frequency has its own drawbacks – in particular for medium voltage, high power applications. They cause large dv_/ dt stresses on the motor terminals and the switching devices, leading to increased electromagnetic interference (EMI) problems and higher switching losses. Harmonics in the motor currents can further be minimized by adopting dodecagonal voltage space vector (SV) switching (12-sided polygon). In case of dodecagonal SV switching, the fifth and seventh order (6n , 1, n = odd) harmonics are completely eliminated for the full modulation range including over modulation and twelve step operation in the motor phase voltages and currents. In addition to low order harmonic current suppression, the linear modulation range for dodecagonal SV switching is also more by 6% when compared to that of the conventional hexagonal SV switching. The dodecagonal voltage SV structure is made possible by connecting two inverters with DC-link voltages Vd and 0:366Vd on either side of an open-end winding induction motor. The dodecagonal space vector switching can be used to produce better quality phase voltage and current waveforms and overcome the problem of low order fifth and seventh harmonic currents and to improve the range for linear modulation while reducing the switching frequency of the inverters when compared to that of the conventional hexagonal space vector based inverters. This thesis focuses on three aspects of multilevel dodecagonal space vector structures (i) Two new power circuit topologies that generate a multilevel dodecagonal voltage space vector structure with symmetric triangles, (ii) A multilevel dodecagonal SV structure with nineteen concentric dodecagons, (iii) Pulse width modulation (PWM) timing calculation methods for a general N-level dodecagonal SV structure. (i) Two new power circuit topologies capable of generating multilevel dodecagonal voltage space vector structure with symmetric triangles with minimum number of DC link power supplies and floating capacitor H-bridges are proposed. The first power topology is composed of two hybrid cascaded five level inverters connected to either side of an open end winding induction machine. Each inverter consists of a three level neutral point clamped (NPC) inverter, cascaded with an isolated capacitor fed H-bridge making it a five level inverter. The second topology is a hybrid topology for a normal induction motor (star or delta connected), where the power is fed to the motor only from one side. The proposed scheme retains all the advantages of multilevel topologies as well the advantages of the dodecagonal voltage space vector structure. Both topologies have inherent capacitor balancing for floating H-bridges for all modulation indices including transient operations. The proposed topologies do not require any pre-charging circuitry for startup. PWM timing calculation method for space vector modulation is also explored in this chapter. Due to the symmetric arrangement of congruent triangles within the voltage space vector structure, the timing computation requires only the sampled reference values and does not require any iterative searching, off-line computation, look-up tables or angle estimation. Experimental results for steady state operation and transient operation are also presented to validate the proposed concept. (ii) A multilevel dodecagonal voltage space vector structure with nineteen concentric do-decagons is proposed for the first time. This space vector structure is achieved by connecting two sets of asymmetric hybrid five level inverters on either side of an open-end winding induction motor. The dodecagonal structure is made possible by proper selection of DC-link voltages and switching states of the inverters. In addition to that, a generic and simple method for calculation of PWM timings using only sampled reference values (v and v ) is proposed. This enables the scheme to be used for any closed loop application like vector control. Also, a new switching technique is proposed which ensures minimum switching while eliminating the fifth and seventh order harmonics and suppressing the eleventh and thirteenth harmonics, eliminating the need for bulky filters. The motor phase voltage is a 24-stepped waveform for the entire modulation range thereby reducing the number of switchings of the individual inverter modules. Experimental results for steady state operation, transient operation including start-up have been presented and the results of Fast Fourier Transform (FFT) analysis is also presented for validating the proposed concept. (iii) A method to obtain PWM timings for a general N-level dodecagonal voltage space vector structure using only sampled reference values is proposed. Typical methods that are used to find PWM timings for dodecagonal SV structures use modulation index and the reference vector angle, to get the timings T1 and T2 using trigonometric calculations. This method requires look-up tables and is difficult to implement in closed loop systems. The proposed method requires only two additions to compute these timings. For multilevel case, typical iterative methods need timing calculations (matrix multiplications) to be performed for each triangle. The proposed method is generic and can be extended to any number of levels with symmetric structures and does not require any iterative searching for locating the triangle in which the tip of the reference vector lies. The algorithm outputs the triangle number and the PWM timing values of T0, T1 and T2 which can be set as the compare values for any carrier based PWM module to obtain space vector PWM like switching sequences. Simulation and experimental results for steady state and transient conditions have been presented to validate the proposed method. A 3.7 kW, 415 V, 50 Hz, 4-pole open-end winding induction motor was used for the experimental studies. The semiconductor switches that were used to realize the power circuit for the experiment were 75 A, 1200 V insulated-gate bipolar transistor (IGBT) half-bridge modules (SKM75GB12T4). Opto-isolated gate drivers with desaturation protection (M57962L) were used to drive the IGBTs. For the speed control and PWM timing computation a digital signal processor (DSP-TMS320F28335) with a clock frequency of 150 MHz was used. For modulation frequencies 10 Hz and below, a constant sampling frequency of 1 kHz was used as the frequency modulation ratio is high. For modulation frequencies above 10 Hz, synchronous PWM strategy was used. The time duration Ts is the sampling interval for which the timings T1 , T2 and T0 are calculated. As in the case of any synchronous PWM method, the duration of sampling time (Ts) is a function of the fundamental frequency of the modulating signal. In this case, Ts = 1_.fm • 12n) sec. where fm is fundamental frequency in Hertz and ‘n’ is the number of samples per 30ý dodecagonal sector. The PWM timings and the triangle data (from the DSP) is fed to field programmable gate array (FPGA) (SPARTAN XC3S200) clocked at 50 MHz where the actual gating pulses are generated. The capacitor balancing algorithm and the dead-time modules were implemented within FPGA. No external hardware was used for generation of dead-time. The dead-time block generates a constant dead-time of 2 s for all the switches. Extensive testing was done for steady state operations and transient operations including quick acceleration and start-up to validate the proposed concepts. With the advantages like extension of linear modulation range, elimination of fifth and seventh harmonics in phase voltages and currents for the full modulation range, suppression of eleventh and thirteenth harmonics in phase voltages and currents, reduced device voltage ratings, lesser dv_dt stresses on devices and motor phase windings, lower switching frequency, inherent cascaded H-bridge (CHB) capacitor balancing, the proposed space vector structures, the inverter power circuit topologies, the switching techniques and the PWM timing calculation methods can be considered as viable schemes for medium voltage, high power motor drive applications.

The electrification era has been marked up by an increase in volume of electric vehicles which are directly or indirectly powered by electricity. Railways, roadways and airways are being electrified as we speak at their own respective rate. In addition to that upcoming concepts for transport solution such as hyperloop also described as the fifth mode of transportation will be electrified. The current thesis work is based on developing the model and control of the propulsion system of a scaled Hyperloop pod designed by student team KTH Hyperloop representing KTH. The team competes in Hyperloop competition organized by Spacex and the goal is to achieve the highest possible speed in a given distance and track designed by SpaceX. In order to achieve the goal of being the fastest, the scaled pod uses a Double Sided Linear Induction Motor (DSLIM) as mentioned in the subsequent chapter. The motor modelling is done on Simulink and is similar to a rotary induction motor (RIM). However the presence of end effect in DSLIM makes it different from RIM and has been discussed subsequently. The control strategy uses a synchronous frame PI control for the current control and sensor based speed control for controlling the speed of the pod.The speed control output is a reference current which is used as an input to the current controller which finally gives voltage as the control output. The corresponding bandwidth for the various loops have been calculated based on motor parameters as discussed in the method section. The validation of the motor model and the corresponding controller has been discussed in the result section, where the accuracy of the controller for the designed modelled is discussed. / Elektrifieringstiden har präglats av en ökning i volym av elfordon som direkt eller indirekt drivs med el. Järnvägar, vägar och luftvägar elektrifieras just nu med deras respektive takt. Utöver det kommer kommande koncept för transportlösning som hyperloop som också beskrivs som det femte transportsättet att elektrifieras. Detta examensarbete bygger på att utveckla modellen och regleringen av framdrivningssystemet för en nedskalad Hyperloop-pod utvecklad av studentteamet KTH Hyperloop som representerar KTH. Teamet tävlar i Hyperloop-tävlingen organiserad av SpaceX och målet är att uppnå högsta möjliga hastighet på ett visst avstånd och spår framtaget av SpaceX. För att uppnå målet om att vara snabbast använder den nedskalade podden en dubbelsidig elektrisk linjär induktionsmotor (DSLIM) som nämns i det följande kapitlet. Den elektriska motormodelleringen görs i Simulink och liknar en roterande induktionsmotor(RIM). Men närvaron av ’end effect’ i DSLIM gör den annorlunda än RIM och har diskuterats därefter. Styrstrategin använder en synkron ram-PI-styrning för strömstyrning och sensorbaserad hastighetsreglering för att styra hastigheten på podden. Varvtalsstyrningsutgången är en referensström som används som en ingång till den nuvarande styrenheten som slutligen ger spänning som slutling styrning. Motsvarande bandbredd för de olika slingorna har beräknats baserat på elektriska motorparametrar som diskuterats i metodavsnittet.Valideringen av elmotormodellen och motsvarande styrenhet har diskuterats i resultatsektionen, där noggrannheten hos styrenheten för den konstruerade modellerna diskuteras.

Nowadays, three-phase induction motors are widely used on industrial and other types of processes. Therefore, accurate knowledge of an induction motor performance is very essential to have an idea of its operation conditions. This study is a sequel of a previous one, where Direct and Soft starting methods of three-phase motors has been simulated and compared. As in the previous study, the theory behind this one is based on representing the real motor by aset of equations and values in Matlab, forming a corresponding idealistic motor in a way where all the physical effects are similar. The motor is started under three different frequencies in the VVVF method using supporting simulation of the current, torque, speed,efficiency and power factor curves. The results of the three starting methods are then discussed and compared. / Numera är tre-fas asynkronmotorer i stor utsträckning på industriella och andra typer av processer. Därför är det mycket viktigt att ha exakt kunskap om en induktionsmotorprestanda för att ha en uppfattning om dess driftsförhållanden . Denna studie är en fortsättning av en tidigare, där direkt och mjukstart metoder för trefasmotorer har simulerats och jämförts. Såsom i den tidigare studien, är teorin bakom denna en baserat på representerar den verkligamotorn av en uppsättning ekvationer och värden i Matlab, som bildar en motsvarande ideell motor på ett sätt där alla de fysiska effekterna är likartade . Motorn startas under tre olika frekvenser i VVVF metod med stöd simulering av ström, vridmoment, hastighet, effektivitetoch effektfaktorn kurvor. Därefter, resultaten av de tre startmetoder diskuteras och jämföras. / في الوقت الحالي تستخدم المحركات التحريضية ثلاثية الطور بشكل واسع في التطبيقات الصناعية و غيرها. و لهذا فإن المعرفة الدقيقة بأداء المحرك التحريضي أساسية لإعطاء فكرة عن ظروف تشغيله. إن هذه الدراسة هي تتمة لدراسة سابقة حيث تمت محاكاة و مقارنة طريقتي الإقلاع المباشر و الناعم للمحرك التحريضي ثلاثي الطور. كما في الدراسة السابقة, فإن هذه الدراسة مبنية على تمثيل المحرك الحقيقي بمجموعة من المعادلات و القيم الاسمية في برنامج ماتلاب لتكوين محرك مثالي مطابق, بحيث تكون جميع الآثار الفيزيائية مماثلة للمحرك الحقيقي. يتم إقلاع المحرك عند ثلاث ترددات مختلفة بطريقة تغيير التردد و التوتر و يتم محاكاة هذا الإقلاع عبر منحنيات التيار، العزم، السرعة، المردود و عامل الاستطاعة ثم تقارن نتائج طرق الإقلاع الثلاثة.

Šiame baigiamajame darbe tiriamas elektriškai ir magnetiškai dvipusio tiesiaeigio asinchroninio variklio (TAV) valdymo būdas, keičiant vieno iš induktorių maitinimo įtampos fazę kito induktoriaus maitinimo įtampos fazės atžvilgiu. Įvade suformuluotas darbo tikslas ir paminėtos TAV taikymo galimybės. Atlikta literatūros šaltinių analizė ir apžvelgti tiesiaeigiai asinchroniniai varikliai bei jų konstrukcijos. Pateikti šių variklių privalumai, trūkumai ir panaudojimo sritys. Teorinėje dalyje išanalizuotos tiesiaeigės stūmiklių pavaros ir apžvelgti specialūs tiesiaeigių variklių valdymo būdai. Išanalizuotos statinės charakteristikos ir sudaryta skaičiavimo metodika. Tiriamojoje dalyje sudarytas TAV modelis ir imituotos dinaminės charakteristikos. Pagamintas ir išbandytas TAV bandymų stendas, pateiktos išvados. Pasiūlyta tiesiaeigės stūmiklio pavaros funkcinė ir elektrinė principinė schemos. Darbą sudaro 7 dalys: įvadas, literatūros analizė, tyrimo tikslas ir uždaviniai, tiriamoji dalis eksperimentinė dalis, tyrimo rezultatų apibendrinimas, literatūra ir kt. šaltiniai. Darbo apimtis – 70 p. teksto be priedų, 49 iliustr., 3 lent., 24 bibliografiniai šaltiniai. / Electrically and magnetically control mode of two-sided linear induction motor (LIM) is analysed in this thesis. It is done by changing one of the voltage power supply inductor phase regard to next phase inductor. The main goal of thesis and LIM application possibilities are formulated in introduction. Literature review and analysis of linear induction motors and their construction was accomplished. The use of energy, main advantages and disadvantages of these motors were represented. Special control techniques, analysis of linear pushing drives and linear motors were analysed in theoretical section. LIM static characteristics and calculation methodology is provided in this section either. In the research section consist of LIM mathematical model, where dynamic characteristics are simulated. The actual LIM model was made and tested, experiment conclusions were written. The linear spindle drive functional and electrical diagrams were proposed. The work consists of seven sections: introduction, literature review, the study of aims and objectives, experimental section, investigating LIM and providing results, literature and others sources. Work size - 70 p. text without appendixes, 49 pictures., 3 tables., 24 bibliographic sources.