Os Sistemas Supervisórios (SS) executam diversas funções vitais em um processo automatizado e também operam como interface homem-máquina. Os mesmos recebem informações de dispositivos como Controladores Lógicos Programáveis (CLP), inversores de freqüência, etc, e ao mesmo tempo enviam parâmetros de controle fornecidos pelos operadores do processo aos equipamentos de controle. Na operação de SS, a atuação correta e a experiência dos operadores humanos é portanto também vital no controle do processo automatizado. Em recente trabalho(Andrade-2001) de pesquisa na Escola Politécnica da USP foi desenvolvido um Sistema Especialista para operar em tempo real com Sistemas Supervisórios para auxiliar na tomada de decisão dos operadores do sistema. Ao longo do tempo de operação de uma planta automatizada ocorrem novas situações que passam a compor os novos cenários do sistema e também contribuem para o aumento do conhecimento e da experiência dos operadores humanos. Assim sendo, Sistemas Especialistas constantemente devem ser atualizados com novas regras para atender às novas demandas da planta automatizada. Este trabalho de pesquisa apresenta os resultados obtidos com o Sistema Especialista desenvolvido para operar em tempo real com Sistemas Supervisórios, como também o andamento das pesquisas no campo de aprendizado de máquina e mineração de dados com o objetivo de desenvolver e de habilitar Sistemas Especialistas que operam em tempo real com a capacidade de aprender conforme ocorrem eventos durante o funcionamento de uma planta industrial automatizada. / Supervision systems ( SS ) perform diverse vital functions in an automated process and also operate as a man machine interface. The SS receive informations from devices as programmable logical Controllers (PLC), frequency inverters , etc, and at the same time send parameters of control supplied by the process users to the control equipment. In the SS operation, the correct actions and the experience of the human users are therefore vital in the control of the automated process. In a recent research work(Andrade-2001) of the USP Polytechnic School an Expert System was developed to interact in real time with a SS aiming to help in the decision-making process of the system users. During the operation time of an automated plant new situations occur, which come to compose the new system settings and also contribute to the increasing of the human users\' knowledge and experience. Thus, Expert Systems should be constantly brought up to date with these new rules for attend the new demands of the automated plant. This research work shows the results obtained by the expert system, developed to operate in real time with the supervisory systems. It also shows the course of the researches in the fields of machine learning and data mining with the objective of developing and enabling Expert Systems that operate in real time with the capacity to learn events as they happen during the operation of an automated industrial plant.

To achieve the goal of efficient ”anytime, anywhere” communication, it is essential to develop mobile devices which can efficiently support multiple wireless communication standards. Also, in order to efficiently accommodate the further evolution of these standards, it should be possible to modify/upgrade the operation of the mobile devices without having to recall previously deployed devices. This is achievable if as much functionality of the mobile device as possible is provided through software. A mobile device which fits this description is called a Software Defined Radio (SDR). Reconfigurable hardware-based solutions are an attractive option for realizing SDRs as they can potentially provide a favourable combination of the flexibility of a DSP or a GPP and the efficiency of an ASIC. The work presented in this thesis discusses the development of efficient reconfigurable hardware for one of the most energy-intensive functionalities in the mobile device, namely, Forward Error Correction (FEC). FEC is required in order to achieve reliable transfer of information at minimal transmit power levels. FEC is achieved by encoding the information in a process called channel coding. Previous studies have shown that the FEC unit accounts for around 40% of the total energy consumption of the mobile unit. In addition, modern wireless standards also place the additional requirement of flexibility on the FEC unit. Thus, the FEC unit of the mobile device represents a considerable amount of computing ability that needs to be accommodated into a very small power, area and energy budget. Two channel coding techniques have found widespread use in most modern wireless standards -namely convolutional coding and turbo coding. The Viterbi algorithm is most widely used for decoding convolutionally encoded sequences. It is possible to use this algorithm iteratively in order to decode turbo codes. Hence, this thesis specifically focusses on developing architectures for flexible Viterbi decoders. Chapter 2 provides a description of the Viterbi and turbo decoding techniques. The flexibility requirements placed on the Viterbi decoder by modern standards can be divided into two types -code rate flexibility and constraint length flexibility. The code rate dictates the number of received bits which are handled together as a symbol at the receiver. Hence, code rate flexibility needs to be built into the basic computing units which are used to implement the Viterbi algorithm. The constraint length dictates the number of computations required per received symbol as well as the manner of transfer of results between these computations. Hence, assuming that multiple processing units are used to perform the required computations, supporting constraint length flexibility necessitates changes in the interconnection network connecting the computing units. A constraint length K Viterbi decoder needs 2K−1computations to be performed per received symbol. The results of the computations are exchanged among the computing units in order to prepare for the next received symbol. The communication pattern according to which these results are exchanged forms a graph called a de Bruijn graph, with 2K−1nodes. This implies that providing constraint length flexibility requires being able to realize de Bruijn graphs of various sizes on the interconnection network connecting the processing units. This thesis focusses on providing constraint length flexibility in an efficient manner. Quite clearly, the topology employed for interconnecting the processing units has a huge effect on the efficiency with which multiple constraint lengths can be supported. This thesis aims to explore the usefulness of interconnection topologies similar to the de Bruijn graph, for building constraint length flexible Viterbi decoders. Five different topologies have been considered in this thesis, which can be discussed under two different headings, as done below: De Bruijn network-based architectures The interconnection network that is of chief interest in this thesis is the de Bruijn interconnection network itself, as it is identical to the communication pattern for a Viterbi decoder of a given constraint length. The problem of realizing flexible constraint length Viterbi decoders using a de Bruijn network has been approached in two different ways. The first is an embedding-theoretic approach where the problem of supporting multiple constraint lengths on a de Bruijn network is seen as a problem of embedding smaller sized de Bruijn graphs on a larger de Bruijn graph. Mathematical manipulations are presented to show that this embedding can generally be accomplished with a maximum dilation of, where N is the number of computing nodes in the physical network, while simultaneously avoiding any congestion of the physical links. In this case, however, the mapping of the decoder states onto the processing nodes is assumed fixed. Another scheme is derived based on a variable assignment of decoder states onto computing nodes, which turns out to be more efficient than the embedding-based approach. For this scheme, the maximum number of cycles per stage is found to be limited to 2 irrespective of the maximum contraint length to be supported. In addition, it is also found to be possible to execute multiple smaller decoders in parallel on the physical network, for smaller constraint lengths. Consequently, post logic-synthesis, this architecture is found to be more area-efficient than the architecture based on the embedding theoretic approach. It is also a more efficiently scalable architecture. Alternative architectures There are several interconnection topologies which are closely connected to the de Bruijn graph, and hence could form attractive alternatives for realizing flexbile constraint length Viterbi decoders. We consider two more topologies from this class -namely, the shuffle-exchange network and the flattened butterfly network. The variable state assignment scheme developed for the de Bruijn network is found to be directly applicable to the shuffle-exchange network. The average number of clock cycles per stage is found to be limited to 4 in this case. This is again independent of the constraint length to be supported. On the flattened butterfly (which is actually identical to the hypercube), a state scheduling scheme similar to that of bitonic sorting is used. This architecture is found to offer the ideal throughput of one decoded bit every clock cycle, for any constraint length. For comparison with a more general purpose topology, we consider a flexible constraint length Viterbi decoder architecture based on a 2D-mesh, which is a popular choice for general purpose applications, as well as many signal processing applications. The state scheduling scheme used here is also similar to that used for bitonic sorting on a mesh. All the alternative architectures are capable of executing multiple smaller decoders in parallel on the larger interconnection network. Inferences Following logic synthesis and power estimation, it is found that the de Bruijn network-based architecture with the variable state assignment scheme yields the lowest (area)−(time) product, while the flattened butterfly network-based architecture yields the lowest (area) - (time)2product. This means, that the de Bruijn network-based architecture is the best choice for moderate throughput applications, while the flattened butterfly network-based architecture is the best choice for high throughput applications. However, as the flattened butterfly network is less scalable in terms of size compared to the de Bruijn network, it can be concluded that among the architectures considered in this thesis, the de Bruijn network-based architecture with the variable state assignment scheme is overall an attractive choice for realizing flexible constraint length Viterbi decoders.

A pesar del explosivo crecimiento de la capacidad computacional de los ordenadores convencionales, alimentada fundamentalmente por la rápida evolución experimentada por los procesadores, existen multitud de problemas de notable importancia que aún no pueden ser abordados de forma satisfactoria. La solución más factible para abordar este tipo de problemas se basa en la utilización de computadores paralelos. Esta tesis se centra en el estudio de la red de interconexión de los computadores paralelos, aportando soluciones eficaces para mejorar su rendimiento. Se proponen mejoras de los elementos críticos de la red: los encaminadores y la propia topología. Las nuevas propuestas derivadas del trabajo son:· Un eficaz mecanismo de encaminamiento con un menor coste. Esta idea fue empleada por IBM en el supercomputador IBM BlueGene/L.· Se ha mejorado la gestión interna de los encaminadores con un coste acotado.· Se presentan arquitecturas de almacenamiento para los encaminadores con una relación coste-rendimiento favorable.· Se propone una nueva disposición de la red de interconexión que permite mejorar sus propiedades topológicas de forma notable frente a las empleadas usualmente.

The electricity high voltage transmission networks are interconnected over most of the continents but this is not the case of the power system organizations. Indeed, as described with the concept of integrated power system, the organization over these large networks is divided by several kinds of internal borders. In this context, the research object, the cross-border coordination of operation, is a set of coordination arrangements over internal borders between differing regulatory, technical and market designs. These arrangements can include for instance the famous market couplings, some cost-sharing agreements or common security assessments among several other solutions. The existence and improvement of the cross-border coordination of operation can be beneficial to the whole integrated power system. This statement is verified in the European case as in 2012 where several regional and continental coordination arrangements are successfully implemented.In order to benefit from the European experience and contribute to support the European improvement process, this thesis investigates the cross-border coordination of operation in the European case with four angles of study. First, a modular framework is built to describe the existing solutions and the implementation choices from a regulatory point of view. Second, the thesis analyses the tools available to assess the impact of an evolution of the cross-border coordination. Third, the role of the European Union (EU) is described as critical both for the existing arrangements and to support the improvement process. The last angle of study focuses on two dimensions of the economic modes of coordination between transmission system operators.

The world is currently experiencing major issues in the energy sector. The ever-growing human population, limited energy resources and the effect of greenhouse gas emissions have become major global concerns for the energy sector, including the electricity generation sector. This dilemma caused electricity providers to revise their generation methods and created a major need for consumers to utilise electricity more efficiently. Demand side management (DSM) is one initiative developed for consumers to efficiently utilise electricity. Due to their high electricity consumption and technical skills, mines are ideal targets for the implementation of DSM strategies. Therefore, the focus of this study was to investigate South African mines for possible implementation of DSM strategies on their compressed air networks. Compressed air networks at South African mines are relatively old and inadequately maintained. This causes inefficient distribution and use of compressed air. The study will therefore focus on reconfiguring mining compressed air networks for cost savings. Cost savings include financial savings on electricity bills, implementation costs and decreased maintenance. Through several investigations, the possibility of implementing energy savings strategies to reconfigure the compressed air networks of two South African mines was identified. Reconfiguring the networks would respectively entail interconnecting two shafts and relocating a compressor from an abandoned shaft to a fully productive shaft. Theoretical simulations were developed to determine the networks’ responses to the reconfiguration strategies. The simulations assisted in exposing the viability of implementing the reconfiguration strategies on the respective compressed air networks. Positive responses were obtained from the simulations and proposals were made to the respective mines for possible implementation. The proposed initiatives were implemented on the respective mines’ compressed air networks. After implementation of the interconnection strategy, a consecutive three-month performance assessment period commenced to prove the viability of the proposed savings. An average power saving of 1 700 kW was achieved during the performance assessment period. The proposed initiative to relocate the compressor is currently being implemented. A financial saving of approximately R8.9 million per annum was achieved by implementing the interconnection strategy. The large financial saving was due to the utilisation of the mine’s salvaged equipment. Further savings were achieved by the decreased maintenance on the mine’s compressors. Due to the successful implementation of the interconnection strategy, it is safe to state that cost savings can be achieved by reconfiguring mining compressed air networks. / MIng (Mechanical Engineering), North-West University, Potchefstroom Campus, 2014

In recent years, the number of available cores in a processor are increasing rapidly while the pace of performance improvement of an individual core has been lagged. It led application developers to extract more parallelism from a number of cores to make their applications run faster. However, writing a parallel program that scales well with the increasing core counts is challenging. Consequently, many parallel applications suffer from performance bugs caused by scalability limiters. We expect core counts to continue to increase for the foreseeable future and hence, addressing scalability limiters is important for better performance on future hardware. With this thesis, I propose both software frameworks and hardware improvements that I developed to address three important scalability limiters: load imbalance, barrier latency and increasing on-chip packet latency. First, I introduce a debugging framework for load imbalance called LIME. The LIME framework uses profiling, statistical analysis and control flow graph analysis to automatically determine the nature of load imbalance problems and pinpoint the code where the problems are introduced. Second, I address scalability problem of the barrier, which has become costly and difficult to achieve scalable performance. To address this problem, I propose a transmission line (TL) based hardware barrier support, called TLSync, that is orders of magnitude faster than software barrier implementation while supports many (tens) of barriers simultaneously using a single chip-spanning network. Third and lastly, I focus on the increasing packet latency in on-chip network, and propose a hybrid interconnection where a low-latency TL based interconnect is synergistically used with a high-throughput switched interconnect. Also, a new adaptive packet steering policy is created to judiciously use the limited throughput available on the low-latency TL interconnect.

As the convergence of multiple functions in a single electronic device drives current electronic trends, the need for increasing integration density is becoming more emphasized than in the past. To keep up with the industrial need and realize the new system integration law, three-dimensional (3-D) integration called System-on-Package (SoP) is becoming necessary. However, the commercialization of 3-D integration should overcome several technical barriers, one of which is the difficulty for the electrical design of interconnections. The 3-D interconnection design is difficult because of the modeling challenge of electrical coupling from the complicated structures of a large number of interconnections. In addition, mixed-signal design requires broadband modeling, which covers a large frequency spectrum for integrated microsystems. By using currently available methods, the electrical modeling of 3-D interconnections can be a very challenging task. This dissertation proposes a new method for constructing a broadband model of a large number of 3-D interconnections. The basic idea to address the many interconnections is using modal basis functions that capture electrical effects in interconnections. Since the use of global modal basis functions alleviates the need for discretization process of the interconnection structure, the computational cost is reduced considerably. The resultant interconnection model is a RLGC model that describes the broadband electrical behavior including losses and couplings. The smaller number of basis functions makes the interconnection model simpler, and therefore allows the generation of network parameters at reduced computational cost. Focusing on the modeling of bonding wires in stacked ICs and through-silicon via (TSV) interconnections, this research validates the interconnection modeling approach using several examples from 3-D full-wave EM simulation results.

Multi-Processor System-on-Chip (MPSoC) possui vários processadores, em um único chip. Várias aplicações podem ser executadas de maneira paralela ou uma aplicação paralelizável pode ser particionada e alocada em cada processador, a fim de acelerar a sua execução. Um problema em MPSoCs é a comunicação entre os processadores, necessária para a execução destas aplicações. Neste trabalho, propomos uma arquitetura de rede de interconexão baseada na topologia crossbar, com memória compartilhada. Esta arquitetura é parametrizável, possuindo N processadores e N módulos de memórias. A troca de informação entre os processadores é feita via memória compartilhada. Neste tipo de implementação cada processador executa a sua aplicação em seu próprio módulo de memória. Através da rede, todos os processadores têm completo acesso a seus módulos de memória simultaneamente, permitindo que cada aplicação seja executada concorrentemente. Além disso, um processador pode acessar outros módulos de memória, sempre que necessite obter dados gerados por outro processador. A arquitetura proposta é modelada em VHDL e seu desempenho é analisado através da execução paralela de uma aplicação, em comparação à sua respectiva execução sequencial. A aplicação escolhida consiste na otimização de funções objetivo através do método de Otimização por Enxame de Partículas (Particle Swarm Optimization - PSO). Neste método, um enxame de partículas é distribuído igualmente entre os processadores da rede e, ao final de cada interação, um processador acessa o módulo de memória de outro processador, a fim de obter a melhor posição encontrada pelo enxame alocado neste. A comunicação entre processadores é baseada em três estratégias: anel, vizinhança e broadcast. Essa aplicação foi escolhida por ser computacionalmente intensiva e, dessa forma, uma forte candidata a paralelização. / Multi-Processor System-on-Chip (MPSoC) has multiple processors in a single chip. Multiple applications can be executed in parallel or a parallelizable application can be partitioned and allocated to each processor in order to accelerate their execution. One problem in MPSoCs is the communication between the processors required to implement these applications. In this work, we propose the architecture of an interconnection network based on the crossbar topology, with shared memory. This architecture is parameterizable, having N processors and N memory modules. The exchange of information between processors is done via shared memory. In this type of implementation each processor executes its application stored in its own memory module. Through the network, all processors have complete access to their own memory modules simultaneously allowing each application to run concurrently. Moreover, a processor can access other memory modules, whenever it needs to retrieve data generated by another processor. The proposed architecture is modelled in VHDL and its performance is analysed by the execution of a parallel aplication, in comparison to its sequencial one. The chosen application consists of optimizing some objetive functions by using the Particle Swarm Optimization method. In this method, particles of a swarm are distributed among the processors and, at the end of each iteration, a processor accesses the memory module of another one in order to obtain the best position found in the swarm. The communication between processors is based on three strategies: ring, neighbourhood and broadcast. This application was chosen due to its computational intensive characteristic and, therefore, a strong candidate for parallelization.

Made available in DSpace on 2014-12-17T15:48:09Z (GMT). No. of bitstreams: 0 Previous issue date: 2007-02-02 / Multimedia systems must incorporate middleware concepts in order to abstract hardware and operational systems issues. Applications in those systems may be executed in different kinds of platforms, and their components need to communicate with each other. In this context, it is needed the definition of specific communication mechanisms for the transmission of information flow. This work presents a interconnection component model for distributed multimedia environments, and its implementation details. The model offers specific communication mechanisms for transmission of information flow between software components considering the Cosmos framework requirements in order to support component dynamic reconfiguration / Sistemas multim?dia devem incorporar conceitos de middleware de forma a abstrair especificidades de hardware e sistemas operacionais. Aplica??es nestes sistemas podem ser executadas em diferentes tipos de plataformas, e os componentes destes sistemas precisam interagir uns com os outros. Neste contexto, faz-se necess?rio a defini??o de mecanismos de comunica??o espec?ficos para a transmiss?o de fluxos de informa??o. Este trabalho apresenta um modelo para a interconex?o de componentes em ambientes multim?dia, e sua arquitetura de implementa??o. O modelo oferece mecanismos de comunica??o espec?ficos para a transmiss?o de fluxos de informa??o entre componentes de software atendendo aos requisitos do framework Cosmos de maneira a suportar a reconfigura??o din?mica de componentes

Made available in DSpace on 2014-12-17T15:48:13Z (GMT). No. of bitstreams: 1 CarlosES.pdf: 1065336 bytes, checksum: c1840ccdd384fc7c59635d8e173e484f (MD5) Previous issue date: 2007-02-05 / Multimedia systems must incorporate middleware concepts in order to abstract hardware and operational systems issues. Applications in those systems may be executed in different kinds of platforms, and their components need to communicate with each other. In this context, it is needed the definition of specific communication mechanisms for the transmission of information flow. This work presents a interconnection component model for distributed multimedia environments, and its implementation details. The model offers specific communication mechanisms for transmission of information flow between software components considering the Cosmos framework requirements in order to support component dynamic reconfiguration / Sistemas multim?dia devem incorporar conceitos de middleware de forma a abstrair especificidades de hardware e sistemas operacionais. Aplica??es nestes sistemas podem ser executadas em diferentes tipos de plataformas, e os componentes destes sistemas precisam interagir uns com os outros. Neste contexto, faz-se necess?rio a defini??o de mecanismos de comunica??o espec?ficos para a transmiss?o de fluxos de informa??o. Este trabalho apresenta um modelo para a interconex?o de componentes em ambientes multim?dia, e sua arquitetura de implementa??o. O modelo oferece mecanismos de comunica??o espec?ficos para a transmiss?o de fluxos de informa??o entre componentes de software atendendo aos requisitos do framework Cosmos de maneira a suportar a reconfigura??o din?mica de componentes