Cargas e fontes elétricas de pequeno porte, integradas através de alimentadores de distribuição de baixa tensão, agrupadas e gerenciadas de tal maneira que se comportem como uma única entidade controlável dentro de um sistema de potência e com a capacidade de operar de forma paralela ou isolada da rede elétrica convencional, constituem-se em um novo tipo de sistema elétrico conhecido como Minirrede. Esta tese aborda o problema relacionado à estabilidade dinâmica de Minirredes com controle autônomo de frequência e tensão, quando operadas de forma isolada da rede convencional. As minirredes analisadas são compostas por combinações de fontes elétricas convencionais e fontes alternativas que não geram naturalmente em 50 ou 60 Hz, sendo necessária a utilização de inversores para sua conexão com a rede elétrica. A análise se realiza no espaço de estados com metodologias baseadas nas teorias que envolvem os autovalores e autovetores da matriz de estado. Para isto, modelos no espaço de estados são desenvolvidos para cada componente da Minirrede, mantendo um compromisso entre precisão e complexidade. O caráter analítico da análise permite investigar a relação entre a estabilidade da Minirrede e os parâmetros do sistema, tais como ganhos dos controladores, dimensionamento da rede, configurações de geração, entre outros. Análises complementares de sensibilidade dos autovalores aos parâmetros elétricos do sistema permitem inferir o comportamento dinâmico de diversas configurações de Minirredes, obtendo-se importantes conclusões à respeito. Os resultados analíticos são verificados através de simulação computacional no ambiente Simulink/Matlab®. / Electrical loads and small power sources, integrated through low voltage distribution feeders, managed in such a way to behave as one controllable entity within in a power system, and with the ability to operate connected or non-connected to the conventional power system is a new kind of electrical system known as Microgrid. This thesis addresses the problem related to dynamic stability of island Microgrids with autonomous control of frequency and voltage. The Microgrids analyzed are composed of combinations of conventional and alternative power sources that do not generate electricity naturally in 50 or 60 Hz, therefore inverters are needed to provide AC network interface. The analysis is performed in the state space with methodologies based on theories involving the eigenvalues and eigenvectors of the state matrix. For this, state-space models are developed for each component of Microgrid, maintaining a compromise between accuracy and complexity. The analytical nature of this study allows investigating the relationship between the stability of Microgrid and parameters of the system, such as controller gains, network design, generation architectures, among others. Complementary sensitivity analyzes of eigenvalues to the electrical parameters of the system allow us to infer the dynamic behavior of various configurations of Microgrids, obtaining important conclusions on the matter. The analytical results are verified by computer simulation using the platform Simulink/Matlab®.

In this thesis, several design methodologies are presented to improve the reliability of dual traction inverters in hybrid electric vehicles (HEVs). Several power inverter topologies including the two-level voltage-source inverter, the boost voltage-source inverter, the Z-source inverter, and reduced-parts inverters are compared in terms of power ratings, volume, and efficiency. The comparison results show that the two-level voltage-source inverter presents higher efficiency, higher power density, and lower cost. Therefore, the back-to-back two-level voltage-source inverter is selected. DC-link capacitor and power modules are the most vulnerable components in dual traction inverters. The lifetime of capacitor is mainly determined by the core temperature. In this thesis, an interleaving control scheme is proposed to reduce the capacitor power loss by decreasing the total DC-link current harmonics. With reduced capacitor power loss, the core temperature of capacitor is reduced. Therefore, the lifetime of capacitor is improved. In addition, a fast electro-thermal model of traction inverters is proposed to estimate the junction temperatures of power devices. Practical switching losses are measured and thermal coupling effects between multiple devices are considered. The calculation rate of junction temperature is reduced by considering both power loss profiles and properties of the thermal impedance. With this model, over-temperature protection and lifetime evaluation can be implemented to enhance the reliability of traction inverters. Finally, a current sensor fault-tolerant operation scheme with six-phase current reconstruction technique is proposed to improve the reliability of dual inverters. In order to get the missing phase currents, the PWM signals are phase shifted to create the reconstruction conditions. With measured DC-link current, all phase-currents of dual inverters are obtained at the expense of slight degradation of maximum allowable modulation index. Therefore, when some or all of the phase current sensors are failed, the dual traction inverters can operate normally. / Thesis / Doctor of Philosophy (PhD)

Traction inverter, as a critical component in electrified transportation, has been the subject of many research studies in terms of topologies, modulation, and control schemes. Recently, some of the well-known electric vehicle manufacturers have utilized higher-voltage batteries to benefit from lower current, higher power density, and faster charging times. With the ongoing trend toward higher voltage DC-link in electric vehicles, some multilevel structures have been investigated as a feasible and efficient option for replacing the two-level inverters. Higher efficiency, higher power density, better waveform quality, and inherent fault-tolerance are the foremost advantages of multilevel inverters which make them an attractive solution for this application. The first contribution of this thesis is to investigate and present a comprehensive review of the multilevel structures in traction applications. Secondly, this thesis proposes an electro-thermal model based on foster equivalent thermal networks for a designed three-level active neutral point clamped (ANPC) inverter, as well as a modified sinusoidal pulse-width modulation (SPWM) -based technique. This electro-thermal model and the modulation technique enable temperature estimation in the inverter and minimization of the hotspot temperature and hence, increase the power density. Based on the experimental results derived from the implemented setup, a 12% increase in power density is achieved with the proposed technique. The other contribution is a reduced-complexity model-predictive controller (MPC) for the three-level ANPC inverter without weighting factors in which the number of calculations has dropped from 27 to 12 in each sampling period. The improvements to the structure and control system of the inverter are supported by theoretical analysis, simulation results, and experimental tests. A three-level inverter is implemented for 800 V, 70 kW operation and tested. 750 V Silicon Carbide (SiC) switches are utilized in the inverter structure. Finally, future trends and suggestions for the following studies are stated in this thesis. / Thesis / Doctor of Philosophy (PhD)

No description available.

This thesis focuses on the concept, design, and simulation of the Reconfigurable Multi-Source Inverter for EV applications and its effectiveness when combined with a HESS. The current trends in the automotive market, including different vehicle types, and the adoption of electrified vehicles by the public are discussed. The benefits and logistics of different vehicle architectures are analyzed and compared. Hybrid vehicles will be essential in helping transition society from conventional internal combustion engine vehicles to purely electric vehicles. The individual components of these electrified vehicles are reviewed, and common topologies are discussed with the benefits of each system compared. The batteries required for these electric vehicles are costly and require many individual cells in order to operate efficiently. Many hybrids vehicles make use of expensive power electronics, such as DC/DC converters to help boost the operating voltage of the battery pack without adding additional cells. A Reconfigurable Multi-Source Inverter in introduced and its switching structure is explained in depth. Its’ ability to make use of multiple DC sources to create four different voltage levels is outlined and possible modulation techniques are presented. This thesis aims to introduce a novel Reconfigurable Multi-Source Inverter using a Space Vector Pulse Width Modulation (SVPWM) scheme and is further investigated through simulations and with plans for experimental validation on an R-L load. / Thesis / Master of Applied Science (MASc) / One of the main factors affecting the cost of electrified vehicles is the expense of building a high voltage battery pack. Motor’s used in electric vehicle applications typically operate at higher voltages and therefore require large battery pack or costly power electronics to step the voltage of the pack up to a suitable operating level. A Reconfigurable Multi-Source Inverter uses a combination of two sources to create different voltage levels. This novel inverter can be used to maximize the voltage of smaller packs to help reduce the overall cost of vehicle electrification.

Multi-level inverters play a significant role in high power drive systems for induction motors. Interest in multi-level inverters started with the three-level, neutral point clamped (NPC) inverter. Now there are many topologies for higher number of levels such as the, flying capacitor and cascaded H-bridge etc. The advantage of multi-level inverters is the reduced voltage stress on the switching devices, lower dv/dt and lower harmonic content. The voltage space vector structure in a multi-level inverter has a hexagonal periphery similar to that in a two-level inverter. In the over-modulation region in multi-level inverters, there is the presence of lower order harmonics such as 5th and 7th in the output voltage, and this can be avoided by using a voltage space vector scheme with more than six polygonal voltage space vectors such as 12, 18, 24 etc. These polygonal voltage space vectors can be generated by using multi-level inverter topologies, by cascading two-level inverter structures with asymmetric DC-links. This thesis deals with the development of 12-sided and 18-sided polygonal voltage space vector schemes for induction motor drives. With the 12-sided polygonal structure, all the 5th and 7th harmonic orders and 6n±1, n=1, 3, 5.. are absent throughout the modulation range, and in the 18-sided voltage space vector scheme, 5th, 7th, 11th and 13th harmonics are absent throughout the modulation range. With the absence of the low order frequencies in the proposed polygonal space vector structures, high frequency PWM schemes are not needed for voltage control. This is an advantage over conventional schemes. Also, due to the absence of lower order harmonics throughout the modulation range, special compensated synchronous reference frame PI controllers are not needed in current controlled vector control schemes in over-modulation. In this thesis a method is proposed for generating 12-sided polygonal voltage space vectors for an induction motor fed from one side. A cascaded combination of three two-level inverters is used with asymmetrical DC-links. A simple space vector PWM scheme based only on the sampled reference phase amplitudes are used for the inverter output voltage control. The reference space vector is sampled at different sampling rates depending on the frequency of operation. The number of samples in a sector is chosen to keep the overall switching frequency around 1kHz, in order to minimize switching losses. The voltage space vectors that make up the two sides of the sector in which the reference vector lies, are time averaged using volt-sec balance, to result in the reference vector. In the proposed 12-sided PWM scheme all the harmonics of the order 6n±1, n=1, 3, 5... are eliminated from the phase voltage, throughout the modulation range. In multi-level inverters steps are taken to eliminate common-mode voltage. Common-mode voltage is defined as one third of the sum of the three pole voltages of the inverter for a three phase system. Bearings are found to fail prematurely in drives with fast rising voltage pulses and high frequency switching. The alternating common-mode voltage generated by the PWM inverter contributes to capacitive couplings from stator body to rotor body. This generates motor shaft voltages causing bearing currents to flow from rotor to stator body and then to the ground. There can be a flashover between the bearing races. Also a phenomenon termed EDM (Electro-discharge machining) effect occurs and may damage the bearings. Common-mode voltage has to be eliminated in order to overcome these effects. In multi-level inverters redundancy of space vector locations is used to eliminate common-mode voltages. In the present thesis a 12-sided polygonal voltage space vector based inverter with an open-end winding induction motor is proposed, in which the common-mode voltage variation at the poles of the inverter is eliminated. In this scheme, there is a three-level inverter on each side of the open-end winding of the induction motor. The three-level inverter is made by cascading two, two-level inverters with unequal DC-link voltages. Appropriate space vectors are selected from opposite sides such that the sum of the pole voltages on each side is a constant. Also during the PWM operation when the zero vector is applied, identical voltage levels are used on both sides of the open-end windings, in order to make the phase voltages zero, while the common-mode voltage is kept constant. This way, common-mode voltage variations are eliminated throughout the modulation range by appropriately selecting the voltage vectors from opposite ends. In this method all the harmonics of 6n±1, n=1, 3, 5.. and triplen orders are eliminated. In the 12-sided polygonal voltage space vector methods, the 11th and 13th harmonics though attenuated are not eliminated. In the 18-sided polygonal voltage space vector method the 11th and 13th harmonics are eliminated along with the 5th and 7th harmonics. This scheme consists of an open-end winding induction motor fed from one side by a two-level inverter and the other side by a three-level inverter comprising of two cascaded two-level inverters. Asymmetric DC-links of a particular ratio are present. The 12-sided and 18-sided polygonal voltage space vector methods have been first simulated using SIMULINK and then verified experimentally on a 1.5kW induction motor drive. In the simulation as well as the experimental setup the starting point is the generation of the three reference voltages v, vB and vC . A method for determining the sector in which the reference vector lies by comparing the values of the scaled sampled instantaneous reference voltages is proposed. For the reference vector lying in a sector between the two active vectors, the first vector is to be kept on for T1 duration and the second vector for T2 duration. These timing durations can be found from the derived formula, using the sampled instantaneous values of the reference voltages and the sector information. From the pulse widths and the sector number, the voltage level at which a phase in the inverter has to be maintained is uniquely determined from look-up tables. Thus, once the pole voltages are determined the phase voltages can be easily determined for simulation studies. By using a suitable induction motor model in the simulation, the effect of the PWM scheme on the motor current can be easily obtained. The simulation studies are experimentally verified on a 1.5kW open-end winding induction motor drive. A V/f control scheme is used for the study of the drive scheme for different speeds of operation. A DSP (TMS320LF2407A) is used for generating the PWM signals for variable speed operation. The 12-sided polygonal voltage space vector scheme with the motor fed from a single side has a simple power bus structure and it is also observed that the pole voltage is clamped to zero for 30% of the time duration of one cycle of operation. This will increase the overall efficiency. The proposed scheme eliminates all harmonics of the order 6n±1, n=1, 3, 5…for the complete modulation range. The 12-sided polygonal voltage space vector scheme with common-mode elimination requires the open-end winding configuration of the induction motor. Two asymmetrical DC-links are required which are common to both sides. The leg of the high voltage inverter is seen to be switched only for 50% duration in a cycle of operation. This will also reduce switching losses considerably. The proposed scheme not only eliminates all harmonics of the order 6n±1, n=1, 3, 5…for the complete modulation range, but also maintains the common-mode voltage on both sides constant. The common-mode voltage variation is eliminated. This eliminates bearing currents and shaft voltages which can damage the motor bearings. In the 18-sided polygonal voltage space vector based inverter, the 11th and 13th harmonics are eliminated along with the 5th and 7th. Here also an open-end winding induction motor is used, with a two-level inverter on one side and a three-level inverter on the other side. A pole of the two-level inverter is at clamped to zero voltage for 50% of the time and a pole of the three-level inverter is clamped to zero for 30% of the time for one cycle of operation. The 18-sided polygonal voltage space vectors show the highest maximum peak fundamental voltage in the 18-step mode of 0.663Vdc compared to 0.658Vdc in the 12-step mode of the 12-sided polygonal voltage space vector scheme and 0.637Vdc in the six-step mode of a two-level inverter or conventional multi-level inverter (where Vdc is the radius of the space vector polygon). Though the schemes proposed are verified on a low power laboratory prototype, the principle and the control algorithm development are general in nature and can be easily extended to induction motor drives for high power applications.

Τα τελευταία 35 χρόνια έχει προκύψει ένα ενεργειακό πρόβλημα το οποίο μας επιβάλει να αλλάξουμε την ενεργειακή μας αντίληψη. Το πετρέλαιο αλλά και άλλα ορυκτά καύσιμα έχουν πεπερασμένα αποθέματα και η χρήση τους επιβαρύνει το περιβάλλον. Επίσης γεωπολιτικά συμφέροντα δεν επιτρέπουν την ανεμπόδιστη διανομή του. Μέσα σε αυτό το κλίμα της ενεργειακής απεξάρτησης από τα ορυκτά καύσιμα αναπτύσσονται τα τελευταία χρόνια τα υβριδικά οχήματα. Τα ηλεκτρικά υβριδικά οχήματα είναι ένα μεταβατικό στάδιο από την πετρελαιοκίνηση στην εξ’ ολοκλήρου κίνηση μέσω ηλεκτρισμού από ενεργειακές κυψέλες. Αποτελούνται από έναν συμβατικό κινητήρα εσωτερικής καύσης και μια ηλεκτρική μηχανή, η οποία τροφοδοτείται από συσσωρευτές. Τα υβριδικά οχήματα χωρίζονται σε διάφορες κατηγορίες ανάλογα με τις τεχνολογίες υβριδοποίησης που διαθέτουν και την διάταξη του ηλεκτρομηχανολογικού τους συστήματος. Στόχος της παρούσας διπλωματικής εργασίας (η οποία είναι η συνέχεια δυο προηγούμενων) είναι η προσπάθεια κατασκευής ενός υβριδικού αυτοκινήτου. Για να γίνει αυτό εφικτό απαιτούνται, ένα όχημα το οποίο να μπορεί να δεχθεί εύκολα μηχανολογικές μετατροπές, ένας ηλεκτρικός κινητήρας και συσσωρευτές. Ο ηλεκτρικός κινητήρας ελέγχεται από έναν αντιστροφέα. Ο αντιστροφέας είναι μια ηλεκτρική συσκευή η οποία μετατρέπει το συνεχές ρεύμα των συσσωρευτών σε εναλλασσόμενο. Βασικό κομμάτι του αντιστροφέα είναι η λογική παλμοδότησής του. Ο αντιστροφέας που κατασκευάστηκε χρησιμοποιεί τον άμεσο έλεγχο ροπής, ο οποίος είναι ένα είδος άμεσου διανυσματικού ελέγχου που χρησιμοποιεί τον μετασχηματισμό Park. / Τα τελευταία 35 χρόνια έχει προκύψει ένα ενεργειακό πρόβλημα το οποίο μας επιβάλει να αλλάξουμε την ενεργειακή μας αντίληψη. Το πετρέλαιο αλλά και άλλα ορυκτά καύσιμα έχουν πεπερασμένα αποθέματα και η χρήση τους επιβαρύνει το περιβάλλον. Επίσης γεωπολιτικά συμφέροντα δεν επιτρέπουν την ανεμπόδιστη διανομή του. Μέσα σε αυτό το κλίμα της ενεργειακής απεξάρτησης από τα ορυκτά καύσιμα αναπτύσσονται τα τελευταία χρόνια τα υβριδικά οχήματα. Τα ηλεκτρικά υβριδικά οχήματα είναι ένα μεταβατικό στάδιο από την πετρελαιοκίνηση στην εξ’ ολοκλήρου κίνηση μέσω ηλεκτρισμού από ενεργειακές κυψέλες. Αποτελούνται από έναν συμβατικό κινητήρα εσωτερικής καύσης και μια ηλεκτρική μηχανή, η οποία τροφοδοτείται από συσσωρευτές. Τα υβριδικά οχήματα χωρίζονται σε διάφορες κατηγορίες ανάλογα με τις τεχνολογίες υβριδοποίησης που διαθέτουν και την διάταξη του ηλεκτρομηχανολογικού τους συστήματος. Στόχος της παρούσας διπλωματικής εργασίας (η οποία είναι η συνέχεια δυο προηγούμενων) είναι η προσπάθεια κατασκευής ενός υβριδικού αυτοκινήτου. Για να γίνει αυτό εφικτό απαιτούνται, ένα όχημα το οποίο να μπορεί να δεχθεί εύκολα μηχανολογικές μετατροπές, ένας ηλεκτρικός κινητήρας και συσσωρευτές. Ο ηλεκτρικός κινητήρας ελέγχεται από έναν αντιστροφέα. Ο αντιστροφέας είναι μια ηλεκτρική συσκευή η οποία μετατρέπει το συνεχές ρεύμα των συσσωρευτών σε εναλλασσόμενο. Βασικό κομμάτι του αντιστροφέα είναι η λογική παλμοδότησής του. Ο αντιστροφέας που κατασκευάστηκε χρησιμοποιεί τον άμεσο έλεγχο ροπής, ο οποίος είναι ένα είδος άμεσου διανυσματικού ελέγχου που χρησιμοποιεί τον μετασχηματισμό Park.

In high-power electric drives, multilevel inverters are generally deployed to address issues such as electromagnetic interference, switch voltage stress and harmonic distortion. The switching frequency of the inverter is always kept low, of the order of 1KHz or even less to reduce switching losses and synchronous pulse width modulation (PWM) is used to avoid the problem of sub-harmonics and beat frequencies. This is particularly important if the switching frequency is very low. The synchronous PWM is getting popularity as its realization is very easy with digital controllers compared to analog controllers. Neutral-point-clamped (NPC) inverters, cascaded H-bridge, and flying-capacitor multilevel inverters are some of the popular schemes used for high-power applications. Hybrids of these multilevel inverters have also been proposed recently to take advantage of the basic configurations. Multilevel inverters can also be realized by feeding the induction motor from both ends (open-end winding) using conventional inverter structures. For controlling the output voltage of these inverters, various PWM techniques are used. Chapter-1 of this thesis provides an over view of the various multilevel inverter schemes preceded by a discussion on basic two-level VSI topology. The inverters used in motor drive applications have to be operated in over-modulation range in order to extract the maximum fundamental output voltage that is possible from the dc-link. Operation in this high modulation range is required to meet temporary overloads or to have maximum power operation in the high speed range (flux weakened region). This, however, introduces a substantial amount of low order harmonics in the Motor phase voltages. Due to these low-order harmonic frequencies, the dynamic performance of the drive is lost and the current control schemes are severely affected especially due to 5th and 7th harmonic components. Further, due to these low-order harmonics and non-linear PWM operation in over-modulation region, frequent over-current fault conditions occur and reliability of the drive is jeopardized. The twelve sided-polygonal space vector diagram (dodecagonal space vectors) can be used to overcome the problem of low order 5th and 7th harmonics and to give more range for linear modulation while keeping the switching frequency at a minimum compared to conventional hexagonal space vector based inverters. Thus, the dodecagonal space-vector switching can be viewed as an engineering compromise between low switching frequency and quality load current waveform. Most of the previous works of dodecagonal space-vector generation schemes are based on NPC inverters. However, sophisticated charge control schemes are required in NPC inverters to deal with the neutral-point voltage fluctuation and the neutral-point voltage shifting issues. The losses in the clamping diodes are another major concern. In the second chapter, a multilevel dodecagonal space-vector generation scheme based on flying capacitor topology, utilizing an open end winding induction motor is presented. The neutral point charge-balancing problem reported in the previous works is not present in this scheme, the clamping diodes are eliminated and the number of power supplies required has been reduced. The capacitors have inherent charge balancing capability, and the charge control is done once in every switching cycle, which gives tight voltage control for the capacitors. For the speed control of induction motors, the space-vector PWM scheme is more advantageous than the sine-triangle PWM as it gives a more linear range of operation and improved harmonic performance. One major disadvantage with the conventional space-vector PWM is that the trigonometric operations demand formidable computational efforts and look-up tables. Carrier based, common-mode injected PWM schemes have been proposed to simplify the PWM process. However, the freedom of selecting the PWM switching sequences is limited here. Another way of obtaining SVPWM is using the reference voltage samples and the nearest vector information to switch appropriate devices for proper time intervals, realizing the reference vector in an average sense. In-formation regarding the sector and nearest vectors can be easily obtained by comparing the instantaneous amplitudes of the reference voltages. This PWM approach is pro-posed for the speed control of the motor in this thesis. The trigonometric operations and the requirement of large look-up tables in the conventional SVPWM are avoided in this method. It has the additional advantage that the switching sequences can be decided at will, which is helpful in reducing further, the harmonic distortion in certain frequency ranges. In this way, this method tries to combine the advantages of vector based methods (conventional SVPWM) and scalar methods (carrier-based methods). The open-end winding schemes allowed the required phase voltage levels to be generated quite easily by feeding from both ends of the windings. Thus, most of the multilevel inverters based on dodecagonal space-vector structures relied on induction motors with open-end windings. The main disadvantage of open-end winding induction motor is that six wires are to be run from the inverter to the motor, which may be unacceptable in certain applications. Apart from the inconvenience of laying six wires, the voltage reflections in the wires can lead to over voltages at the motor terminals, causing insulation failures. Where as the topology presented in chapter-2 of this thesis uses open-end winding motor with flying-capacitor inverters for the generation of dodecagonal space-vectors, the topology presented in chapter-3 utilizes a cascade connection of flying-capacitors and floating H-bridge cells to generate the same set of voltage space-vectors, thus allowing any standard induction motor as the load. Of the methods used for the speed control of induction motors, namely sine-triangle PWM and space vector PWM, the latter that provides extra modulation range is naturally preferred. It is a well-understood fact that the way in which the PWM switching sequences are applied has a significant influence on the harmonic performance of the drive. However, this topic has not been addressed properly for dodecagonal voltage space-vector based multilevel inverter drives. In chapter-4 of the thesis, this aspect is taken into ac-count and the notion of “harmonic flux trajectories” and “stator flux ripple” are used to analyze the harmonic performance of the various PWM switching schemes. Although the PWM method used in this study is similar to that in chapter-2, the modification in the PWM switching sequence in the PWM algorithm yields significant improvements in harmonic performance. The proposed topologies and PWM schemes are extensively simulated and experimentally verified. The control scheme was implemented using a DSP processor running at a clock frequency 150MHz and a four-pole, 3.7kW, 50Hz, 415V three-phase induction motor was used as the load. Since the PWM ports are limited in a DSP, a field-programmable gate array (FPGA) was used to decode the PWM signals from the DSP to generate timing information required for PWM sequencing for all the power devices. The same FPGA was used to generate the dead-time signals for the power devices also.

Use of multilevel inverters are inevitable in medium and high voltage drives. This is due to the fact that the multilevel inverters can produce voltages in smaller steps which will reduce the harmonic content and result in more sinusoidal voltages and currents as compared to voltages and currents from two-level inverters. Due to the device limitations, use of two-level inverters is not possible in medium and high voltage drive applications. Though multiple devices can be connected both in series and parallel to achieve two-level operation, the output voltages still suffer from high harmonic content. Multilevel inverters have multiple DC voltage levels with switches that enable one of the voltage steps to be applied to the load. Due to decrease in step size during each switching instant, output voltages and currents of the multilevel inverters have considerably less harmonic content. As the number of levels increase, the switching step reduces thereby the harmonic content also reduces drastically. Due to their advantages, multilevel inverters have gained lot of acceptance in the industry even at lower voltages. The three main configurations that have gained popularity are the neutral point clamped converter, the flying capacitor converter and the cascaded H-bridge converter. Each converter has its own set of advantages and disadvantages. Based on the requirements of various applications, it is possible to fabricate hybrid multilevel topologies that are combinations of the three basic topologies. Researchers around the world have proposed several such converters for diverse applications so as to suit particular requirements like modularity, ease of control, improved reliability, fault tolerant capability etc. The present thesis explores multilevel converters with single DC link to be used for motor drive and grid connected applications. A novel five-level inverter topology formed by cascading a floating capacitor H-bridge module to a regular three-level flying capacitor inverter has been explored in chapter 2. The three-level flying capacitor inverter can generate pole voltages of 0, VDC /2 and VDC . By cascading it with another floating capacitor H-bridge of voltage magnitude VDC /4, pole voltages of 0, VDC /4, VDC/2, 3VDC /4 and VDC . Each of these pole voltage levels can have one or more switching combinations. However each switching combination has a unique effect on the state of the two capacitor voltages. By switching through redundant switching combinations for the same pole voltage, the two capacitors present in each phase can be balanced. The proposed topology also has an advantage that if one of the devices in the H-bridge fails, the topology can still be operated as a regular three-level flying capacitor inverter that can supply full load at rated power by bypassing the faulty H-bridge. This fault tolerant operation of the converter will enable it to be used in applications like traction and marine drives where high reliability is needed. The proposed converter needs a single DC link. All the required voltage levels can be generated from the single DC link. This enables back to back grid connected operation possible where multiple converters can interact with a single DC link. Various pole voltage switching combination and its effect on individual capacitor has been studied. A control algorithm to balance the capacitor voltages by switching through multiple redundancies for the same pole voltage has been developed. The proposed configuration has been implemented in hardware using IGBT H-bridge modules and the control circuitry is realized using DSP and FPGA. The performance of the drive is verified for various frequencies and modulation indices during steady state by running a three phase induction motor at no load. The stability of the drive during transients has been studied by accelerating the machine suddenly at no load and analyzing the performance of the drive. The capacitor voltages are made to deviate from their intended values and the capacitor balancing algorithm has been verified for its ability to bring the capacitor voltages back to their intended values. The experimental results have been presented and discussed in detail in the chapter 2. In the third chapter a common-mode voltage eliminated three-level inverter using a single DC link has been proposed. The power schematic is similar to the one presented in chapter 2. In this chapter the space vector polygon formed by the three phases of the proposed topology has been presented. The common-mode voltage generated by different pole voltage combinations for same space vector location and the redundant switching state combinations has been studied. The pole voltage combinations with zero common mode voltage have been studied. The switching state redundancies for the the pole voltage have been studied. The space vector polygon formed with the pole voltage combinations has been analyzed. A drive is made with the proposed common-mode voltage eliminated inverter. The performance of the drive is tested for various modulation indices and frequencies by running a three phase squirrel cage induction motor at no load. The transient performance is verified by accelerating the motor suddenly and checking the common-mode voltage along with the capacitor voltages. The results have been presented and discussed in detail in chapter 3. This converter has advantages like use of single DC supply, ability to operate as a regular three level converter in case of failure of one of the H-bridges. The work presented in fourth chapter proposes a novel three phase 17-level inverter configuration which utilizes a single DC supply. The rest of voltages are generated using three floating capacitor H-bridges. The redundant switching combinations for generating various pole voltages and their effect on the capacitors have been studied and suitable capacitor balancing algorithm has been developed. The proposed topology has been realized in hardware and the performance of the drive during steady state has been studied by running an induction motor at various modulation indices and frequencies. The transient response of the drive has been observed by accelerating the motor suddenly under no load. The results have been presented in detail in chapter four. This configuration also needs a single DC link. The advantages of this configuration is in case of failure of any devices in the H-bridge, the drive can be operated at reduced number of levels while supplying full load current. This feature helps the drive to be used in fault tolerant applications like marine and traction drives where reliability of the drive is of prime importance. All the topologies that have been presented in the previous chapters have mentioned about the usage of the proposed genre of topologies use single DC link and hence will enable back to back grid tied inverter connection. In the fifth chapter this has has been verified experimentally. The three phase squirrel cage induction motor is driven by using the seventeen-level inverter drive proposed in chapter four. A five-level active front-end is realized by the converter topology proposed in chapter two. The converter is run and the performance of the drive is studied at various modulation indices and speeds of the motor. Various aspects like re-generation operation, acceleration and other aspects of the drive have been studied experimentally and the results are presented in detail. For experimental setup, Semikron SKM75GB12T4 IGBT modules have been used to realize the power topology. These IGBTs are driven by M56972L drivers. The control circuit is realized using TMS320F2812 DSP along with Xilinx Spartan 3 FPGA (XC3S200) has been used. The voltages and currents are sensed using LEM LV-20P and LA 55-P hall effect based sensors.

Neutral-point-clamped (NPC) three-level inverter is capable of handling higher dc bus voltage and producing output waveform of better quality than a conventional two-level inverter. The main objective of the present work is to analyze the existing PWM schemes for two-level and three-level inverters in terms of line current ripple, and to design new PWM techniques for the NPC inverter to reduce line current distortion. Various discontinuous PWM or bus-clamping PWM (BCPWM) methods for a two-level voltage source inverter are analyzed in terms of rms line current ripple, which is evaluated by integrating the error voltage (i.e. error between the applied and reference voltages). The BCPWM schemes can be broadly classified into continual-clamp PWM (CCPWM) and split-clamp PWM (SCPWM). It is shown that split-clamp PWM scheme leads to lower harmonic distortion than CCPWM scheme. Further, advanced bus-clamping PWM (ABCPWM) methods for a two-level inverter are also studied. These methods clamp each phase to the positive and negative DC terminals over certain intervals as in BCPWM schemes, and also switch each phase at double the nominal frequency in certain other intervals unlike in BCPWM. Analytical closed-form expressions are derived for the total rms harmonic distortion due to SCPWM, CCPWM and ABCPWM schemes. Existing sinusoidal and bus-clamping PWM schemes for three-level NPC inverters are also analyzed in the space vector domain. These methods are compared in terms of line current ripple analytically as well as experimentally. As earlier, closed-form expressions are derived for the harmonic distortion factors corresponding to centered space vector PWM (CSVPWM) and the various BCPWM methods. A three-level inverter can be viewed as an equivalent two-level inverter in each sixth of the fundamental cycle or hextant. This is widely used to simplify the control of an NPC inverter. Further, this approach makes it simple to extend the BCPWM and ABCPWM methods for two-level inverters to three-level inverters. Furthermore, the method of analysis of line current ripple for the two-level inverter can also be easily extended to the three-level case. The pivot vector, which is half the length of the longest voltage vectors produced by the NPC inverter, acts as an equivalent null vector for the conceptual two-level inverter. Each pivot vector can be produced by two inverter states termed as “pivot states”. Typically, in continuous modulation methods for NPC inverter such as sinusoidal PWM and centered space vector PWM, the switching sequence (i.e. the sequence in which the voltage vectors are applied) begins and ends with the same pivot vector in each subcycle, which is equivalent to a half-carrier cycle. To be more precise, the switching sequence starts with one pivot state and ends with the other in each subcycle. However, in case of BCPWM schemes, only one pivot state is used in a subcycle. The choice of pivot state results in a variety of BCPWM schemes for an NPC inverter. Different BCPWM schemes are evaluated in terms of rms line current ripple. The optimal BCPWM, which minimizes the rms current ripple, is determined for an NPC inverter, controlled as an equivalent two-level inverter. Further, four new switching sequences are proposed here for a three-level inverter, controlled as a conceptual two-level inverter. These sequences apply the pivot vector only once, but employ one of the other two vectors twice within the subcycle. These four switching sequences are termed as “ABCPWM sequences” for three-level inverter. These sequences exploit the flexibility available in the space vector approach to PWM to switch a phase more than once in a subcycle, which results in the application of an active vector twice within the subcycle. Influence of the proposed ABCPWM sequences on the line current ripple over a subcycle is studied. The various sequences are compared in terms of rms line current ripple over a subcycle. An analytical closed-form expression for rms line current ripple over a subcycle is derived in terms of reference magnitude, angle of reference voltage vector, and subcycle duration for each of the sequences. Further, closed-form expressions are also derived for the rms current ripple over a line cycle in terms of modulation index and subcycle duration, corresponding to the various sequences. The four proposed ABCPWM sequences for the NPC inverter can be grouped into two pairs of sequences. Each pair of sequences is shown to perform better than the individual sequences, if the two sequences are employed in appropriate spatial regions. Hence, with these two pairs of sequences, two hybrid PWM schemes are proposed. Finally, a hybrid PWM technique is proposed which employs all five sequences (conventional and proposed four sequences) in spatial regions where each performs the best. This is termed as “five-zone hybrid PWM”. The total harmonic distortion (THD) in the motor current, pertaining to all the proposed schemes, is studied theoretically over the entire range of linear modulation. The theoretical investigations are validated experimentally on a 2.2 kW, 415V, 4.9A, 50 Hz induction motor drive. The no-load current THD is measured over a range of fundamental frequency from 10 Hz to 50 Hz in steps of 2 Hz for the various PWM methods. Theoretical and experimental results bring out the reduction in current THD due to the proposed BCPWM schemes at fundamental frequencies of 45 Hz and above, compared to CSVPWM. The ABCPWM methods improve the performance at higher as well as lower modulation indices. Further improvement is achieved with the proposed five-zone hybrid PWM. At the rated frequency (50 Hz) of the drive, the improvement in line current distortion is around 36% with this hybrid PWM scheme over CSVPWM. The reduction in THD is also experimentally verified at different loads on the motor. The difference between the top and bottom capacitor voltages is measured at various operating conditions, corresponding to CSVPWM and the proposed schemes. No significant difference is observed in the dc neutral voltage shifts with the different proposed schemes and CSVPWM method. Thus, the proposed methods improve the THD at low and high speed ranges without appreciable worsening of the dc voltage unbalance.