In the thesis the design of process tolerant, use-aware radio-frequency front-ends were explored. First, the design of fuzzy logic and equation based controllers, which can adapt to multi-dimensional channel conditions, are proposed. Secondly, the thesis proves that adaptive systems can have multiple modes of operation depending upon the throughput requirements of the system. Two such modes were demonstrated: one optimizing the energy-per-bit (energy priority mode) and another achieving the lowest power consumption at the highest throughput (data priority mode). Finally, to achieve process tolerant channel adaptive operation a self-learning methodology is proposed which learns the optimal re-configuration setting for the system on-the-fly. Implications of the research are discussed and future avenues of further research are proposed.

The presentation highlights research on theory, design, EM modeling, fabrication, packaging, and measurement of GaAs Monolithic Microwave Integrated Circuits (MMICs). The goal of this work is to design MMIC LNAs with low noise figure, high gain, and wide bandwidth. The work aims to develop GaAs MMIC LNAs for the application of RF front-end receivers in radio telescopes. GaAs MMIC technology offers modern radio astronomy attractive solutions based on its advantage in terms of high operational frequency, low noise, excellent repeatability and high integration density. Theoretical investigations are performed, presenting the formulation and graphical methods, and focusing on a systematic method to design a low noise amplifier for the best noise, gain and input/output return loss. Additionally, an EM simulation method is utilized and successfully applied to MMIC designs. The effect of packaging including the wire bond and chassis is critical as the frequency increases. Therefore, it is modeled by full-wave analysis where the measured results verify the reliability of these models. The designed MMICs are validated by measurements of several prototypes, including three C/X band and one Q band MMIC LNAs. Moreover, comparison to similar industrial chips demonstrates the superiority of the proposed structures regarding bandwidth, noise and gain flatness, and making them suitable for use in radio astronomy receivers. / Graduate / 2020-05-01

Este trabalho apresenta o projeto de um bloco LNA-Misturador dentro de um mesmo circuito integrado para aplicações em um receptor Bluetooth 2;45GHz. Uma estratégia de projeto bem clara, concisa e com uma boa base física e matemática foi desenvolvida para auxiliar o processo de projeto de um bloco LNA-Misturador, composto por um LNA cascode em cascata com um misturador de chaveamento de corrente com entradas simples e degeneração indutiva nas fontes dos estágios de transcondutância. Esta estratégia foi adaptada de trabalhos apresentados na literatura. A estratégia de projeto proposta considera o compromisso entre ruído, linearidade, ganho, dissipação de potência, casamento de impedâncias e isolamento de portas, usando as dimensões dos dispositivos e condições de polarização como variáveis de projeto. Com base nesta estratégia se obteve um bloco LNA-Misturador que atinge algumas especificações propostas. Um bloco LNA-Misturador foi projetado e fabricado em uma tecnologia CMOS 0;35µm para validar a estratégia de projeto proposta. Além disso, para atingir os objetivos, durante o desenvolvimento deste trabalho foi dada atenção especial no projeto dos indutores. Foi projetado, fabricado e medido um chip de teste. Para tal fim foram aplicadas técnicas e estruturas de de-embedding nas medidas para conseguir resultados mais confiáveis. Os resultados experimentais obtidos para os indutores e os resultados preliminares do bloco LNA-Misturador s~ao satisfatórios de acordo com as especificações e os esperados das simulações. No entanto, os indutores integrados degradam significativamente o desempenho do bloco LNA-Misturador. Se forem usados processos de fabricação nos quais os indutores apresentem melhor desempenho, os resultados do bloco LNA-Misturador aplicando a estratégia de projeto desenvolvida neste trabalho podem ser melhorados. Finalmente, é importante ressaltar que a estratégia de projeto proposta neste trabalho já está sendo usada e adaptada em outros projetos com o propósito de melhorar os resultados obtidos, e conseguir auxiliar o processo de projeto deste tipo de blocos. / This work presents a fully integrated LNA-Mixer design for a Bluetooth receiver application at 2:45GHz. A concise design strategy with good physics and mathematics basis was developed to assist the design process of a LNA-Mixer block, formed by a cascode LNA in cascade to a single balanced current commutation Mixer with inductive degeneration. This strategy was adapted from literature and considers the trade-offs between noise, linearity, gain, power dissipation, impedance matching and ports isolation, using the device dimensions and bias conditions as design variables. Based on this strategy, the proposed LNA-Mixer design specifications were achieved. To validate the proposed design strategy, the LNA-Mixer were fabricated in a 0:35µm CMOS process. Furthermore, to achieve the specifications, during the development of this work a special attention to the RF CMOS inductors was given. A test chip was designed, fabricated and measured applying de-embedding structures to obtain more reliable results. The experimental results obtained for the inductors and the preliminary results for the LNA-Mixer are satisfactory compared to the specifications and as expected from simulations. However, the integrated inductors degrade the performance of the block significantly and if a manufacturing process in which the inductor has better performance is used, the resulting LNA-Mixer design applying the strategy developed in this work can be improved. Finally, it is important to highlight that the design strategy proposed in this work is already being used and adapted in other designs in order to improve the results, and to assist the design process of such blocks.

De nos jours, les modules hyperfréquences doivent de plus en plus présenter non seulement des performances électriques sans cesse améliorées mais aussi des fonctionnalités nouvelles ainsi que de fortes compacités, et des coûts de fabrication les plus réduits possibles. Les perspectives attractives apportées par l'utilisation des technologies SiGe permettent aujourd'hui d'envisager la réalisation de circuits intégrés jusqu'aux fréquences millimétriques tandis que, dans le même temps, le développement rapide des technologies MEMS RF permet de réaliser de nouvelles fonctionnalités au niveau des circuits radiofréquences. Dans la première partie de ce mémoire, nous proposons un concept d'amplificateur faible bruit reconfigurable en fréquence (HIPERLAN et BLUETOOTH), basé sur l'association des technologies SiGe et MEMS RF. Conception et performances simulées des amplificateurs élaborés à la fois pour une intégration monolithique et une autre par fil de souduresont alors présentées. La deuxième partie est entièrement consacrée à la conception et la réalisation des MEMS RF suivant les spécifications que nous avons établi lors de la première partie. Conception, réalisation et caractérisation des structures MEMS RF sont présentés, pour aboutir à l'obtention de performances situées à l'état de l'art pour des capacités autant séries que parallèles. La dernière partie, traite de l'assemblage entre les deux technologies MEMS et SiGe, avec trois études réalisées sur une intégration monolithique dite « Above IC », un assemblage par fils de soudure et un assemblage Flip Chip. Au final, des modules de test assemblés sont présentés et caractérisés

Cette thèse est une tentative vers la conception de la bande Ka émetteur-récepteur RF pour les réseaux de capteurs sans fil (WSN), pour lesquelles la consommation d'énergie, le coût et la taille sont des paramètres critiques. Au sens de la consommation d'énergie, un transmetteur RF est la partie la plus cruciale d'un nœud de capteur. Nous avons choisi STMicroelectronics 90nm global purpose (GP) pour atteindre la technologie CMOS à faible puissance, faible coût et de petite taille. Pour la première fois, nous avons introduit la bande Ka dans le context de WSN, a fin de bénéficier de l'immunité élevée du réseau et la petite taille antenne. Étant donné que la technologie que nous avons choisi et du kit associé fonderie de conception n'est pas pour la conception RF, nous avons été obligés de mettre au point un outil de conception individuelle pour la bande à ondes millimétriques. De cette façon, nous avons développé une solution simple et précise le modèle MOS transistor, comprenant charge et le modèle de capacité, modèle de bruit et le modèle complet des effets parasites. Nous avons proposé une nouvelle structure pour les inducteurs de la ligne de transmission et un modèle précis de RLGC a été développé pour la conception et la simulation de ces inducteurs. Et puis par la simulation de la pleine d'onde (full wave) électromagnétique dans le logiciel HFSS, nous avons extrait des parameters du modele d'incucteurs , et d'autres éléments passifs, telles que des pads RF et T-jonctions. Comme notre première expérience, nous avons conçu et optimisé une LNA à 30 GHz, en utilisant notre outil de conception. Le LNA conçu a été fabriqué dans STMicroelectronics 90nm global dans le processus de GP CMOS et a été mesurée dans le laboratoire IMEP. Les résultats des mesures montrent 10dB gain de puissance et de 4,8 dB figre bruit (noise figure) avec 4mW DC la consommation de puissance. Dans l'étape suivante, nous avons conçu et optimisé mieux 30GHz LNA. La simulation post-layout montre 13.9dB gain de puissance et 3.6d figre bruit, avec seulement 3 mW de consommation de puissance. Nous avons proposé un lien simple radio et un structure simple a ete presente pour le récepteur_émetteur. Dans le récepteur, nous avons utilisé la structure hétérodyne, ou dans la quelle nous avons utilise de l'idee de Mixer Harmonique paire et oscillateur couple, à surmonter de nombreux problèmes se pose en mm bande des ondes dans la technologie CMOS. Le Mixer a été conçu en utilisant les résultats d'analyse et de simulation dans le kit de conception de fonderie: 4dB gain de conversion et de 5,8 double side band figre de bruit avec 2.2Mw consommation de puissance, un excellent résultat en comparaison avec les œuvres similaires rapports comme IF Stage 2GHz qui a été conçu comme multi-slice-amplificateur de la chaîne de detection pour accroître (ugmenter)la performance du récepteur et d'atteindre plus faible consommation d'énergie. Enfin, le récepteur a été simulé dans MATLAB et--87dBm de sensibilité, 890KHz de bande passante, avec 6.65mW consommation d'énergie sont obtenus. L'émetteur a été conçu aussi simple que possible, en utilisant idée power oscillateur, délivrant 6mW puissance RF de l'antenne. L'émetteur a généralement les 25% de power efficacité qui est très bon résultat en comparaison avec les œuvres déclarées.

<p>This master thesis deals with the study of ultra low power Low Noise Amplifier (LNA) for use inmedical implant device. Usually, low power consumption is required for a long battery lifetime andlonger operation. The target technology is 90nm CMOS process.First basic principle of LNA is discussed. Then based on a literature review of LNA design, theproposed LNA is presented in sub-threshold region which reduce power consumption through scalingthe supply voltage and through scaling current.The circuit implementation and simulations is presented to testify the performance of LNA .Besides thepower consumption simulated under the typical supply voltage (1V), it is also measured under someother low supply voltages (down to 0.5V) to investigate the minimum power consumption and theminimum noise figure. Evaluation results show that at a supply voltage of 1V the LNA performs a totalpower consumption of 20mW and a noise of 1dB. Proper performance is achieved with a current ofdown to 200uA and supply voltage of down to 0.45V, and a total power consumption of 200uW</p>

Advances toward increased integration and complexity of radio frequency (RF) andmixed-signal integrated circuits reduce the effectiveness of contemporary testmethodologies and result in a rising cost of testing. The focus in this research is on thecircuit-level implementation of alternative test strategies for integrated wirelesstransceivers with the aim to lower test cost by eliminating the need for expensive RFequipment during production testing.The first circuit proposed in this thesis closes the signal path between the transmitterand receiver sections of integrated transceivers in test mode for bit error rate analysis atlow frequencies. Furthermore, the output power of this on-chip loopback block wasmade variable with the goal to allow gain and 1-dB compression point determination forthe RF front-end circuits with on-chip power detectors. The loopback block is intendedfor transceivers operating in the 1.9-2.4GHz range and it can compensate for transmitterreceiveroffset frequency differences from 40MHz to 200MHz. The measuredattenuation range of the 0.052mm2 loopback circuit in 0.13µm CMOS technology was 26-41dB with continuous control, but post-layout simulation results indicate that theattenuation range can be reduced to 11-27dB via optimizations.Another circuit presented in this thesis is a current generator for built-in testing ofimpedance-matched RF front-end circuits with current injection. Since this circuit hashigh output impedance (>1k up to 2.4GHz), it does not influence the input matchingnetwork of the low-noise amplifier (LNA) under test. A major advantage of the currentinjection method over the typical voltage-mode approach is that the built-in test canexpose fabrication defects in components of the matching network in addition to on-chipdevices. The current generator was employed together with two power detectors in arealization of a built-in test for a LNA with 14% layout area overhead in 0.13µm CMOStechnology (<1.5% for the 0.002mm2 current generator). The post-layout simulationresults showed that the LNA gain (S21) estimation with the external matching networkwas within 3.5% of the actual gain in the presence of process-voltage-temperaturevariations and power detector imprecision.

The objective of the proposed research is to understand the design and reliability of RF front-end building blocks using SOI CMOS and SiGe BiCMOS technologies for high dynamic-range applications. This research leads to a comprehensive understanding of dynamic range in SOI CMOS devices and contributes to knowledge leading to improvement in overall dynamic range and reliability of RF building blocks. While the performance of CMOS transistors has been improving naturally with scaling, this work aims to explore the possibilities of improvement in RF performance and reliability using standard layouts (that don't need process modifications). The total-ionizing dose tolerance of SOI CMOS devices has been understood with extensive measurements. Furthermore, the role of body contacts in SOI technology is understood for dynamic range performance improvement. In this work, CMOS low-noise amplifier design for high linearity WLAN applications and its integration with RF switch on the same chip is presented. The LNA and switches designed provide state-of-the-art performance in silicon based technologies. Further, the work aims to explore applications of SiGe HBT in the context of highly linear and reliable RF building blocks. The RF reliability of SiGe HBT based RF switches is investigated and compared with CMOS counterparts. The inverse-mode operation of SiGe HBT based switches is understood to give considerably higher linearity.

The objective of this dissertation is to develop key components of a CMOS heterodyne millimeter-wave receiver front end. Robust designs are necessary to overcome PVT variations as well as modeling inaccuracies, while with minimum power consumption overhead to facilitate low-power radio for portable applications. Heterodyne receiver topology is adopted because of its robust performances at millimeter-wave frequencies. Device models for both passive and active devices are developed and used in the circuit designs in this dissertation. Two low-noise amplifiers (LNAs) are developed in this dissertation. The first LNA features a proposed temperature-compensation biasing technique, which confines the gain variation within 5 dB for temperature variation from -5 to 85 Celsius degree. The measured gain and NF are 21 and 6.5 dB, respectively, for 49-mW power dissipation. The second LNA reveals a design technique to tolerate a low-accuracy model at millimeter-wave frequencies. Both LNAs provide full coverage of the FCC 60-GHz band (57-64 GHz). For the frequency generation circuits, both the IF QVCO and mm-wave VCO are investigated. The inherent bimodal oscillation of QVCOs is analyzed and, for the first time, a systematic measurement technique is proposed to intentionally control the oscillation mode. This technique is further utilized to extend the tuning range of the QVCO, which possesses dual tuning curves without penalty on phase noise. The measurement results of a 13-GHz QVCO in 90-nm CMOS reveals a 21.4% tuning range for continuously tuning from 11.7 to 14.5 GHz. The measured phase noise is -108 dBc/Hz at 1 MHz offset with a core power consumption of 10.8 mW. A millimeter-wave VCO is designed and fabricated in 65-nm CMOS. The VCO is fully characterized under voltage stress to examine the hot-carrier injection effects affecting the performance of a millimeter-wave VCO. The 41.6-47.4 GHz VCO is further integrated into a millimeter-wave down converter. The power-hungry buffer amplifiers are neglected by proper floor planning. Conversion loss of 1.4 dB is obtained with total power consumption of 72.5 mW. Lastly, a power management system consisting of low-dropout (LDO) regulators is designed and integrated in a 90-nm CMOS millimeter-wave transceiver to provide stable and low-noise supply voltages. Voltage variation issues are alleviated by the LDOs.

In this Master's thesis, a direct-conversion receiver front-end has been designed in a 0.18um CMOS technology. Direct-conversion receivers (DCR) have obvious advantages over the heterodyne counterpart. Since the intermediate frequency (IF) is zero, the problem of image is circumvented. As a result, no front-end image reject filter is required and the channel selection requires only a low-pass filter, which makes it easy to integrate directly on chip. However, the DCR also suffers from several drawbacks such as extreme sensitivity to DC offsets, 1/f noise, local oscillator (LO) leakage/radiation, front-end nonlinearity and I/Q mismatch. This implies very high demands on the DCR front-end. The front-end comprises a low-noise amplifier (LNA) and a mixer. Different LNA and mixer architectures has been studied and from the mentioned inherited problems with direct conversion, one proposal for a solution is a differential source degenerated LNA and a differential harmonic mixer, which has been designed and simulated. The LNA has a gain of 12dB, a noise figure of 3.6dB and provides a return loss better than -15dB. The overall noise figure of the signal path is 8dB and the overall IIP3 and IIP2 is -12dBm and 31dBm, respectively.